1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #ifndef KFD_IOCTL_H_INCLUDED 24 #define KFD_IOCTL_H_INCLUDED 25 26 #include <drm/drm.h> 27 #include <linux/ioctl.h> 28 29 /* 30 * - 1.1 - initial version 31 * - 1.3 - Add SMI events support 32 * - 1.4 - Indicate new SRAM EDC bit in device properties 33 * - 1.5 - Add SVM API 34 */ 35 #define KFD_IOCTL_MAJOR_VERSION 1 36 #define KFD_IOCTL_MINOR_VERSION 5 37 38 struct kfd_ioctl_get_version_args { 39 __u32 major_version; /* from KFD */ 40 __u32 minor_version; /* from KFD */ 41 }; 42 43 /* For kfd_ioctl_create_queue_args.queue_type. */ 44 #define KFD_IOC_QUEUE_TYPE_COMPUTE 0x0 45 #define KFD_IOC_QUEUE_TYPE_SDMA 0x1 46 #define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 0x2 47 #define KFD_IOC_QUEUE_TYPE_SDMA_XGMI 0x3 48 49 #define KFD_MAX_QUEUE_PERCENTAGE 100 50 #define KFD_MAX_QUEUE_PRIORITY 15 51 52 struct kfd_ioctl_create_queue_args { 53 __u64 ring_base_address; /* to KFD */ 54 __u64 write_pointer_address; /* from KFD */ 55 __u64 read_pointer_address; /* from KFD */ 56 __u64 doorbell_offset; /* from KFD */ 57 58 __u32 ring_size; /* to KFD */ 59 __u32 gpu_id; /* to KFD */ 60 __u32 queue_type; /* to KFD */ 61 __u32 queue_percentage; /* to KFD */ 62 __u32 queue_priority; /* to KFD */ 63 __u32 queue_id; /* from KFD */ 64 65 __u64 eop_buffer_address; /* to KFD */ 66 __u64 eop_buffer_size; /* to KFD */ 67 __u64 ctx_save_restore_address; /* to KFD */ 68 __u32 ctx_save_restore_size; /* to KFD */ 69 __u32 ctl_stack_size; /* to KFD */ 70 }; 71 72 struct kfd_ioctl_destroy_queue_args { 73 __u32 queue_id; /* to KFD */ 74 __u32 pad; 75 }; 76 77 struct kfd_ioctl_update_queue_args { 78 __u64 ring_base_address; /* to KFD */ 79 80 __u32 queue_id; /* to KFD */ 81 __u32 ring_size; /* to KFD */ 82 __u32 queue_percentage; /* to KFD */ 83 __u32 queue_priority; /* to KFD */ 84 }; 85 86 struct kfd_ioctl_set_cu_mask_args { 87 __u32 queue_id; /* to KFD */ 88 __u32 num_cu_mask; /* to KFD */ 89 __u64 cu_mask_ptr; /* to KFD */ 90 }; 91 92 struct kfd_ioctl_get_queue_wave_state_args { 93 __u64 ctl_stack_address; /* to KFD */ 94 __u32 ctl_stack_used_size; /* from KFD */ 95 __u32 save_area_used_size; /* from KFD */ 96 __u32 queue_id; /* to KFD */ 97 __u32 pad; 98 }; 99 100 /* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */ 101 #define KFD_IOC_CACHE_POLICY_COHERENT 0 102 #define KFD_IOC_CACHE_POLICY_NONCOHERENT 1 103 104 struct kfd_ioctl_set_memory_policy_args { 105 __u64 alternate_aperture_base; /* to KFD */ 106 __u64 alternate_aperture_size; /* to KFD */ 107 108 __u32 gpu_id; /* to KFD */ 109 __u32 default_policy; /* to KFD */ 110 __u32 alternate_policy; /* to KFD */ 111 __u32 pad; 112 }; 113 114 /* 115 * All counters are monotonic. They are used for profiling of compute jobs. 116 * The profiling is done by userspace. 117 * 118 * In case of GPU reset, the counter should not be affected. 119 */ 120 121 struct kfd_ioctl_get_clock_counters_args { 122 __u64 gpu_clock_counter; /* from KFD */ 123 __u64 cpu_clock_counter; /* from KFD */ 124 __u64 system_clock_counter; /* from KFD */ 125 __u64 system_clock_freq; /* from KFD */ 126 127 __u32 gpu_id; /* to KFD */ 128 __u32 pad; 129 }; 130 131 struct kfd_process_device_apertures { 132 __u64 lds_base; /* from KFD */ 133 __u64 lds_limit; /* from KFD */ 134 __u64 scratch_base; /* from KFD */ 135 __u64 scratch_limit; /* from KFD */ 136 __u64 gpuvm_base; /* from KFD */ 137 __u64 gpuvm_limit; /* from KFD */ 138 __u32 gpu_id; /* from KFD */ 139 __u32 pad; 140 }; 141 142 /* 143 * AMDKFD_IOC_GET_PROCESS_APERTURES is deprecated. Use 144 * AMDKFD_IOC_GET_PROCESS_APERTURES_NEW instead, which supports an 145 * unlimited number of GPUs. 146 */ 147 #define NUM_OF_SUPPORTED_GPUS 7 148 struct kfd_ioctl_get_process_apertures_args { 149 struct kfd_process_device_apertures 150 process_apertures[NUM_OF_SUPPORTED_GPUS];/* from KFD */ 151 152 /* from KFD, should be in the range [1 - NUM_OF_SUPPORTED_GPUS] */ 153 __u32 num_of_nodes; 154 __u32 pad; 155 }; 156 157 struct kfd_ioctl_get_process_apertures_new_args { 158 /* User allocated. Pointer to struct kfd_process_device_apertures 159 * filled in by Kernel 160 */ 161 __u64 kfd_process_device_apertures_ptr; 162 /* to KFD - indicates amount of memory present in 163 * kfd_process_device_apertures_ptr 164 * from KFD - Number of entries filled by KFD. 165 */ 166 __u32 num_of_nodes; 167 __u32 pad; 168 }; 169 170 #define MAX_ALLOWED_NUM_POINTS 100 171 #define MAX_ALLOWED_AW_BUFF_SIZE 4096 172 #define MAX_ALLOWED_WAC_BUFF_SIZE 128 173 174 struct kfd_ioctl_dbg_register_args { 175 __u32 gpu_id; /* to KFD */ 176 __u32 pad; 177 }; 178 179 struct kfd_ioctl_dbg_unregister_args { 180 __u32 gpu_id; /* to KFD */ 181 __u32 pad; 182 }; 183 184 struct kfd_ioctl_dbg_address_watch_args { 185 __u64 content_ptr; /* a pointer to the actual content */ 186 __u32 gpu_id; /* to KFD */ 187 __u32 buf_size_in_bytes; /*including gpu_id and buf_size */ 188 }; 189 190 struct kfd_ioctl_dbg_wave_control_args { 191 __u64 content_ptr; /* a pointer to the actual content */ 192 __u32 gpu_id; /* to KFD */ 193 __u32 buf_size_in_bytes; /*including gpu_id and buf_size */ 194 }; 195 196 /* Matching HSA_EVENTTYPE */ 197 #define KFD_IOC_EVENT_SIGNAL 0 198 #define KFD_IOC_EVENT_NODECHANGE 1 199 #define KFD_IOC_EVENT_DEVICESTATECHANGE 2 200 #define KFD_IOC_EVENT_HW_EXCEPTION 3 201 #define KFD_IOC_EVENT_SYSTEM_EVENT 4 202 #define KFD_IOC_EVENT_DEBUG_EVENT 5 203 #define KFD_IOC_EVENT_PROFILE_EVENT 6 204 #define KFD_IOC_EVENT_QUEUE_EVENT 7 205 #define KFD_IOC_EVENT_MEMORY 8 206 207 #define KFD_IOC_WAIT_RESULT_COMPLETE 0 208 #define KFD_IOC_WAIT_RESULT_TIMEOUT 1 209 #define KFD_IOC_WAIT_RESULT_FAIL 2 210 211 #define KFD_SIGNAL_EVENT_LIMIT 4096 212 213 /* For kfd_event_data.hw_exception_data.reset_type. */ 214 #define KFD_HW_EXCEPTION_WHOLE_GPU_RESET 0 215 #define KFD_HW_EXCEPTION_PER_ENGINE_RESET 1 216 217 /* For kfd_event_data.hw_exception_data.reset_cause. */ 218 #define KFD_HW_EXCEPTION_GPU_HANG 0 219 #define KFD_HW_EXCEPTION_ECC 1 220 221 /* For kfd_hsa_memory_exception_data.ErrorType */ 222 #define KFD_MEM_ERR_NO_RAS 0 223 #define KFD_MEM_ERR_SRAM_ECC 1 224 #define KFD_MEM_ERR_POISON_CONSUMED 2 225 #define KFD_MEM_ERR_GPU_HANG 3 226 227 struct kfd_ioctl_create_event_args { 228 __u64 event_page_offset; /* from KFD */ 229 __u32 event_trigger_data; /* from KFD - signal events only */ 230 __u32 event_type; /* to KFD */ 231 __u32 auto_reset; /* to KFD */ 232 __u32 node_id; /* to KFD - only valid for certain 233 event types */ 234 __u32 event_id; /* from KFD */ 235 __u32 event_slot_index; /* from KFD */ 236 }; 237 238 struct kfd_ioctl_destroy_event_args { 239 __u32 event_id; /* to KFD */ 240 __u32 pad; 241 }; 242 243 struct kfd_ioctl_set_event_args { 244 __u32 event_id; /* to KFD */ 245 __u32 pad; 246 }; 247 248 struct kfd_ioctl_reset_event_args { 249 __u32 event_id; /* to KFD */ 250 __u32 pad; 251 }; 252 253 struct kfd_memory_exception_failure { 254 __u32 NotPresent; /* Page not present or supervisor privilege */ 255 __u32 ReadOnly; /* Write access to a read-only page */ 256 __u32 NoExecute; /* Execute access to a page marked NX */ 257 __u32 imprecise; /* Can't determine the exact fault address */ 258 }; 259 260 /* memory exception data */ 261 struct kfd_hsa_memory_exception_data { 262 struct kfd_memory_exception_failure failure; 263 __u64 va; 264 __u32 gpu_id; 265 __u32 ErrorType; /* 0 = no RAS error, 266 * 1 = ECC_SRAM, 267 * 2 = Link_SYNFLOOD (poison), 268 * 3 = GPU hang (not attributable to a specific cause), 269 * other values reserved 270 */ 271 }; 272 273 /* hw exception data */ 274 struct kfd_hsa_hw_exception_data { 275 __u32 reset_type; 276 __u32 reset_cause; 277 __u32 memory_lost; 278 __u32 gpu_id; 279 }; 280 281 /* Event data */ 282 struct kfd_event_data { 283 union { 284 struct kfd_hsa_memory_exception_data memory_exception_data; 285 struct kfd_hsa_hw_exception_data hw_exception_data; 286 }; /* From KFD */ 287 __u64 kfd_event_data_ext; /* pointer to an extension structure 288 for future exception types */ 289 __u32 event_id; /* to KFD */ 290 __u32 pad; 291 }; 292 293 struct kfd_ioctl_wait_events_args { 294 __u64 events_ptr; /* pointed to struct 295 kfd_event_data array, to KFD */ 296 __u32 num_events; /* to KFD */ 297 __u32 wait_for_all; /* to KFD */ 298 __u32 timeout; /* to KFD */ 299 __u32 wait_result; /* from KFD */ 300 }; 301 302 struct kfd_ioctl_set_scratch_backing_va_args { 303 __u64 va_addr; /* to KFD */ 304 __u32 gpu_id; /* to KFD */ 305 __u32 pad; 306 }; 307 308 struct kfd_ioctl_get_tile_config_args { 309 /* to KFD: pointer to tile array */ 310 __u64 tile_config_ptr; 311 /* to KFD: pointer to macro tile array */ 312 __u64 macro_tile_config_ptr; 313 /* to KFD: array size allocated by user mode 314 * from KFD: array size filled by kernel 315 */ 316 __u32 num_tile_configs; 317 /* to KFD: array size allocated by user mode 318 * from KFD: array size filled by kernel 319 */ 320 __u32 num_macro_tile_configs; 321 322 __u32 gpu_id; /* to KFD */ 323 __u32 gb_addr_config; /* from KFD */ 324 __u32 num_banks; /* from KFD */ 325 __u32 num_ranks; /* from KFD */ 326 /* struct size can be extended later if needed 327 * without breaking ABI compatibility 328 */ 329 }; 330 331 struct kfd_ioctl_set_trap_handler_args { 332 __u64 tba_addr; /* to KFD */ 333 __u64 tma_addr; /* to KFD */ 334 __u32 gpu_id; /* to KFD */ 335 __u32 pad; 336 }; 337 338 struct kfd_ioctl_acquire_vm_args { 339 __u32 drm_fd; /* to KFD */ 340 __u32 gpu_id; /* to KFD */ 341 }; 342 343 /* Allocation flags: memory types */ 344 #define KFD_IOC_ALLOC_MEM_FLAGS_VRAM (1 << 0) 345 #define KFD_IOC_ALLOC_MEM_FLAGS_GTT (1 << 1) 346 #define KFD_IOC_ALLOC_MEM_FLAGS_USERPTR (1 << 2) 347 #define KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL (1 << 3) 348 #define KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP (1 << 4) 349 /* Allocation flags: attributes/access options */ 350 #define KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE (1 << 31) 351 #define KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE (1 << 30) 352 #define KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC (1 << 29) 353 #define KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE (1 << 28) 354 #define KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM (1 << 27) 355 #define KFD_IOC_ALLOC_MEM_FLAGS_COHERENT (1 << 26) 356 #define KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED (1 << 25) 357 358 /* Allocate memory for later SVM (shared virtual memory) mapping. 359 * 360 * @va_addr: virtual address of the memory to be allocated 361 * all later mappings on all GPUs will use this address 362 * @size: size in bytes 363 * @handle: buffer handle returned to user mode, used to refer to 364 * this allocation for mapping, unmapping and freeing 365 * @mmap_offset: for CPU-mapping the allocation by mmapping a render node 366 * for userptrs this is overloaded to specify the CPU address 367 * @gpu_id: device identifier 368 * @flags: memory type and attributes. See KFD_IOC_ALLOC_MEM_FLAGS above 369 */ 370 struct kfd_ioctl_alloc_memory_of_gpu_args { 371 __u64 va_addr; /* to KFD */ 372 __u64 size; /* to KFD */ 373 __u64 handle; /* from KFD */ 374 __u64 mmap_offset; /* to KFD (userptr), from KFD (mmap offset) */ 375 __u32 gpu_id; /* to KFD */ 376 __u32 flags; 377 }; 378 379 /* Free memory allocated with kfd_ioctl_alloc_memory_of_gpu 380 * 381 * @handle: memory handle returned by alloc 382 */ 383 struct kfd_ioctl_free_memory_of_gpu_args { 384 __u64 handle; /* to KFD */ 385 }; 386 387 /* Map memory to one or more GPUs 388 * 389 * @handle: memory handle returned by alloc 390 * @device_ids_array_ptr: array of gpu_ids (__u32 per device) 391 * @n_devices: number of devices in the array 392 * @n_success: number of devices mapped successfully 393 * 394 * @n_success returns information to the caller how many devices from 395 * the start of the array have mapped the buffer successfully. It can 396 * be passed into a subsequent retry call to skip those devices. For 397 * the first call the caller should initialize it to 0. 398 * 399 * If the ioctl completes with return code 0 (success), n_success == 400 * n_devices. 401 */ 402 struct kfd_ioctl_map_memory_to_gpu_args { 403 __u64 handle; /* to KFD */ 404 __u64 device_ids_array_ptr; /* to KFD */ 405 __u32 n_devices; /* to KFD */ 406 __u32 n_success; /* to/from KFD */ 407 }; 408 409 /* Unmap memory from one or more GPUs 410 * 411 * same arguments as for mapping 412 */ 413 struct kfd_ioctl_unmap_memory_from_gpu_args { 414 __u64 handle; /* to KFD */ 415 __u64 device_ids_array_ptr; /* to KFD */ 416 __u32 n_devices; /* to KFD */ 417 __u32 n_success; /* to/from KFD */ 418 }; 419 420 /* Allocate GWS for specific queue 421 * 422 * @queue_id: queue's id that GWS is allocated for 423 * @num_gws: how many GWS to allocate 424 * @first_gws: index of the first GWS allocated. 425 * only support contiguous GWS allocation 426 */ 427 struct kfd_ioctl_alloc_queue_gws_args { 428 __u32 queue_id; /* to KFD */ 429 __u32 num_gws; /* to KFD */ 430 __u32 first_gws; /* from KFD */ 431 __u32 pad; 432 }; 433 434 struct kfd_ioctl_get_dmabuf_info_args { 435 __u64 size; /* from KFD */ 436 __u64 metadata_ptr; /* to KFD */ 437 __u32 metadata_size; /* to KFD (space allocated by user) 438 * from KFD (actual metadata size) 439 */ 440 __u32 gpu_id; /* from KFD */ 441 __u32 flags; /* from KFD (KFD_IOC_ALLOC_MEM_FLAGS) */ 442 __u32 dmabuf_fd; /* to KFD */ 443 }; 444 445 struct kfd_ioctl_import_dmabuf_args { 446 __u64 va_addr; /* to KFD */ 447 __u64 handle; /* from KFD */ 448 __u32 gpu_id; /* to KFD */ 449 __u32 dmabuf_fd; /* to KFD */ 450 }; 451 452 /* 453 * KFD SMI(System Management Interface) events 454 */ 455 enum kfd_smi_event { 456 KFD_SMI_EVENT_NONE = 0, /* not used */ 457 KFD_SMI_EVENT_VMFAULT = 1, /* event start counting at 1 */ 458 KFD_SMI_EVENT_THERMAL_THROTTLE = 2, 459 KFD_SMI_EVENT_GPU_PRE_RESET = 3, 460 KFD_SMI_EVENT_GPU_POST_RESET = 4, 461 }; 462 463 #define KFD_SMI_EVENT_MASK_FROM_INDEX(i) (1ULL << ((i) - 1)) 464 465 struct kfd_ioctl_smi_events_args { 466 __u32 gpuid; /* to KFD */ 467 __u32 anon_fd; /* from KFD */ 468 }; 469 470 /* Register offset inside the remapped mmio page 471 */ 472 enum kfd_mmio_remap { 473 KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL = 0, 474 KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL = 4, 475 }; 476 477 /* Guarantee host access to memory */ 478 #define KFD_IOCTL_SVM_FLAG_HOST_ACCESS 0x00000001 479 /* Fine grained coherency between all devices with access */ 480 #define KFD_IOCTL_SVM_FLAG_COHERENT 0x00000002 481 /* Use any GPU in same hive as preferred device */ 482 #define KFD_IOCTL_SVM_FLAG_HIVE_LOCAL 0x00000004 483 /* GPUs only read, allows replication */ 484 #define KFD_IOCTL_SVM_FLAG_GPU_RO 0x00000008 485 /* Allow execution on GPU */ 486 #define KFD_IOCTL_SVM_FLAG_GPU_EXEC 0x00000010 487 /* GPUs mostly read, may allow similar optimizations as RO, but writes fault */ 488 #define KFD_IOCTL_SVM_FLAG_GPU_READ_MOSTLY 0x00000020 489 490 /** 491 * kfd_ioctl_svm_op - SVM ioctl operations 492 * 493 * @KFD_IOCTL_SVM_OP_SET_ATTR: Modify one or more attributes 494 * @KFD_IOCTL_SVM_OP_GET_ATTR: Query one or more attributes 495 */ 496 enum kfd_ioctl_svm_op { 497 KFD_IOCTL_SVM_OP_SET_ATTR, 498 KFD_IOCTL_SVM_OP_GET_ATTR 499 }; 500 501 /** kfd_ioctl_svm_location - Enum for preferred and prefetch locations 502 * 503 * GPU IDs are used to specify GPUs as preferred and prefetch locations. 504 * Below definitions are used for system memory or for leaving the preferred 505 * location unspecified. 506 */ 507 enum kfd_ioctl_svm_location { 508 KFD_IOCTL_SVM_LOCATION_SYSMEM = 0, 509 KFD_IOCTL_SVM_LOCATION_UNDEFINED = 0xffffffff 510 }; 511 512 /** 513 * kfd_ioctl_svm_attr_type - SVM attribute types 514 * 515 * @KFD_IOCTL_SVM_ATTR_PREFERRED_LOC: gpuid of the preferred location, 0 for 516 * system memory 517 * @KFD_IOCTL_SVM_ATTR_PREFETCH_LOC: gpuid of the prefetch location, 0 for 518 * system memory. Setting this triggers an 519 * immediate prefetch (migration). 520 * @KFD_IOCTL_SVM_ATTR_ACCESS: 521 * @KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE: 522 * @KFD_IOCTL_SVM_ATTR_NO_ACCESS: specify memory access for the gpuid given 523 * by the attribute value 524 * @KFD_IOCTL_SVM_ATTR_SET_FLAGS: bitmask of flags to set (see 525 * KFD_IOCTL_SVM_FLAG_...) 526 * @KFD_IOCTL_SVM_ATTR_CLR_FLAGS: bitmask of flags to clear 527 * @KFD_IOCTL_SVM_ATTR_GRANULARITY: migration granularity 528 * (log2 num pages) 529 */ 530 enum kfd_ioctl_svm_attr_type { 531 KFD_IOCTL_SVM_ATTR_PREFERRED_LOC, 532 KFD_IOCTL_SVM_ATTR_PREFETCH_LOC, 533 KFD_IOCTL_SVM_ATTR_ACCESS, 534 KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE, 535 KFD_IOCTL_SVM_ATTR_NO_ACCESS, 536 KFD_IOCTL_SVM_ATTR_SET_FLAGS, 537 KFD_IOCTL_SVM_ATTR_CLR_FLAGS, 538 KFD_IOCTL_SVM_ATTR_GRANULARITY 539 }; 540 541 /** 542 * kfd_ioctl_svm_attribute - Attributes as pairs of type and value 543 * 544 * The meaning of the @value depends on the attribute type. 545 * 546 * @type: attribute type (see enum @kfd_ioctl_svm_attr_type) 547 * @value: attribute value 548 */ 549 struct kfd_ioctl_svm_attribute { 550 __u32 type; 551 __u32 value; 552 }; 553 554 /** 555 * kfd_ioctl_svm_args - Arguments for SVM ioctl 556 * 557 * @op specifies the operation to perform (see enum 558 * @kfd_ioctl_svm_op). @start_addr and @size are common for all 559 * operations. 560 * 561 * A variable number of attributes can be given in @attrs. 562 * @nattr specifies the number of attributes. New attributes can be 563 * added in the future without breaking the ABI. If unknown attributes 564 * are given, the function returns -EINVAL. 565 * 566 * @KFD_IOCTL_SVM_OP_SET_ATTR sets attributes for a virtual address 567 * range. It may overlap existing virtual address ranges. If it does, 568 * the existing ranges will be split such that the attribute changes 569 * only apply to the specified address range. 570 * 571 * @KFD_IOCTL_SVM_OP_GET_ATTR returns the intersection of attributes 572 * over all memory in the given range and returns the result as the 573 * attribute value. If different pages have different preferred or 574 * prefetch locations, 0xffffffff will be returned for 575 * @KFD_IOCTL_SVM_ATTR_PREFERRED_LOC or 576 * @KFD_IOCTL_SVM_ATTR_PREFETCH_LOC resepctively. For 577 * @KFD_IOCTL_SVM_ATTR_SET_FLAGS, flags of all pages will be 578 * aggregated by bitwise AND. The minimum migration granularity 579 * throughout the range will be returned for 580 * @KFD_IOCTL_SVM_ATTR_GRANULARITY. 581 * 582 * Querying of accessibility attributes works by initializing the 583 * attribute type to @KFD_IOCTL_SVM_ATTR_ACCESS and the value to the 584 * GPUID being queried. Multiple attributes can be given to allow 585 * querying multiple GPUIDs. The ioctl function overwrites the 586 * attribute type to indicate the access for the specified GPU. 587 * 588 * @KFD_IOCTL_SVM_ATTR_CLR_FLAGS is invalid for 589 * @KFD_IOCTL_SVM_OP_GET_ATTR. 590 */ 591 struct kfd_ioctl_svm_args { 592 __u64 start_addr; 593 __u64 size; 594 __u32 op; 595 __u32 nattr; 596 /* Variable length array of attributes */ 597 struct kfd_ioctl_svm_attribute attrs[0]; 598 }; 599 600 /** 601 * kfd_ioctl_set_xnack_mode_args - Arguments for set_xnack_mode 602 * 603 * @xnack_enabled: [in/out] Whether to enable XNACK mode for this process 604 * 605 * @xnack_enabled indicates whether recoverable page faults should be 606 * enabled for the current process. 0 means disabled, positive means 607 * enabled, negative means leave unchanged. If enabled, virtual address 608 * translations on GFXv9 and later AMD GPUs can return XNACK and retry 609 * the access until a valid PTE is available. This is used to implement 610 * device page faults. 611 * 612 * On output, @xnack_enabled returns the (new) current mode (0 or 613 * positive). Therefore, a negative input value can be used to query 614 * the current mode without changing it. 615 * 616 * The XNACK mode fundamentally changes the way SVM managed memory works 617 * in the driver, with subtle effects on application performance and 618 * functionality. 619 * 620 * Enabling XNACK mode requires shader programs to be compiled 621 * differently. Furthermore, not all GPUs support changing the mode 622 * per-process. Therefore changing the mode is only allowed while no 623 * user mode queues exist in the process. This ensure that no shader 624 * code is running that may be compiled for the wrong mode. And GPUs 625 * that cannot change to the requested mode will prevent the XNACK 626 * mode from occurring. All GPUs used by the process must be in the 627 * same XNACK mode. 628 * 629 * GFXv8 or older GPUs do not support 48 bit virtual addresses or SVM. 630 * Therefore those GPUs are not considered for the XNACK mode switch. 631 * 632 * Return: 0 on success, -errno on failure 633 */ 634 struct kfd_ioctl_set_xnack_mode_args { 635 __s32 xnack_enabled; 636 }; 637 638 #define AMDKFD_IOCTL_BASE 'K' 639 #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) 640 #define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type) 641 #define AMDKFD_IOW(nr, type) _IOW(AMDKFD_IOCTL_BASE, nr, type) 642 #define AMDKFD_IOWR(nr, type) _IOWR(AMDKFD_IOCTL_BASE, nr, type) 643 644 #define AMDKFD_IOC_GET_VERSION \ 645 AMDKFD_IOR(0x01, struct kfd_ioctl_get_version_args) 646 647 #define AMDKFD_IOC_CREATE_QUEUE \ 648 AMDKFD_IOWR(0x02, struct kfd_ioctl_create_queue_args) 649 650 #define AMDKFD_IOC_DESTROY_QUEUE \ 651 AMDKFD_IOWR(0x03, struct kfd_ioctl_destroy_queue_args) 652 653 #define AMDKFD_IOC_SET_MEMORY_POLICY \ 654 AMDKFD_IOW(0x04, struct kfd_ioctl_set_memory_policy_args) 655 656 #define AMDKFD_IOC_GET_CLOCK_COUNTERS \ 657 AMDKFD_IOWR(0x05, struct kfd_ioctl_get_clock_counters_args) 658 659 #define AMDKFD_IOC_GET_PROCESS_APERTURES \ 660 AMDKFD_IOR(0x06, struct kfd_ioctl_get_process_apertures_args) 661 662 #define AMDKFD_IOC_UPDATE_QUEUE \ 663 AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args) 664 665 #define AMDKFD_IOC_CREATE_EVENT \ 666 AMDKFD_IOWR(0x08, struct kfd_ioctl_create_event_args) 667 668 #define AMDKFD_IOC_DESTROY_EVENT \ 669 AMDKFD_IOW(0x09, struct kfd_ioctl_destroy_event_args) 670 671 #define AMDKFD_IOC_SET_EVENT \ 672 AMDKFD_IOW(0x0A, struct kfd_ioctl_set_event_args) 673 674 #define AMDKFD_IOC_RESET_EVENT \ 675 AMDKFD_IOW(0x0B, struct kfd_ioctl_reset_event_args) 676 677 #define AMDKFD_IOC_WAIT_EVENTS \ 678 AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args) 679 680 #define AMDKFD_IOC_DBG_REGISTER \ 681 AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args) 682 683 #define AMDKFD_IOC_DBG_UNREGISTER \ 684 AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args) 685 686 #define AMDKFD_IOC_DBG_ADDRESS_WATCH \ 687 AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args) 688 689 #define AMDKFD_IOC_DBG_WAVE_CONTROL \ 690 AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args) 691 692 #define AMDKFD_IOC_SET_SCRATCH_BACKING_VA \ 693 AMDKFD_IOWR(0x11, struct kfd_ioctl_set_scratch_backing_va_args) 694 695 #define AMDKFD_IOC_GET_TILE_CONFIG \ 696 AMDKFD_IOWR(0x12, struct kfd_ioctl_get_tile_config_args) 697 698 #define AMDKFD_IOC_SET_TRAP_HANDLER \ 699 AMDKFD_IOW(0x13, struct kfd_ioctl_set_trap_handler_args) 700 701 #define AMDKFD_IOC_GET_PROCESS_APERTURES_NEW \ 702 AMDKFD_IOWR(0x14, \ 703 struct kfd_ioctl_get_process_apertures_new_args) 704 705 #define AMDKFD_IOC_ACQUIRE_VM \ 706 AMDKFD_IOW(0x15, struct kfd_ioctl_acquire_vm_args) 707 708 #define AMDKFD_IOC_ALLOC_MEMORY_OF_GPU \ 709 AMDKFD_IOWR(0x16, struct kfd_ioctl_alloc_memory_of_gpu_args) 710 711 #define AMDKFD_IOC_FREE_MEMORY_OF_GPU \ 712 AMDKFD_IOW(0x17, struct kfd_ioctl_free_memory_of_gpu_args) 713 714 #define AMDKFD_IOC_MAP_MEMORY_TO_GPU \ 715 AMDKFD_IOWR(0x18, struct kfd_ioctl_map_memory_to_gpu_args) 716 717 #define AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU \ 718 AMDKFD_IOWR(0x19, struct kfd_ioctl_unmap_memory_from_gpu_args) 719 720 #define AMDKFD_IOC_SET_CU_MASK \ 721 AMDKFD_IOW(0x1A, struct kfd_ioctl_set_cu_mask_args) 722 723 #define AMDKFD_IOC_GET_QUEUE_WAVE_STATE \ 724 AMDKFD_IOWR(0x1B, struct kfd_ioctl_get_queue_wave_state_args) 725 726 #define AMDKFD_IOC_GET_DMABUF_INFO \ 727 AMDKFD_IOWR(0x1C, struct kfd_ioctl_get_dmabuf_info_args) 728 729 #define AMDKFD_IOC_IMPORT_DMABUF \ 730 AMDKFD_IOWR(0x1D, struct kfd_ioctl_import_dmabuf_args) 731 732 #define AMDKFD_IOC_ALLOC_QUEUE_GWS \ 733 AMDKFD_IOWR(0x1E, struct kfd_ioctl_alloc_queue_gws_args) 734 735 #define AMDKFD_IOC_SMI_EVENTS \ 736 AMDKFD_IOWR(0x1F, struct kfd_ioctl_smi_events_args) 737 738 #define AMDKFD_IOC_SVM AMDKFD_IOWR(0x20, struct kfd_ioctl_svm_args) 739 740 #define AMDKFD_IOC_SET_XNACK_MODE \ 741 AMDKFD_IOWR(0x21, struct kfd_ioctl_set_xnack_mode_args) 742 743 #define AMDKFD_COMMAND_START 0x01 744 #define AMDKFD_COMMAND_END 0x22 745 746 #endif 747