1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #ifndef KFD_IOCTL_H_INCLUDED 24 #define KFD_IOCTL_H_INCLUDED 25 26 #include <drm/drm.h> 27 #include <linux/ioctl.h> 28 29 /* 30 * - 1.1 - initial version 31 * - 1.3 - Add SMI events support 32 * - 1.4 - Indicate new SRAM EDC bit in device properties 33 * - 1.5 - Add SVM API 34 * - 1.6 - Query clear flags in SVM get_attr API 35 * - 1.7 - Checkpoint Restore (CRIU) API 36 * - 1.8 - CRIU - Support for SDMA transfers with GTT BOs 37 * - 1.9 - Add available memory ioctl 38 * - 1.10 - Add SMI profiler event log 39 */ 40 #define KFD_IOCTL_MAJOR_VERSION 1 41 #define KFD_IOCTL_MINOR_VERSION 10 42 43 struct kfd_ioctl_get_version_args { 44 __u32 major_version; /* from KFD */ 45 __u32 minor_version; /* from KFD */ 46 }; 47 48 /* For kfd_ioctl_create_queue_args.queue_type. */ 49 #define KFD_IOC_QUEUE_TYPE_COMPUTE 0x0 50 #define KFD_IOC_QUEUE_TYPE_SDMA 0x1 51 #define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 0x2 52 #define KFD_IOC_QUEUE_TYPE_SDMA_XGMI 0x3 53 54 #define KFD_MAX_QUEUE_PERCENTAGE 100 55 #define KFD_MAX_QUEUE_PRIORITY 15 56 57 struct kfd_ioctl_create_queue_args { 58 __u64 ring_base_address; /* to KFD */ 59 __u64 write_pointer_address; /* from KFD */ 60 __u64 read_pointer_address; /* from KFD */ 61 __u64 doorbell_offset; /* from KFD */ 62 63 __u32 ring_size; /* to KFD */ 64 __u32 gpu_id; /* to KFD */ 65 __u32 queue_type; /* to KFD */ 66 __u32 queue_percentage; /* to KFD */ 67 __u32 queue_priority; /* to KFD */ 68 __u32 queue_id; /* from KFD */ 69 70 __u64 eop_buffer_address; /* to KFD */ 71 __u64 eop_buffer_size; /* to KFD */ 72 __u64 ctx_save_restore_address; /* to KFD */ 73 __u32 ctx_save_restore_size; /* to KFD */ 74 __u32 ctl_stack_size; /* to KFD */ 75 }; 76 77 struct kfd_ioctl_destroy_queue_args { 78 __u32 queue_id; /* to KFD */ 79 __u32 pad; 80 }; 81 82 struct kfd_ioctl_update_queue_args { 83 __u64 ring_base_address; /* to KFD */ 84 85 __u32 queue_id; /* to KFD */ 86 __u32 ring_size; /* to KFD */ 87 __u32 queue_percentage; /* to KFD */ 88 __u32 queue_priority; /* to KFD */ 89 }; 90 91 struct kfd_ioctl_set_cu_mask_args { 92 __u32 queue_id; /* to KFD */ 93 __u32 num_cu_mask; /* to KFD */ 94 __u64 cu_mask_ptr; /* to KFD */ 95 }; 96 97 struct kfd_ioctl_get_queue_wave_state_args { 98 __u64 ctl_stack_address; /* to KFD */ 99 __u32 ctl_stack_used_size; /* from KFD */ 100 __u32 save_area_used_size; /* from KFD */ 101 __u32 queue_id; /* to KFD */ 102 __u32 pad; 103 }; 104 105 struct kfd_ioctl_get_available_memory_args { 106 __u64 available; /* from KFD */ 107 __u32 gpu_id; /* to KFD */ 108 __u32 pad; 109 }; 110 111 /* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */ 112 #define KFD_IOC_CACHE_POLICY_COHERENT 0 113 #define KFD_IOC_CACHE_POLICY_NONCOHERENT 1 114 115 struct kfd_ioctl_set_memory_policy_args { 116 __u64 alternate_aperture_base; /* to KFD */ 117 __u64 alternate_aperture_size; /* to KFD */ 118 119 __u32 gpu_id; /* to KFD */ 120 __u32 default_policy; /* to KFD */ 121 __u32 alternate_policy; /* to KFD */ 122 __u32 pad; 123 }; 124 125 /* 126 * All counters are monotonic. They are used for profiling of compute jobs. 127 * The profiling is done by userspace. 128 * 129 * In case of GPU reset, the counter should not be affected. 130 */ 131 132 struct kfd_ioctl_get_clock_counters_args { 133 __u64 gpu_clock_counter; /* from KFD */ 134 __u64 cpu_clock_counter; /* from KFD */ 135 __u64 system_clock_counter; /* from KFD */ 136 __u64 system_clock_freq; /* from KFD */ 137 138 __u32 gpu_id; /* to KFD */ 139 __u32 pad; 140 }; 141 142 struct kfd_process_device_apertures { 143 __u64 lds_base; /* from KFD */ 144 __u64 lds_limit; /* from KFD */ 145 __u64 scratch_base; /* from KFD */ 146 __u64 scratch_limit; /* from KFD */ 147 __u64 gpuvm_base; /* from KFD */ 148 __u64 gpuvm_limit; /* from KFD */ 149 __u32 gpu_id; /* from KFD */ 150 __u32 pad; 151 }; 152 153 /* 154 * AMDKFD_IOC_GET_PROCESS_APERTURES is deprecated. Use 155 * AMDKFD_IOC_GET_PROCESS_APERTURES_NEW instead, which supports an 156 * unlimited number of GPUs. 157 */ 158 #define NUM_OF_SUPPORTED_GPUS 7 159 struct kfd_ioctl_get_process_apertures_args { 160 struct kfd_process_device_apertures 161 process_apertures[NUM_OF_SUPPORTED_GPUS];/* from KFD */ 162 163 /* from KFD, should be in the range [1 - NUM_OF_SUPPORTED_GPUS] */ 164 __u32 num_of_nodes; 165 __u32 pad; 166 }; 167 168 struct kfd_ioctl_get_process_apertures_new_args { 169 /* User allocated. Pointer to struct kfd_process_device_apertures 170 * filled in by Kernel 171 */ 172 __u64 kfd_process_device_apertures_ptr; 173 /* to KFD - indicates amount of memory present in 174 * kfd_process_device_apertures_ptr 175 * from KFD - Number of entries filled by KFD. 176 */ 177 __u32 num_of_nodes; 178 __u32 pad; 179 }; 180 181 #define MAX_ALLOWED_NUM_POINTS 100 182 #define MAX_ALLOWED_AW_BUFF_SIZE 4096 183 #define MAX_ALLOWED_WAC_BUFF_SIZE 128 184 185 struct kfd_ioctl_dbg_register_args { 186 __u32 gpu_id; /* to KFD */ 187 __u32 pad; 188 }; 189 190 struct kfd_ioctl_dbg_unregister_args { 191 __u32 gpu_id; /* to KFD */ 192 __u32 pad; 193 }; 194 195 struct kfd_ioctl_dbg_address_watch_args { 196 __u64 content_ptr; /* a pointer to the actual content */ 197 __u32 gpu_id; /* to KFD */ 198 __u32 buf_size_in_bytes; /*including gpu_id and buf_size */ 199 }; 200 201 struct kfd_ioctl_dbg_wave_control_args { 202 __u64 content_ptr; /* a pointer to the actual content */ 203 __u32 gpu_id; /* to KFD */ 204 __u32 buf_size_in_bytes; /*including gpu_id and buf_size */ 205 }; 206 207 #define KFD_INVALID_FD 0xffffffff 208 209 /* Matching HSA_EVENTTYPE */ 210 #define KFD_IOC_EVENT_SIGNAL 0 211 #define KFD_IOC_EVENT_NODECHANGE 1 212 #define KFD_IOC_EVENT_DEVICESTATECHANGE 2 213 #define KFD_IOC_EVENT_HW_EXCEPTION 3 214 #define KFD_IOC_EVENT_SYSTEM_EVENT 4 215 #define KFD_IOC_EVENT_DEBUG_EVENT 5 216 #define KFD_IOC_EVENT_PROFILE_EVENT 6 217 #define KFD_IOC_EVENT_QUEUE_EVENT 7 218 #define KFD_IOC_EVENT_MEMORY 8 219 220 #define KFD_IOC_WAIT_RESULT_COMPLETE 0 221 #define KFD_IOC_WAIT_RESULT_TIMEOUT 1 222 #define KFD_IOC_WAIT_RESULT_FAIL 2 223 224 #define KFD_SIGNAL_EVENT_LIMIT 4096 225 226 /* For kfd_event_data.hw_exception_data.reset_type. */ 227 #define KFD_HW_EXCEPTION_WHOLE_GPU_RESET 0 228 #define KFD_HW_EXCEPTION_PER_ENGINE_RESET 1 229 230 /* For kfd_event_data.hw_exception_data.reset_cause. */ 231 #define KFD_HW_EXCEPTION_GPU_HANG 0 232 #define KFD_HW_EXCEPTION_ECC 1 233 234 /* For kfd_hsa_memory_exception_data.ErrorType */ 235 #define KFD_MEM_ERR_NO_RAS 0 236 #define KFD_MEM_ERR_SRAM_ECC 1 237 #define KFD_MEM_ERR_POISON_CONSUMED 2 238 #define KFD_MEM_ERR_GPU_HANG 3 239 240 struct kfd_ioctl_create_event_args { 241 __u64 event_page_offset; /* from KFD */ 242 __u32 event_trigger_data; /* from KFD - signal events only */ 243 __u32 event_type; /* to KFD */ 244 __u32 auto_reset; /* to KFD */ 245 __u32 node_id; /* to KFD - only valid for certain 246 event types */ 247 __u32 event_id; /* from KFD */ 248 __u32 event_slot_index; /* from KFD */ 249 }; 250 251 struct kfd_ioctl_destroy_event_args { 252 __u32 event_id; /* to KFD */ 253 __u32 pad; 254 }; 255 256 struct kfd_ioctl_set_event_args { 257 __u32 event_id; /* to KFD */ 258 __u32 pad; 259 }; 260 261 struct kfd_ioctl_reset_event_args { 262 __u32 event_id; /* to KFD */ 263 __u32 pad; 264 }; 265 266 struct kfd_memory_exception_failure { 267 __u32 NotPresent; /* Page not present or supervisor privilege */ 268 __u32 ReadOnly; /* Write access to a read-only page */ 269 __u32 NoExecute; /* Execute access to a page marked NX */ 270 __u32 imprecise; /* Can't determine the exact fault address */ 271 }; 272 273 /* memory exception data */ 274 struct kfd_hsa_memory_exception_data { 275 struct kfd_memory_exception_failure failure; 276 __u64 va; 277 __u32 gpu_id; 278 __u32 ErrorType; /* 0 = no RAS error, 279 * 1 = ECC_SRAM, 280 * 2 = Link_SYNFLOOD (poison), 281 * 3 = GPU hang (not attributable to a specific cause), 282 * other values reserved 283 */ 284 }; 285 286 /* hw exception data */ 287 struct kfd_hsa_hw_exception_data { 288 __u32 reset_type; 289 __u32 reset_cause; 290 __u32 memory_lost; 291 __u32 gpu_id; 292 }; 293 294 /* Event data */ 295 struct kfd_event_data { 296 union { 297 struct kfd_hsa_memory_exception_data memory_exception_data; 298 struct kfd_hsa_hw_exception_data hw_exception_data; 299 }; /* From KFD */ 300 __u64 kfd_event_data_ext; /* pointer to an extension structure 301 for future exception types */ 302 __u32 event_id; /* to KFD */ 303 __u32 pad; 304 }; 305 306 struct kfd_ioctl_wait_events_args { 307 __u64 events_ptr; /* pointed to struct 308 kfd_event_data array, to KFD */ 309 __u32 num_events; /* to KFD */ 310 __u32 wait_for_all; /* to KFD */ 311 __u32 timeout; /* to KFD */ 312 __u32 wait_result; /* from KFD */ 313 }; 314 315 struct kfd_ioctl_set_scratch_backing_va_args { 316 __u64 va_addr; /* to KFD */ 317 __u32 gpu_id; /* to KFD */ 318 __u32 pad; 319 }; 320 321 struct kfd_ioctl_get_tile_config_args { 322 /* to KFD: pointer to tile array */ 323 __u64 tile_config_ptr; 324 /* to KFD: pointer to macro tile array */ 325 __u64 macro_tile_config_ptr; 326 /* to KFD: array size allocated by user mode 327 * from KFD: array size filled by kernel 328 */ 329 __u32 num_tile_configs; 330 /* to KFD: array size allocated by user mode 331 * from KFD: array size filled by kernel 332 */ 333 __u32 num_macro_tile_configs; 334 335 __u32 gpu_id; /* to KFD */ 336 __u32 gb_addr_config; /* from KFD */ 337 __u32 num_banks; /* from KFD */ 338 __u32 num_ranks; /* from KFD */ 339 /* struct size can be extended later if needed 340 * without breaking ABI compatibility 341 */ 342 }; 343 344 struct kfd_ioctl_set_trap_handler_args { 345 __u64 tba_addr; /* to KFD */ 346 __u64 tma_addr; /* to KFD */ 347 __u32 gpu_id; /* to KFD */ 348 __u32 pad; 349 }; 350 351 struct kfd_ioctl_acquire_vm_args { 352 __u32 drm_fd; /* to KFD */ 353 __u32 gpu_id; /* to KFD */ 354 }; 355 356 /* Allocation flags: memory types */ 357 #define KFD_IOC_ALLOC_MEM_FLAGS_VRAM (1 << 0) 358 #define KFD_IOC_ALLOC_MEM_FLAGS_GTT (1 << 1) 359 #define KFD_IOC_ALLOC_MEM_FLAGS_USERPTR (1 << 2) 360 #define KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL (1 << 3) 361 #define KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP (1 << 4) 362 /* Allocation flags: attributes/access options */ 363 #define KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE (1 << 31) 364 #define KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE (1 << 30) 365 #define KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC (1 << 29) 366 #define KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE (1 << 28) 367 #define KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM (1 << 27) 368 #define KFD_IOC_ALLOC_MEM_FLAGS_COHERENT (1 << 26) 369 #define KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED (1 << 25) 370 371 /* Allocate memory for later SVM (shared virtual memory) mapping. 372 * 373 * @va_addr: virtual address of the memory to be allocated 374 * all later mappings on all GPUs will use this address 375 * @size: size in bytes 376 * @handle: buffer handle returned to user mode, used to refer to 377 * this allocation for mapping, unmapping and freeing 378 * @mmap_offset: for CPU-mapping the allocation by mmapping a render node 379 * for userptrs this is overloaded to specify the CPU address 380 * @gpu_id: device identifier 381 * @flags: memory type and attributes. See KFD_IOC_ALLOC_MEM_FLAGS above 382 */ 383 struct kfd_ioctl_alloc_memory_of_gpu_args { 384 __u64 va_addr; /* to KFD */ 385 __u64 size; /* to KFD */ 386 __u64 handle; /* from KFD */ 387 __u64 mmap_offset; /* to KFD (userptr), from KFD (mmap offset) */ 388 __u32 gpu_id; /* to KFD */ 389 __u32 flags; 390 }; 391 392 /* Free memory allocated with kfd_ioctl_alloc_memory_of_gpu 393 * 394 * @handle: memory handle returned by alloc 395 */ 396 struct kfd_ioctl_free_memory_of_gpu_args { 397 __u64 handle; /* to KFD */ 398 }; 399 400 /* Map memory to one or more GPUs 401 * 402 * @handle: memory handle returned by alloc 403 * @device_ids_array_ptr: array of gpu_ids (__u32 per device) 404 * @n_devices: number of devices in the array 405 * @n_success: number of devices mapped successfully 406 * 407 * @n_success returns information to the caller how many devices from 408 * the start of the array have mapped the buffer successfully. It can 409 * be passed into a subsequent retry call to skip those devices. For 410 * the first call the caller should initialize it to 0. 411 * 412 * If the ioctl completes with return code 0 (success), n_success == 413 * n_devices. 414 */ 415 struct kfd_ioctl_map_memory_to_gpu_args { 416 __u64 handle; /* to KFD */ 417 __u64 device_ids_array_ptr; /* to KFD */ 418 __u32 n_devices; /* to KFD */ 419 __u32 n_success; /* to/from KFD */ 420 }; 421 422 /* Unmap memory from one or more GPUs 423 * 424 * same arguments as for mapping 425 */ 426 struct kfd_ioctl_unmap_memory_from_gpu_args { 427 __u64 handle; /* to KFD */ 428 __u64 device_ids_array_ptr; /* to KFD */ 429 __u32 n_devices; /* to KFD */ 430 __u32 n_success; /* to/from KFD */ 431 }; 432 433 /* Allocate GWS for specific queue 434 * 435 * @queue_id: queue's id that GWS is allocated for 436 * @num_gws: how many GWS to allocate 437 * @first_gws: index of the first GWS allocated. 438 * only support contiguous GWS allocation 439 */ 440 struct kfd_ioctl_alloc_queue_gws_args { 441 __u32 queue_id; /* to KFD */ 442 __u32 num_gws; /* to KFD */ 443 __u32 first_gws; /* from KFD */ 444 __u32 pad; 445 }; 446 447 struct kfd_ioctl_get_dmabuf_info_args { 448 __u64 size; /* from KFD */ 449 __u64 metadata_ptr; /* to KFD */ 450 __u32 metadata_size; /* to KFD (space allocated by user) 451 * from KFD (actual metadata size) 452 */ 453 __u32 gpu_id; /* from KFD */ 454 __u32 flags; /* from KFD (KFD_IOC_ALLOC_MEM_FLAGS) */ 455 __u32 dmabuf_fd; /* to KFD */ 456 }; 457 458 struct kfd_ioctl_import_dmabuf_args { 459 __u64 va_addr; /* to KFD */ 460 __u64 handle; /* from KFD */ 461 __u32 gpu_id; /* to KFD */ 462 __u32 dmabuf_fd; /* to KFD */ 463 }; 464 465 /* 466 * KFD SMI(System Management Interface) events 467 */ 468 enum kfd_smi_event { 469 KFD_SMI_EVENT_NONE = 0, /* not used */ 470 KFD_SMI_EVENT_VMFAULT = 1, /* event start counting at 1 */ 471 KFD_SMI_EVENT_THERMAL_THROTTLE = 2, 472 KFD_SMI_EVENT_GPU_PRE_RESET = 3, 473 KFD_SMI_EVENT_GPU_POST_RESET = 4, 474 KFD_SMI_EVENT_MIGRATE_START = 5, 475 KFD_SMI_EVENT_MIGRATE_END = 6, 476 KFD_SMI_EVENT_PAGE_FAULT_START = 7, 477 KFD_SMI_EVENT_PAGE_FAULT_END = 8, 478 KFD_SMI_EVENT_QUEUE_EVICTION = 9, 479 KFD_SMI_EVENT_QUEUE_RESTORE = 10, 480 KFD_SMI_EVENT_UNMAP_FROM_GPU = 11, 481 482 /* 483 * max event number, as a flag bit to get events from all processes, 484 * this requires super user permission, otherwise will not be able to 485 * receive event from any process. Without this flag to receive events 486 * from same process. 487 */ 488 KFD_SMI_EVENT_ALL_PROCESS = 64 489 }; 490 491 enum KFD_MIGRATE_TRIGGERS { 492 KFD_MIGRATE_TRIGGER_PREFETCH, 493 KFD_MIGRATE_TRIGGER_PAGEFAULT_GPU, 494 KFD_MIGRATE_TRIGGER_PAGEFAULT_CPU, 495 KFD_MIGRATE_TRIGGER_TTM_EVICTION 496 }; 497 498 enum KFD_QUEUE_EVICTION_TRIGGERS { 499 KFD_QUEUE_EVICTION_TRIGGER_SVM, 500 KFD_QUEUE_EVICTION_TRIGGER_USERPTR, 501 KFD_QUEUE_EVICTION_TRIGGER_TTM, 502 KFD_QUEUE_EVICTION_TRIGGER_SUSPEND, 503 KFD_QUEUE_EVICTION_CRIU_CHECKPOINT, 504 KFD_QUEUE_EVICTION_CRIU_RESTORE 505 }; 506 507 enum KFD_SVM_UNMAP_TRIGGERS { 508 KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY, 509 KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY_MIGRATE, 510 KFD_SVM_UNMAP_TRIGGER_UNMAP_FROM_CPU 511 }; 512 513 #define KFD_SMI_EVENT_MASK_FROM_INDEX(i) (1ULL << ((i) - 1)) 514 #define KFD_SMI_EVENT_MSG_SIZE 96 515 516 struct kfd_ioctl_smi_events_args { 517 __u32 gpuid; /* to KFD */ 518 __u32 anon_fd; /* from KFD */ 519 }; 520 521 /************************************************************************************************** 522 * CRIU IOCTLs (Checkpoint Restore In Userspace) 523 * 524 * When checkpointing a process, the userspace application will perform: 525 * 1. PROCESS_INFO op to determine current process information. This pauses execution and evicts 526 * all the queues. 527 * 2. CHECKPOINT op to checkpoint process contents (BOs, queues, events, svm-ranges) 528 * 3. UNPAUSE op to un-evict all the queues 529 * 530 * When restoring a process, the CRIU userspace application will perform: 531 * 532 * 1. RESTORE op to restore process contents 533 * 2. RESUME op to start the process 534 * 535 * Note: Queues are forced into an evicted state after a successful PROCESS_INFO. User 536 * application needs to perform an UNPAUSE operation after calling PROCESS_INFO. 537 */ 538 539 enum kfd_criu_op { 540 KFD_CRIU_OP_PROCESS_INFO, 541 KFD_CRIU_OP_CHECKPOINT, 542 KFD_CRIU_OP_UNPAUSE, 543 KFD_CRIU_OP_RESTORE, 544 KFD_CRIU_OP_RESUME, 545 }; 546 547 /** 548 * kfd_ioctl_criu_args - Arguments perform CRIU operation 549 * @devices: [in/out] User pointer to memory location for devices information. 550 * This is an array of type kfd_criu_device_bucket. 551 * @bos: [in/out] User pointer to memory location for BOs information 552 * This is an array of type kfd_criu_bo_bucket. 553 * @priv_data: [in/out] User pointer to memory location for private data 554 * @priv_data_size: [in/out] Size of priv_data in bytes 555 * @num_devices: [in/out] Number of GPUs used by process. Size of @devices array. 556 * @num_bos [in/out] Number of BOs used by process. Size of @bos array. 557 * @num_objects: [in/out] Number of objects used by process. Objects are opaque to 558 * user application. 559 * @pid: [in/out] PID of the process being checkpointed 560 * @op [in] Type of operation (kfd_criu_op) 561 * 562 * Return: 0 on success, -errno on failure 563 */ 564 struct kfd_ioctl_criu_args { 565 __u64 devices; /* Used during ops: CHECKPOINT, RESTORE */ 566 __u64 bos; /* Used during ops: CHECKPOINT, RESTORE */ 567 __u64 priv_data; /* Used during ops: CHECKPOINT, RESTORE */ 568 __u64 priv_data_size; /* Used during ops: PROCESS_INFO, RESTORE */ 569 __u32 num_devices; /* Used during ops: PROCESS_INFO, RESTORE */ 570 __u32 num_bos; /* Used during ops: PROCESS_INFO, RESTORE */ 571 __u32 num_objects; /* Used during ops: PROCESS_INFO, RESTORE */ 572 __u32 pid; /* Used during ops: PROCESS_INFO, RESUME */ 573 __u32 op; 574 }; 575 576 struct kfd_criu_device_bucket { 577 __u32 user_gpu_id; 578 __u32 actual_gpu_id; 579 __u32 drm_fd; 580 __u32 pad; 581 }; 582 583 struct kfd_criu_bo_bucket { 584 __u64 addr; 585 __u64 size; 586 __u64 offset; 587 __u64 restored_offset; /* During restore, updated offset for BO */ 588 __u32 gpu_id; /* This is the user_gpu_id */ 589 __u32 alloc_flags; 590 __u32 dmabuf_fd; 591 __u32 pad; 592 }; 593 594 /* CRIU IOCTLs - END */ 595 /**************************************************************************************************/ 596 597 /* Register offset inside the remapped mmio page 598 */ 599 enum kfd_mmio_remap { 600 KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL = 0, 601 KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL = 4, 602 }; 603 604 /* Guarantee host access to memory */ 605 #define KFD_IOCTL_SVM_FLAG_HOST_ACCESS 0x00000001 606 /* Fine grained coherency between all devices with access */ 607 #define KFD_IOCTL_SVM_FLAG_COHERENT 0x00000002 608 /* Use any GPU in same hive as preferred device */ 609 #define KFD_IOCTL_SVM_FLAG_HIVE_LOCAL 0x00000004 610 /* GPUs only read, allows replication */ 611 #define KFD_IOCTL_SVM_FLAG_GPU_RO 0x00000008 612 /* Allow execution on GPU */ 613 #define KFD_IOCTL_SVM_FLAG_GPU_EXEC 0x00000010 614 /* GPUs mostly read, may allow similar optimizations as RO, but writes fault */ 615 #define KFD_IOCTL_SVM_FLAG_GPU_READ_MOSTLY 0x00000020 616 /* Keep GPU memory mapping always valid as if XNACK is disable */ 617 #define KFD_IOCTL_SVM_FLAG_GPU_ALWAYS_MAPPED 0x00000040 618 619 /** 620 * kfd_ioctl_svm_op - SVM ioctl operations 621 * 622 * @KFD_IOCTL_SVM_OP_SET_ATTR: Modify one or more attributes 623 * @KFD_IOCTL_SVM_OP_GET_ATTR: Query one or more attributes 624 */ 625 enum kfd_ioctl_svm_op { 626 KFD_IOCTL_SVM_OP_SET_ATTR, 627 KFD_IOCTL_SVM_OP_GET_ATTR 628 }; 629 630 /** kfd_ioctl_svm_location - Enum for preferred and prefetch locations 631 * 632 * GPU IDs are used to specify GPUs as preferred and prefetch locations. 633 * Below definitions are used for system memory or for leaving the preferred 634 * location unspecified. 635 */ 636 enum kfd_ioctl_svm_location { 637 KFD_IOCTL_SVM_LOCATION_SYSMEM = 0, 638 KFD_IOCTL_SVM_LOCATION_UNDEFINED = 0xffffffff 639 }; 640 641 /** 642 * kfd_ioctl_svm_attr_type - SVM attribute types 643 * 644 * @KFD_IOCTL_SVM_ATTR_PREFERRED_LOC: gpuid of the preferred location, 0 for 645 * system memory 646 * @KFD_IOCTL_SVM_ATTR_PREFETCH_LOC: gpuid of the prefetch location, 0 for 647 * system memory. Setting this triggers an 648 * immediate prefetch (migration). 649 * @KFD_IOCTL_SVM_ATTR_ACCESS: 650 * @KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE: 651 * @KFD_IOCTL_SVM_ATTR_NO_ACCESS: specify memory access for the gpuid given 652 * by the attribute value 653 * @KFD_IOCTL_SVM_ATTR_SET_FLAGS: bitmask of flags to set (see 654 * KFD_IOCTL_SVM_FLAG_...) 655 * @KFD_IOCTL_SVM_ATTR_CLR_FLAGS: bitmask of flags to clear 656 * @KFD_IOCTL_SVM_ATTR_GRANULARITY: migration granularity 657 * (log2 num pages) 658 */ 659 enum kfd_ioctl_svm_attr_type { 660 KFD_IOCTL_SVM_ATTR_PREFERRED_LOC, 661 KFD_IOCTL_SVM_ATTR_PREFETCH_LOC, 662 KFD_IOCTL_SVM_ATTR_ACCESS, 663 KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE, 664 KFD_IOCTL_SVM_ATTR_NO_ACCESS, 665 KFD_IOCTL_SVM_ATTR_SET_FLAGS, 666 KFD_IOCTL_SVM_ATTR_CLR_FLAGS, 667 KFD_IOCTL_SVM_ATTR_GRANULARITY 668 }; 669 670 /** 671 * kfd_ioctl_svm_attribute - Attributes as pairs of type and value 672 * 673 * The meaning of the @value depends on the attribute type. 674 * 675 * @type: attribute type (see enum @kfd_ioctl_svm_attr_type) 676 * @value: attribute value 677 */ 678 struct kfd_ioctl_svm_attribute { 679 __u32 type; 680 __u32 value; 681 }; 682 683 /** 684 * kfd_ioctl_svm_args - Arguments for SVM ioctl 685 * 686 * @op specifies the operation to perform (see enum 687 * @kfd_ioctl_svm_op). @start_addr and @size are common for all 688 * operations. 689 * 690 * A variable number of attributes can be given in @attrs. 691 * @nattr specifies the number of attributes. New attributes can be 692 * added in the future without breaking the ABI. If unknown attributes 693 * are given, the function returns -EINVAL. 694 * 695 * @KFD_IOCTL_SVM_OP_SET_ATTR sets attributes for a virtual address 696 * range. It may overlap existing virtual address ranges. If it does, 697 * the existing ranges will be split such that the attribute changes 698 * only apply to the specified address range. 699 * 700 * @KFD_IOCTL_SVM_OP_GET_ATTR returns the intersection of attributes 701 * over all memory in the given range and returns the result as the 702 * attribute value. If different pages have different preferred or 703 * prefetch locations, 0xffffffff will be returned for 704 * @KFD_IOCTL_SVM_ATTR_PREFERRED_LOC or 705 * @KFD_IOCTL_SVM_ATTR_PREFETCH_LOC resepctively. For 706 * @KFD_IOCTL_SVM_ATTR_SET_FLAGS, flags of all pages will be 707 * aggregated by bitwise AND. That means, a flag will be set in the 708 * output, if that flag is set for all pages in the range. For 709 * @KFD_IOCTL_SVM_ATTR_CLR_FLAGS, flags of all pages will be 710 * aggregated by bitwise NOR. That means, a flag will be set in the 711 * output, if that flag is clear for all pages in the range. 712 * The minimum migration granularity throughout the range will be 713 * returned for @KFD_IOCTL_SVM_ATTR_GRANULARITY. 714 * 715 * Querying of accessibility attributes works by initializing the 716 * attribute type to @KFD_IOCTL_SVM_ATTR_ACCESS and the value to the 717 * GPUID being queried. Multiple attributes can be given to allow 718 * querying multiple GPUIDs. The ioctl function overwrites the 719 * attribute type to indicate the access for the specified GPU. 720 */ 721 struct kfd_ioctl_svm_args { 722 __u64 start_addr; 723 __u64 size; 724 __u32 op; 725 __u32 nattr; 726 /* Variable length array of attributes */ 727 struct kfd_ioctl_svm_attribute attrs[]; 728 }; 729 730 /** 731 * kfd_ioctl_set_xnack_mode_args - Arguments for set_xnack_mode 732 * 733 * @xnack_enabled: [in/out] Whether to enable XNACK mode for this process 734 * 735 * @xnack_enabled indicates whether recoverable page faults should be 736 * enabled for the current process. 0 means disabled, positive means 737 * enabled, negative means leave unchanged. If enabled, virtual address 738 * translations on GFXv9 and later AMD GPUs can return XNACK and retry 739 * the access until a valid PTE is available. This is used to implement 740 * device page faults. 741 * 742 * On output, @xnack_enabled returns the (new) current mode (0 or 743 * positive). Therefore, a negative input value can be used to query 744 * the current mode without changing it. 745 * 746 * The XNACK mode fundamentally changes the way SVM managed memory works 747 * in the driver, with subtle effects on application performance and 748 * functionality. 749 * 750 * Enabling XNACK mode requires shader programs to be compiled 751 * differently. Furthermore, not all GPUs support changing the mode 752 * per-process. Therefore changing the mode is only allowed while no 753 * user mode queues exist in the process. This ensure that no shader 754 * code is running that may be compiled for the wrong mode. And GPUs 755 * that cannot change to the requested mode will prevent the XNACK 756 * mode from occurring. All GPUs used by the process must be in the 757 * same XNACK mode. 758 * 759 * GFXv8 or older GPUs do not support 48 bit virtual addresses or SVM. 760 * Therefore those GPUs are not considered for the XNACK mode switch. 761 * 762 * Return: 0 on success, -errno on failure 763 */ 764 struct kfd_ioctl_set_xnack_mode_args { 765 __s32 xnack_enabled; 766 }; 767 768 #define AMDKFD_IOCTL_BASE 'K' 769 #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) 770 #define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type) 771 #define AMDKFD_IOW(nr, type) _IOW(AMDKFD_IOCTL_BASE, nr, type) 772 #define AMDKFD_IOWR(nr, type) _IOWR(AMDKFD_IOCTL_BASE, nr, type) 773 774 #define AMDKFD_IOC_GET_VERSION \ 775 AMDKFD_IOR(0x01, struct kfd_ioctl_get_version_args) 776 777 #define AMDKFD_IOC_CREATE_QUEUE \ 778 AMDKFD_IOWR(0x02, struct kfd_ioctl_create_queue_args) 779 780 #define AMDKFD_IOC_DESTROY_QUEUE \ 781 AMDKFD_IOWR(0x03, struct kfd_ioctl_destroy_queue_args) 782 783 #define AMDKFD_IOC_SET_MEMORY_POLICY \ 784 AMDKFD_IOW(0x04, struct kfd_ioctl_set_memory_policy_args) 785 786 #define AMDKFD_IOC_GET_CLOCK_COUNTERS \ 787 AMDKFD_IOWR(0x05, struct kfd_ioctl_get_clock_counters_args) 788 789 #define AMDKFD_IOC_GET_PROCESS_APERTURES \ 790 AMDKFD_IOR(0x06, struct kfd_ioctl_get_process_apertures_args) 791 792 #define AMDKFD_IOC_UPDATE_QUEUE \ 793 AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args) 794 795 #define AMDKFD_IOC_CREATE_EVENT \ 796 AMDKFD_IOWR(0x08, struct kfd_ioctl_create_event_args) 797 798 #define AMDKFD_IOC_DESTROY_EVENT \ 799 AMDKFD_IOW(0x09, struct kfd_ioctl_destroy_event_args) 800 801 #define AMDKFD_IOC_SET_EVENT \ 802 AMDKFD_IOW(0x0A, struct kfd_ioctl_set_event_args) 803 804 #define AMDKFD_IOC_RESET_EVENT \ 805 AMDKFD_IOW(0x0B, struct kfd_ioctl_reset_event_args) 806 807 #define AMDKFD_IOC_WAIT_EVENTS \ 808 AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args) 809 810 #define AMDKFD_IOC_DBG_REGISTER_DEPRECATED \ 811 AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args) 812 813 #define AMDKFD_IOC_DBG_UNREGISTER_DEPRECATED \ 814 AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args) 815 816 #define AMDKFD_IOC_DBG_ADDRESS_WATCH_DEPRECATED \ 817 AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args) 818 819 #define AMDKFD_IOC_DBG_WAVE_CONTROL_DEPRECATED \ 820 AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args) 821 822 #define AMDKFD_IOC_SET_SCRATCH_BACKING_VA \ 823 AMDKFD_IOWR(0x11, struct kfd_ioctl_set_scratch_backing_va_args) 824 825 #define AMDKFD_IOC_GET_TILE_CONFIG \ 826 AMDKFD_IOWR(0x12, struct kfd_ioctl_get_tile_config_args) 827 828 #define AMDKFD_IOC_SET_TRAP_HANDLER \ 829 AMDKFD_IOW(0x13, struct kfd_ioctl_set_trap_handler_args) 830 831 #define AMDKFD_IOC_GET_PROCESS_APERTURES_NEW \ 832 AMDKFD_IOWR(0x14, \ 833 struct kfd_ioctl_get_process_apertures_new_args) 834 835 #define AMDKFD_IOC_ACQUIRE_VM \ 836 AMDKFD_IOW(0x15, struct kfd_ioctl_acquire_vm_args) 837 838 #define AMDKFD_IOC_ALLOC_MEMORY_OF_GPU \ 839 AMDKFD_IOWR(0x16, struct kfd_ioctl_alloc_memory_of_gpu_args) 840 841 #define AMDKFD_IOC_FREE_MEMORY_OF_GPU \ 842 AMDKFD_IOW(0x17, struct kfd_ioctl_free_memory_of_gpu_args) 843 844 #define AMDKFD_IOC_MAP_MEMORY_TO_GPU \ 845 AMDKFD_IOWR(0x18, struct kfd_ioctl_map_memory_to_gpu_args) 846 847 #define AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU \ 848 AMDKFD_IOWR(0x19, struct kfd_ioctl_unmap_memory_from_gpu_args) 849 850 #define AMDKFD_IOC_SET_CU_MASK \ 851 AMDKFD_IOW(0x1A, struct kfd_ioctl_set_cu_mask_args) 852 853 #define AMDKFD_IOC_GET_QUEUE_WAVE_STATE \ 854 AMDKFD_IOWR(0x1B, struct kfd_ioctl_get_queue_wave_state_args) 855 856 #define AMDKFD_IOC_GET_DMABUF_INFO \ 857 AMDKFD_IOWR(0x1C, struct kfd_ioctl_get_dmabuf_info_args) 858 859 #define AMDKFD_IOC_IMPORT_DMABUF \ 860 AMDKFD_IOWR(0x1D, struct kfd_ioctl_import_dmabuf_args) 861 862 #define AMDKFD_IOC_ALLOC_QUEUE_GWS \ 863 AMDKFD_IOWR(0x1E, struct kfd_ioctl_alloc_queue_gws_args) 864 865 #define AMDKFD_IOC_SMI_EVENTS \ 866 AMDKFD_IOWR(0x1F, struct kfd_ioctl_smi_events_args) 867 868 #define AMDKFD_IOC_SVM AMDKFD_IOWR(0x20, struct kfd_ioctl_svm_args) 869 870 #define AMDKFD_IOC_SET_XNACK_MODE \ 871 AMDKFD_IOWR(0x21, struct kfd_ioctl_set_xnack_mode_args) 872 873 #define AMDKFD_IOC_CRIU_OP \ 874 AMDKFD_IOWR(0x22, struct kfd_ioctl_criu_args) 875 876 #define AMDKFD_IOC_AVAILABLE_MEMORY \ 877 AMDKFD_IOWR(0x23, struct kfd_ioctl_get_available_memory_args) 878 879 #define AMDKFD_COMMAND_START 0x01 880 #define AMDKFD_COMMAND_END 0x24 881 882 #endif 883