1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #ifndef KFD_IOCTL_H_INCLUDED 24 #define KFD_IOCTL_H_INCLUDED 25 26 #include <drm/drm.h> 27 #include <linux/ioctl.h> 28 29 /* 30 * - 1.1 - initial version 31 * - 1.3 - Add SMI events support 32 * - 1.4 - Indicate new SRAM EDC bit in device properties 33 * - 1.5 - Add SVM API 34 * - 1.6 - Query clear flags in SVM get_attr API 35 * - 1.7 - Checkpoint Restore (CRIU) API 36 * - 1.8 - CRIU - Support for SDMA transfers with GTT BOs 37 * - 1.9 - Add available memory ioctl 38 */ 39 #define KFD_IOCTL_MAJOR_VERSION 1 40 #define KFD_IOCTL_MINOR_VERSION 9 41 42 struct kfd_ioctl_get_version_args { 43 __u32 major_version; /* from KFD */ 44 __u32 minor_version; /* from KFD */ 45 }; 46 47 /* For kfd_ioctl_create_queue_args.queue_type. */ 48 #define KFD_IOC_QUEUE_TYPE_COMPUTE 0x0 49 #define KFD_IOC_QUEUE_TYPE_SDMA 0x1 50 #define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 0x2 51 #define KFD_IOC_QUEUE_TYPE_SDMA_XGMI 0x3 52 53 #define KFD_MAX_QUEUE_PERCENTAGE 100 54 #define KFD_MAX_QUEUE_PRIORITY 15 55 56 struct kfd_ioctl_create_queue_args { 57 __u64 ring_base_address; /* to KFD */ 58 __u64 write_pointer_address; /* from KFD */ 59 __u64 read_pointer_address; /* from KFD */ 60 __u64 doorbell_offset; /* from KFD */ 61 62 __u32 ring_size; /* to KFD */ 63 __u32 gpu_id; /* to KFD */ 64 __u32 queue_type; /* to KFD */ 65 __u32 queue_percentage; /* to KFD */ 66 __u32 queue_priority; /* to KFD */ 67 __u32 queue_id; /* from KFD */ 68 69 __u64 eop_buffer_address; /* to KFD */ 70 __u64 eop_buffer_size; /* to KFD */ 71 __u64 ctx_save_restore_address; /* to KFD */ 72 __u32 ctx_save_restore_size; /* to KFD */ 73 __u32 ctl_stack_size; /* to KFD */ 74 }; 75 76 struct kfd_ioctl_destroy_queue_args { 77 __u32 queue_id; /* to KFD */ 78 __u32 pad; 79 }; 80 81 struct kfd_ioctl_update_queue_args { 82 __u64 ring_base_address; /* to KFD */ 83 84 __u32 queue_id; /* to KFD */ 85 __u32 ring_size; /* to KFD */ 86 __u32 queue_percentage; /* to KFD */ 87 __u32 queue_priority; /* to KFD */ 88 }; 89 90 struct kfd_ioctl_set_cu_mask_args { 91 __u32 queue_id; /* to KFD */ 92 __u32 num_cu_mask; /* to KFD */ 93 __u64 cu_mask_ptr; /* to KFD */ 94 }; 95 96 struct kfd_ioctl_get_queue_wave_state_args { 97 __u64 ctl_stack_address; /* to KFD */ 98 __u32 ctl_stack_used_size; /* from KFD */ 99 __u32 save_area_used_size; /* from KFD */ 100 __u32 queue_id; /* to KFD */ 101 __u32 pad; 102 }; 103 104 struct kfd_ioctl_get_available_memory_args { 105 __u64 available; /* from KFD */ 106 __u32 gpu_id; /* to KFD */ 107 __u32 pad; 108 }; 109 110 /* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */ 111 #define KFD_IOC_CACHE_POLICY_COHERENT 0 112 #define KFD_IOC_CACHE_POLICY_NONCOHERENT 1 113 114 struct kfd_ioctl_set_memory_policy_args { 115 __u64 alternate_aperture_base; /* to KFD */ 116 __u64 alternate_aperture_size; /* to KFD */ 117 118 __u32 gpu_id; /* to KFD */ 119 __u32 default_policy; /* to KFD */ 120 __u32 alternate_policy; /* to KFD */ 121 __u32 pad; 122 }; 123 124 /* 125 * All counters are monotonic. They are used for profiling of compute jobs. 126 * The profiling is done by userspace. 127 * 128 * In case of GPU reset, the counter should not be affected. 129 */ 130 131 struct kfd_ioctl_get_clock_counters_args { 132 __u64 gpu_clock_counter; /* from KFD */ 133 __u64 cpu_clock_counter; /* from KFD */ 134 __u64 system_clock_counter; /* from KFD */ 135 __u64 system_clock_freq; /* from KFD */ 136 137 __u32 gpu_id; /* to KFD */ 138 __u32 pad; 139 }; 140 141 struct kfd_process_device_apertures { 142 __u64 lds_base; /* from KFD */ 143 __u64 lds_limit; /* from KFD */ 144 __u64 scratch_base; /* from KFD */ 145 __u64 scratch_limit; /* from KFD */ 146 __u64 gpuvm_base; /* from KFD */ 147 __u64 gpuvm_limit; /* from KFD */ 148 __u32 gpu_id; /* from KFD */ 149 __u32 pad; 150 }; 151 152 /* 153 * AMDKFD_IOC_GET_PROCESS_APERTURES is deprecated. Use 154 * AMDKFD_IOC_GET_PROCESS_APERTURES_NEW instead, which supports an 155 * unlimited number of GPUs. 156 */ 157 #define NUM_OF_SUPPORTED_GPUS 7 158 struct kfd_ioctl_get_process_apertures_args { 159 struct kfd_process_device_apertures 160 process_apertures[NUM_OF_SUPPORTED_GPUS];/* from KFD */ 161 162 /* from KFD, should be in the range [1 - NUM_OF_SUPPORTED_GPUS] */ 163 __u32 num_of_nodes; 164 __u32 pad; 165 }; 166 167 struct kfd_ioctl_get_process_apertures_new_args { 168 /* User allocated. Pointer to struct kfd_process_device_apertures 169 * filled in by Kernel 170 */ 171 __u64 kfd_process_device_apertures_ptr; 172 /* to KFD - indicates amount of memory present in 173 * kfd_process_device_apertures_ptr 174 * from KFD - Number of entries filled by KFD. 175 */ 176 __u32 num_of_nodes; 177 __u32 pad; 178 }; 179 180 #define MAX_ALLOWED_NUM_POINTS 100 181 #define MAX_ALLOWED_AW_BUFF_SIZE 4096 182 #define MAX_ALLOWED_WAC_BUFF_SIZE 128 183 184 struct kfd_ioctl_dbg_register_args { 185 __u32 gpu_id; /* to KFD */ 186 __u32 pad; 187 }; 188 189 struct kfd_ioctl_dbg_unregister_args { 190 __u32 gpu_id; /* to KFD */ 191 __u32 pad; 192 }; 193 194 struct kfd_ioctl_dbg_address_watch_args { 195 __u64 content_ptr; /* a pointer to the actual content */ 196 __u32 gpu_id; /* to KFD */ 197 __u32 buf_size_in_bytes; /*including gpu_id and buf_size */ 198 }; 199 200 struct kfd_ioctl_dbg_wave_control_args { 201 __u64 content_ptr; /* a pointer to the actual content */ 202 __u32 gpu_id; /* to KFD */ 203 __u32 buf_size_in_bytes; /*including gpu_id and buf_size */ 204 }; 205 206 #define KFD_INVALID_FD 0xffffffff 207 208 /* Matching HSA_EVENTTYPE */ 209 #define KFD_IOC_EVENT_SIGNAL 0 210 #define KFD_IOC_EVENT_NODECHANGE 1 211 #define KFD_IOC_EVENT_DEVICESTATECHANGE 2 212 #define KFD_IOC_EVENT_HW_EXCEPTION 3 213 #define KFD_IOC_EVENT_SYSTEM_EVENT 4 214 #define KFD_IOC_EVENT_DEBUG_EVENT 5 215 #define KFD_IOC_EVENT_PROFILE_EVENT 6 216 #define KFD_IOC_EVENT_QUEUE_EVENT 7 217 #define KFD_IOC_EVENT_MEMORY 8 218 219 #define KFD_IOC_WAIT_RESULT_COMPLETE 0 220 #define KFD_IOC_WAIT_RESULT_TIMEOUT 1 221 #define KFD_IOC_WAIT_RESULT_FAIL 2 222 223 #define KFD_SIGNAL_EVENT_LIMIT 4096 224 225 /* For kfd_event_data.hw_exception_data.reset_type. */ 226 #define KFD_HW_EXCEPTION_WHOLE_GPU_RESET 0 227 #define KFD_HW_EXCEPTION_PER_ENGINE_RESET 1 228 229 /* For kfd_event_data.hw_exception_data.reset_cause. */ 230 #define KFD_HW_EXCEPTION_GPU_HANG 0 231 #define KFD_HW_EXCEPTION_ECC 1 232 233 /* For kfd_hsa_memory_exception_data.ErrorType */ 234 #define KFD_MEM_ERR_NO_RAS 0 235 #define KFD_MEM_ERR_SRAM_ECC 1 236 #define KFD_MEM_ERR_POISON_CONSUMED 2 237 #define KFD_MEM_ERR_GPU_HANG 3 238 239 struct kfd_ioctl_create_event_args { 240 __u64 event_page_offset; /* from KFD */ 241 __u32 event_trigger_data; /* from KFD - signal events only */ 242 __u32 event_type; /* to KFD */ 243 __u32 auto_reset; /* to KFD */ 244 __u32 node_id; /* to KFD - only valid for certain 245 event types */ 246 __u32 event_id; /* from KFD */ 247 __u32 event_slot_index; /* from KFD */ 248 }; 249 250 struct kfd_ioctl_destroy_event_args { 251 __u32 event_id; /* to KFD */ 252 __u32 pad; 253 }; 254 255 struct kfd_ioctl_set_event_args { 256 __u32 event_id; /* to KFD */ 257 __u32 pad; 258 }; 259 260 struct kfd_ioctl_reset_event_args { 261 __u32 event_id; /* to KFD */ 262 __u32 pad; 263 }; 264 265 struct kfd_memory_exception_failure { 266 __u32 NotPresent; /* Page not present or supervisor privilege */ 267 __u32 ReadOnly; /* Write access to a read-only page */ 268 __u32 NoExecute; /* Execute access to a page marked NX */ 269 __u32 imprecise; /* Can't determine the exact fault address */ 270 }; 271 272 /* memory exception data */ 273 struct kfd_hsa_memory_exception_data { 274 struct kfd_memory_exception_failure failure; 275 __u64 va; 276 __u32 gpu_id; 277 __u32 ErrorType; /* 0 = no RAS error, 278 * 1 = ECC_SRAM, 279 * 2 = Link_SYNFLOOD (poison), 280 * 3 = GPU hang (not attributable to a specific cause), 281 * other values reserved 282 */ 283 }; 284 285 /* hw exception data */ 286 struct kfd_hsa_hw_exception_data { 287 __u32 reset_type; 288 __u32 reset_cause; 289 __u32 memory_lost; 290 __u32 gpu_id; 291 }; 292 293 /* Event data */ 294 struct kfd_event_data { 295 union { 296 struct kfd_hsa_memory_exception_data memory_exception_data; 297 struct kfd_hsa_hw_exception_data hw_exception_data; 298 }; /* From KFD */ 299 __u64 kfd_event_data_ext; /* pointer to an extension structure 300 for future exception types */ 301 __u32 event_id; /* to KFD */ 302 __u32 pad; 303 }; 304 305 struct kfd_ioctl_wait_events_args { 306 __u64 events_ptr; /* pointed to struct 307 kfd_event_data array, to KFD */ 308 __u32 num_events; /* to KFD */ 309 __u32 wait_for_all; /* to KFD */ 310 __u32 timeout; /* to KFD */ 311 __u32 wait_result; /* from KFD */ 312 }; 313 314 struct kfd_ioctl_set_scratch_backing_va_args { 315 __u64 va_addr; /* to KFD */ 316 __u32 gpu_id; /* to KFD */ 317 __u32 pad; 318 }; 319 320 struct kfd_ioctl_get_tile_config_args { 321 /* to KFD: pointer to tile array */ 322 __u64 tile_config_ptr; 323 /* to KFD: pointer to macro tile array */ 324 __u64 macro_tile_config_ptr; 325 /* to KFD: array size allocated by user mode 326 * from KFD: array size filled by kernel 327 */ 328 __u32 num_tile_configs; 329 /* to KFD: array size allocated by user mode 330 * from KFD: array size filled by kernel 331 */ 332 __u32 num_macro_tile_configs; 333 334 __u32 gpu_id; /* to KFD */ 335 __u32 gb_addr_config; /* from KFD */ 336 __u32 num_banks; /* from KFD */ 337 __u32 num_ranks; /* from KFD */ 338 /* struct size can be extended later if needed 339 * without breaking ABI compatibility 340 */ 341 }; 342 343 struct kfd_ioctl_set_trap_handler_args { 344 __u64 tba_addr; /* to KFD */ 345 __u64 tma_addr; /* to KFD */ 346 __u32 gpu_id; /* to KFD */ 347 __u32 pad; 348 }; 349 350 struct kfd_ioctl_acquire_vm_args { 351 __u32 drm_fd; /* to KFD */ 352 __u32 gpu_id; /* to KFD */ 353 }; 354 355 /* Allocation flags: memory types */ 356 #define KFD_IOC_ALLOC_MEM_FLAGS_VRAM (1 << 0) 357 #define KFD_IOC_ALLOC_MEM_FLAGS_GTT (1 << 1) 358 #define KFD_IOC_ALLOC_MEM_FLAGS_USERPTR (1 << 2) 359 #define KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL (1 << 3) 360 #define KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP (1 << 4) 361 /* Allocation flags: attributes/access options */ 362 #define KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE (1 << 31) 363 #define KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE (1 << 30) 364 #define KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC (1 << 29) 365 #define KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE (1 << 28) 366 #define KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM (1 << 27) 367 #define KFD_IOC_ALLOC_MEM_FLAGS_COHERENT (1 << 26) 368 #define KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED (1 << 25) 369 370 /* Allocate memory for later SVM (shared virtual memory) mapping. 371 * 372 * @va_addr: virtual address of the memory to be allocated 373 * all later mappings on all GPUs will use this address 374 * @size: size in bytes 375 * @handle: buffer handle returned to user mode, used to refer to 376 * this allocation for mapping, unmapping and freeing 377 * @mmap_offset: for CPU-mapping the allocation by mmapping a render node 378 * for userptrs this is overloaded to specify the CPU address 379 * @gpu_id: device identifier 380 * @flags: memory type and attributes. See KFD_IOC_ALLOC_MEM_FLAGS above 381 */ 382 struct kfd_ioctl_alloc_memory_of_gpu_args { 383 __u64 va_addr; /* to KFD */ 384 __u64 size; /* to KFD */ 385 __u64 handle; /* from KFD */ 386 __u64 mmap_offset; /* to KFD (userptr), from KFD (mmap offset) */ 387 __u32 gpu_id; /* to KFD */ 388 __u32 flags; 389 }; 390 391 /* Free memory allocated with kfd_ioctl_alloc_memory_of_gpu 392 * 393 * @handle: memory handle returned by alloc 394 */ 395 struct kfd_ioctl_free_memory_of_gpu_args { 396 __u64 handle; /* to KFD */ 397 }; 398 399 /* Map memory to one or more GPUs 400 * 401 * @handle: memory handle returned by alloc 402 * @device_ids_array_ptr: array of gpu_ids (__u32 per device) 403 * @n_devices: number of devices in the array 404 * @n_success: number of devices mapped successfully 405 * 406 * @n_success returns information to the caller how many devices from 407 * the start of the array have mapped the buffer successfully. It can 408 * be passed into a subsequent retry call to skip those devices. For 409 * the first call the caller should initialize it to 0. 410 * 411 * If the ioctl completes with return code 0 (success), n_success == 412 * n_devices. 413 */ 414 struct kfd_ioctl_map_memory_to_gpu_args { 415 __u64 handle; /* to KFD */ 416 __u64 device_ids_array_ptr; /* to KFD */ 417 __u32 n_devices; /* to KFD */ 418 __u32 n_success; /* to/from KFD */ 419 }; 420 421 /* Unmap memory from one or more GPUs 422 * 423 * same arguments as for mapping 424 */ 425 struct kfd_ioctl_unmap_memory_from_gpu_args { 426 __u64 handle; /* to KFD */ 427 __u64 device_ids_array_ptr; /* to KFD */ 428 __u32 n_devices; /* to KFD */ 429 __u32 n_success; /* to/from KFD */ 430 }; 431 432 /* Allocate GWS for specific queue 433 * 434 * @queue_id: queue's id that GWS is allocated for 435 * @num_gws: how many GWS to allocate 436 * @first_gws: index of the first GWS allocated. 437 * only support contiguous GWS allocation 438 */ 439 struct kfd_ioctl_alloc_queue_gws_args { 440 __u32 queue_id; /* to KFD */ 441 __u32 num_gws; /* to KFD */ 442 __u32 first_gws; /* from KFD */ 443 __u32 pad; 444 }; 445 446 struct kfd_ioctl_get_dmabuf_info_args { 447 __u64 size; /* from KFD */ 448 __u64 metadata_ptr; /* to KFD */ 449 __u32 metadata_size; /* to KFD (space allocated by user) 450 * from KFD (actual metadata size) 451 */ 452 __u32 gpu_id; /* from KFD */ 453 __u32 flags; /* from KFD (KFD_IOC_ALLOC_MEM_FLAGS) */ 454 __u32 dmabuf_fd; /* to KFD */ 455 }; 456 457 struct kfd_ioctl_import_dmabuf_args { 458 __u64 va_addr; /* to KFD */ 459 __u64 handle; /* from KFD */ 460 __u32 gpu_id; /* to KFD */ 461 __u32 dmabuf_fd; /* to KFD */ 462 }; 463 464 /* 465 * KFD SMI(System Management Interface) events 466 */ 467 enum kfd_smi_event { 468 KFD_SMI_EVENT_NONE = 0, /* not used */ 469 KFD_SMI_EVENT_VMFAULT = 1, /* event start counting at 1 */ 470 KFD_SMI_EVENT_THERMAL_THROTTLE = 2, 471 KFD_SMI_EVENT_GPU_PRE_RESET = 3, 472 KFD_SMI_EVENT_GPU_POST_RESET = 4, 473 KFD_SMI_EVENT_MIGRATE_START = 5, 474 KFD_SMI_EVENT_MIGRATE_END = 6, 475 KFD_SMI_EVENT_PAGE_FAULT_START = 7, 476 KFD_SMI_EVENT_PAGE_FAULT_END = 8, 477 KFD_SMI_EVENT_QUEUE_EVICTION = 9, 478 KFD_SMI_EVENT_QUEUE_RESTORE = 10, 479 KFD_SMI_EVENT_UNMAP_FROM_GPU = 11, 480 481 /* 482 * max event number, as a flag bit to get events from all processes, 483 * this requires super user permission, otherwise will not be able to 484 * receive event from any process. Without this flag to receive events 485 * from same process. 486 */ 487 KFD_SMI_EVENT_ALL_PROCESS = 64 488 }; 489 490 enum KFD_MIGRATE_TRIGGERS { 491 KFD_MIGRATE_TRIGGER_PREFETCH, 492 KFD_MIGRATE_TRIGGER_PAGEFAULT_GPU, 493 KFD_MIGRATE_TRIGGER_PAGEFAULT_CPU, 494 KFD_MIGRATE_TRIGGER_TTM_EVICTION 495 }; 496 497 enum KFD_QUEUE_EVICTION_TRIGGERS { 498 KFD_QUEUE_EVICTION_TRIGGER_SVM, 499 KFD_QUEUE_EVICTION_TRIGGER_USERPTR, 500 KFD_QUEUE_EVICTION_TRIGGER_TTM, 501 KFD_QUEUE_EVICTION_TRIGGER_SUSPEND, 502 KFD_QUEUE_EVICTION_CRIU_CHECKPOINT, 503 KFD_QUEUE_EVICTION_CRIU_RESTORE 504 }; 505 506 enum KFD_SVM_UNMAP_TRIGGERS { 507 KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY, 508 KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY_MIGRATE, 509 KFD_SVM_UNMAP_TRIGGER_UNMAP_FROM_CPU 510 }; 511 512 #define KFD_SMI_EVENT_MASK_FROM_INDEX(i) (1ULL << ((i) - 1)) 513 #define KFD_SMI_EVENT_MSG_SIZE 96 514 515 struct kfd_ioctl_smi_events_args { 516 __u32 gpuid; /* to KFD */ 517 __u32 anon_fd; /* from KFD */ 518 }; 519 520 /************************************************************************************************** 521 * CRIU IOCTLs (Checkpoint Restore In Userspace) 522 * 523 * When checkpointing a process, the userspace application will perform: 524 * 1. PROCESS_INFO op to determine current process information. This pauses execution and evicts 525 * all the queues. 526 * 2. CHECKPOINT op to checkpoint process contents (BOs, queues, events, svm-ranges) 527 * 3. UNPAUSE op to un-evict all the queues 528 * 529 * When restoring a process, the CRIU userspace application will perform: 530 * 531 * 1. RESTORE op to restore process contents 532 * 2. RESUME op to start the process 533 * 534 * Note: Queues are forced into an evicted state after a successful PROCESS_INFO. User 535 * application needs to perform an UNPAUSE operation after calling PROCESS_INFO. 536 */ 537 538 enum kfd_criu_op { 539 KFD_CRIU_OP_PROCESS_INFO, 540 KFD_CRIU_OP_CHECKPOINT, 541 KFD_CRIU_OP_UNPAUSE, 542 KFD_CRIU_OP_RESTORE, 543 KFD_CRIU_OP_RESUME, 544 }; 545 546 /** 547 * kfd_ioctl_criu_args - Arguments perform CRIU operation 548 * @devices: [in/out] User pointer to memory location for devices information. 549 * This is an array of type kfd_criu_device_bucket. 550 * @bos: [in/out] User pointer to memory location for BOs information 551 * This is an array of type kfd_criu_bo_bucket. 552 * @priv_data: [in/out] User pointer to memory location for private data 553 * @priv_data_size: [in/out] Size of priv_data in bytes 554 * @num_devices: [in/out] Number of GPUs used by process. Size of @devices array. 555 * @num_bos [in/out] Number of BOs used by process. Size of @bos array. 556 * @num_objects: [in/out] Number of objects used by process. Objects are opaque to 557 * user application. 558 * @pid: [in/out] PID of the process being checkpointed 559 * @op [in] Type of operation (kfd_criu_op) 560 * 561 * Return: 0 on success, -errno on failure 562 */ 563 struct kfd_ioctl_criu_args { 564 __u64 devices; /* Used during ops: CHECKPOINT, RESTORE */ 565 __u64 bos; /* Used during ops: CHECKPOINT, RESTORE */ 566 __u64 priv_data; /* Used during ops: CHECKPOINT, RESTORE */ 567 __u64 priv_data_size; /* Used during ops: PROCESS_INFO, RESTORE */ 568 __u32 num_devices; /* Used during ops: PROCESS_INFO, RESTORE */ 569 __u32 num_bos; /* Used during ops: PROCESS_INFO, RESTORE */ 570 __u32 num_objects; /* Used during ops: PROCESS_INFO, RESTORE */ 571 __u32 pid; /* Used during ops: PROCESS_INFO, RESUME */ 572 __u32 op; 573 }; 574 575 struct kfd_criu_device_bucket { 576 __u32 user_gpu_id; 577 __u32 actual_gpu_id; 578 __u32 drm_fd; 579 __u32 pad; 580 }; 581 582 struct kfd_criu_bo_bucket { 583 __u64 addr; 584 __u64 size; 585 __u64 offset; 586 __u64 restored_offset; /* During restore, updated offset for BO */ 587 __u32 gpu_id; /* This is the user_gpu_id */ 588 __u32 alloc_flags; 589 __u32 dmabuf_fd; 590 __u32 pad; 591 }; 592 593 /* CRIU IOCTLs - END */ 594 /**************************************************************************************************/ 595 596 /* Register offset inside the remapped mmio page 597 */ 598 enum kfd_mmio_remap { 599 KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL = 0, 600 KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL = 4, 601 }; 602 603 /* Guarantee host access to memory */ 604 #define KFD_IOCTL_SVM_FLAG_HOST_ACCESS 0x00000001 605 /* Fine grained coherency between all devices with access */ 606 #define KFD_IOCTL_SVM_FLAG_COHERENT 0x00000002 607 /* Use any GPU in same hive as preferred device */ 608 #define KFD_IOCTL_SVM_FLAG_HIVE_LOCAL 0x00000004 609 /* GPUs only read, allows replication */ 610 #define KFD_IOCTL_SVM_FLAG_GPU_RO 0x00000008 611 /* Allow execution on GPU */ 612 #define KFD_IOCTL_SVM_FLAG_GPU_EXEC 0x00000010 613 /* GPUs mostly read, may allow similar optimizations as RO, but writes fault */ 614 #define KFD_IOCTL_SVM_FLAG_GPU_READ_MOSTLY 0x00000020 615 616 /** 617 * kfd_ioctl_svm_op - SVM ioctl operations 618 * 619 * @KFD_IOCTL_SVM_OP_SET_ATTR: Modify one or more attributes 620 * @KFD_IOCTL_SVM_OP_GET_ATTR: Query one or more attributes 621 */ 622 enum kfd_ioctl_svm_op { 623 KFD_IOCTL_SVM_OP_SET_ATTR, 624 KFD_IOCTL_SVM_OP_GET_ATTR 625 }; 626 627 /** kfd_ioctl_svm_location - Enum for preferred and prefetch locations 628 * 629 * GPU IDs are used to specify GPUs as preferred and prefetch locations. 630 * Below definitions are used for system memory or for leaving the preferred 631 * location unspecified. 632 */ 633 enum kfd_ioctl_svm_location { 634 KFD_IOCTL_SVM_LOCATION_SYSMEM = 0, 635 KFD_IOCTL_SVM_LOCATION_UNDEFINED = 0xffffffff 636 }; 637 638 /** 639 * kfd_ioctl_svm_attr_type - SVM attribute types 640 * 641 * @KFD_IOCTL_SVM_ATTR_PREFERRED_LOC: gpuid of the preferred location, 0 for 642 * system memory 643 * @KFD_IOCTL_SVM_ATTR_PREFETCH_LOC: gpuid of the prefetch location, 0 for 644 * system memory. Setting this triggers an 645 * immediate prefetch (migration). 646 * @KFD_IOCTL_SVM_ATTR_ACCESS: 647 * @KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE: 648 * @KFD_IOCTL_SVM_ATTR_NO_ACCESS: specify memory access for the gpuid given 649 * by the attribute value 650 * @KFD_IOCTL_SVM_ATTR_SET_FLAGS: bitmask of flags to set (see 651 * KFD_IOCTL_SVM_FLAG_...) 652 * @KFD_IOCTL_SVM_ATTR_CLR_FLAGS: bitmask of flags to clear 653 * @KFD_IOCTL_SVM_ATTR_GRANULARITY: migration granularity 654 * (log2 num pages) 655 */ 656 enum kfd_ioctl_svm_attr_type { 657 KFD_IOCTL_SVM_ATTR_PREFERRED_LOC, 658 KFD_IOCTL_SVM_ATTR_PREFETCH_LOC, 659 KFD_IOCTL_SVM_ATTR_ACCESS, 660 KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE, 661 KFD_IOCTL_SVM_ATTR_NO_ACCESS, 662 KFD_IOCTL_SVM_ATTR_SET_FLAGS, 663 KFD_IOCTL_SVM_ATTR_CLR_FLAGS, 664 KFD_IOCTL_SVM_ATTR_GRANULARITY 665 }; 666 667 /** 668 * kfd_ioctl_svm_attribute - Attributes as pairs of type and value 669 * 670 * The meaning of the @value depends on the attribute type. 671 * 672 * @type: attribute type (see enum @kfd_ioctl_svm_attr_type) 673 * @value: attribute value 674 */ 675 struct kfd_ioctl_svm_attribute { 676 __u32 type; 677 __u32 value; 678 }; 679 680 /** 681 * kfd_ioctl_svm_args - Arguments for SVM ioctl 682 * 683 * @op specifies the operation to perform (see enum 684 * @kfd_ioctl_svm_op). @start_addr and @size are common for all 685 * operations. 686 * 687 * A variable number of attributes can be given in @attrs. 688 * @nattr specifies the number of attributes. New attributes can be 689 * added in the future without breaking the ABI. If unknown attributes 690 * are given, the function returns -EINVAL. 691 * 692 * @KFD_IOCTL_SVM_OP_SET_ATTR sets attributes for a virtual address 693 * range. It may overlap existing virtual address ranges. If it does, 694 * the existing ranges will be split such that the attribute changes 695 * only apply to the specified address range. 696 * 697 * @KFD_IOCTL_SVM_OP_GET_ATTR returns the intersection of attributes 698 * over all memory in the given range and returns the result as the 699 * attribute value. If different pages have different preferred or 700 * prefetch locations, 0xffffffff will be returned for 701 * @KFD_IOCTL_SVM_ATTR_PREFERRED_LOC or 702 * @KFD_IOCTL_SVM_ATTR_PREFETCH_LOC resepctively. For 703 * @KFD_IOCTL_SVM_ATTR_SET_FLAGS, flags of all pages will be 704 * aggregated by bitwise AND. That means, a flag will be set in the 705 * output, if that flag is set for all pages in the range. For 706 * @KFD_IOCTL_SVM_ATTR_CLR_FLAGS, flags of all pages will be 707 * aggregated by bitwise NOR. That means, a flag will be set in the 708 * output, if that flag is clear for all pages in the range. 709 * The minimum migration granularity throughout the range will be 710 * returned for @KFD_IOCTL_SVM_ATTR_GRANULARITY. 711 * 712 * Querying of accessibility attributes works by initializing the 713 * attribute type to @KFD_IOCTL_SVM_ATTR_ACCESS and the value to the 714 * GPUID being queried. Multiple attributes can be given to allow 715 * querying multiple GPUIDs. The ioctl function overwrites the 716 * attribute type to indicate the access for the specified GPU. 717 */ 718 struct kfd_ioctl_svm_args { 719 __u64 start_addr; 720 __u64 size; 721 __u32 op; 722 __u32 nattr; 723 /* Variable length array of attributes */ 724 struct kfd_ioctl_svm_attribute attrs[]; 725 }; 726 727 /** 728 * kfd_ioctl_set_xnack_mode_args - Arguments for set_xnack_mode 729 * 730 * @xnack_enabled: [in/out] Whether to enable XNACK mode for this process 731 * 732 * @xnack_enabled indicates whether recoverable page faults should be 733 * enabled for the current process. 0 means disabled, positive means 734 * enabled, negative means leave unchanged. If enabled, virtual address 735 * translations on GFXv9 and later AMD GPUs can return XNACK and retry 736 * the access until a valid PTE is available. This is used to implement 737 * device page faults. 738 * 739 * On output, @xnack_enabled returns the (new) current mode (0 or 740 * positive). Therefore, a negative input value can be used to query 741 * the current mode without changing it. 742 * 743 * The XNACK mode fundamentally changes the way SVM managed memory works 744 * in the driver, with subtle effects on application performance and 745 * functionality. 746 * 747 * Enabling XNACK mode requires shader programs to be compiled 748 * differently. Furthermore, not all GPUs support changing the mode 749 * per-process. Therefore changing the mode is only allowed while no 750 * user mode queues exist in the process. This ensure that no shader 751 * code is running that may be compiled for the wrong mode. And GPUs 752 * that cannot change to the requested mode will prevent the XNACK 753 * mode from occurring. All GPUs used by the process must be in the 754 * same XNACK mode. 755 * 756 * GFXv8 or older GPUs do not support 48 bit virtual addresses or SVM. 757 * Therefore those GPUs are not considered for the XNACK mode switch. 758 * 759 * Return: 0 on success, -errno on failure 760 */ 761 struct kfd_ioctl_set_xnack_mode_args { 762 __s32 xnack_enabled; 763 }; 764 765 #define AMDKFD_IOCTL_BASE 'K' 766 #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) 767 #define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type) 768 #define AMDKFD_IOW(nr, type) _IOW(AMDKFD_IOCTL_BASE, nr, type) 769 #define AMDKFD_IOWR(nr, type) _IOWR(AMDKFD_IOCTL_BASE, nr, type) 770 771 #define AMDKFD_IOC_GET_VERSION \ 772 AMDKFD_IOR(0x01, struct kfd_ioctl_get_version_args) 773 774 #define AMDKFD_IOC_CREATE_QUEUE \ 775 AMDKFD_IOWR(0x02, struct kfd_ioctl_create_queue_args) 776 777 #define AMDKFD_IOC_DESTROY_QUEUE \ 778 AMDKFD_IOWR(0x03, struct kfd_ioctl_destroy_queue_args) 779 780 #define AMDKFD_IOC_SET_MEMORY_POLICY \ 781 AMDKFD_IOW(0x04, struct kfd_ioctl_set_memory_policy_args) 782 783 #define AMDKFD_IOC_GET_CLOCK_COUNTERS \ 784 AMDKFD_IOWR(0x05, struct kfd_ioctl_get_clock_counters_args) 785 786 #define AMDKFD_IOC_GET_PROCESS_APERTURES \ 787 AMDKFD_IOR(0x06, struct kfd_ioctl_get_process_apertures_args) 788 789 #define AMDKFD_IOC_UPDATE_QUEUE \ 790 AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args) 791 792 #define AMDKFD_IOC_CREATE_EVENT \ 793 AMDKFD_IOWR(0x08, struct kfd_ioctl_create_event_args) 794 795 #define AMDKFD_IOC_DESTROY_EVENT \ 796 AMDKFD_IOW(0x09, struct kfd_ioctl_destroy_event_args) 797 798 #define AMDKFD_IOC_SET_EVENT \ 799 AMDKFD_IOW(0x0A, struct kfd_ioctl_set_event_args) 800 801 #define AMDKFD_IOC_RESET_EVENT \ 802 AMDKFD_IOW(0x0B, struct kfd_ioctl_reset_event_args) 803 804 #define AMDKFD_IOC_WAIT_EVENTS \ 805 AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args) 806 807 #define AMDKFD_IOC_DBG_REGISTER_DEPRECATED \ 808 AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args) 809 810 #define AMDKFD_IOC_DBG_UNREGISTER_DEPRECATED \ 811 AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args) 812 813 #define AMDKFD_IOC_DBG_ADDRESS_WATCH_DEPRECATED \ 814 AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args) 815 816 #define AMDKFD_IOC_DBG_WAVE_CONTROL_DEPRECATED \ 817 AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args) 818 819 #define AMDKFD_IOC_SET_SCRATCH_BACKING_VA \ 820 AMDKFD_IOWR(0x11, struct kfd_ioctl_set_scratch_backing_va_args) 821 822 #define AMDKFD_IOC_GET_TILE_CONFIG \ 823 AMDKFD_IOWR(0x12, struct kfd_ioctl_get_tile_config_args) 824 825 #define AMDKFD_IOC_SET_TRAP_HANDLER \ 826 AMDKFD_IOW(0x13, struct kfd_ioctl_set_trap_handler_args) 827 828 #define AMDKFD_IOC_GET_PROCESS_APERTURES_NEW \ 829 AMDKFD_IOWR(0x14, \ 830 struct kfd_ioctl_get_process_apertures_new_args) 831 832 #define AMDKFD_IOC_ACQUIRE_VM \ 833 AMDKFD_IOW(0x15, struct kfd_ioctl_acquire_vm_args) 834 835 #define AMDKFD_IOC_ALLOC_MEMORY_OF_GPU \ 836 AMDKFD_IOWR(0x16, struct kfd_ioctl_alloc_memory_of_gpu_args) 837 838 #define AMDKFD_IOC_FREE_MEMORY_OF_GPU \ 839 AMDKFD_IOW(0x17, struct kfd_ioctl_free_memory_of_gpu_args) 840 841 #define AMDKFD_IOC_MAP_MEMORY_TO_GPU \ 842 AMDKFD_IOWR(0x18, struct kfd_ioctl_map_memory_to_gpu_args) 843 844 #define AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU \ 845 AMDKFD_IOWR(0x19, struct kfd_ioctl_unmap_memory_from_gpu_args) 846 847 #define AMDKFD_IOC_SET_CU_MASK \ 848 AMDKFD_IOW(0x1A, struct kfd_ioctl_set_cu_mask_args) 849 850 #define AMDKFD_IOC_GET_QUEUE_WAVE_STATE \ 851 AMDKFD_IOWR(0x1B, struct kfd_ioctl_get_queue_wave_state_args) 852 853 #define AMDKFD_IOC_GET_DMABUF_INFO \ 854 AMDKFD_IOWR(0x1C, struct kfd_ioctl_get_dmabuf_info_args) 855 856 #define AMDKFD_IOC_IMPORT_DMABUF \ 857 AMDKFD_IOWR(0x1D, struct kfd_ioctl_import_dmabuf_args) 858 859 #define AMDKFD_IOC_ALLOC_QUEUE_GWS \ 860 AMDKFD_IOWR(0x1E, struct kfd_ioctl_alloc_queue_gws_args) 861 862 #define AMDKFD_IOC_SMI_EVENTS \ 863 AMDKFD_IOWR(0x1F, struct kfd_ioctl_smi_events_args) 864 865 #define AMDKFD_IOC_SVM AMDKFD_IOWR(0x20, struct kfd_ioctl_svm_args) 866 867 #define AMDKFD_IOC_SET_XNACK_MODE \ 868 AMDKFD_IOWR(0x21, struct kfd_ioctl_set_xnack_mode_args) 869 870 #define AMDKFD_IOC_CRIU_OP \ 871 AMDKFD_IOWR(0x22, struct kfd_ioctl_criu_args) 872 873 #define AMDKFD_IOC_AVAILABLE_MEMORY \ 874 AMDKFD_IOWR(0x23, struct kfd_ioctl_get_available_memory_args) 875 876 #define AMDKFD_COMMAND_START 0x01 877 #define AMDKFD_COMMAND_END 0x24 878 879 #endif 880