1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #ifndef KFD_IOCTL_H_INCLUDED 24 #define KFD_IOCTL_H_INCLUDED 25 26 #include <drm/drm.h> 27 #include <linux/ioctl.h> 28 29 /* 30 * - 1.1 - initial version 31 * - 1.3 - Add SMI events support 32 * - 1.4 - Indicate new SRAM EDC bit in device properties 33 * - 1.5 - Add SVM API 34 * - 1.6 - Query clear flags in SVM get_attr API 35 * - 1.7 - Checkpoint Restore (CRIU) API 36 * - 1.8 - CRIU - Support for SDMA transfers with GTT BOs 37 * - 1.9 - Add available memory ioctl 38 * - 1.10 - Add SMI profiler event log 39 * - 1.11 - Add unified memory for ctx save/restore area 40 * - 1.12 - Add DMA buf export ioctl 41 */ 42 #define KFD_IOCTL_MAJOR_VERSION 1 43 #define KFD_IOCTL_MINOR_VERSION 12 44 45 struct kfd_ioctl_get_version_args { 46 __u32 major_version; /* from KFD */ 47 __u32 minor_version; /* from KFD */ 48 }; 49 50 /* For kfd_ioctl_create_queue_args.queue_type. */ 51 #define KFD_IOC_QUEUE_TYPE_COMPUTE 0x0 52 #define KFD_IOC_QUEUE_TYPE_SDMA 0x1 53 #define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 0x2 54 #define KFD_IOC_QUEUE_TYPE_SDMA_XGMI 0x3 55 56 #define KFD_MAX_QUEUE_PERCENTAGE 100 57 #define KFD_MAX_QUEUE_PRIORITY 15 58 59 struct kfd_ioctl_create_queue_args { 60 __u64 ring_base_address; /* to KFD */ 61 __u64 write_pointer_address; /* from KFD */ 62 __u64 read_pointer_address; /* from KFD */ 63 __u64 doorbell_offset; /* from KFD */ 64 65 __u32 ring_size; /* to KFD */ 66 __u32 gpu_id; /* to KFD */ 67 __u32 queue_type; /* to KFD */ 68 __u32 queue_percentage; /* to KFD */ 69 __u32 queue_priority; /* to KFD */ 70 __u32 queue_id; /* from KFD */ 71 72 __u64 eop_buffer_address; /* to KFD */ 73 __u64 eop_buffer_size; /* to KFD */ 74 __u64 ctx_save_restore_address; /* to KFD */ 75 __u32 ctx_save_restore_size; /* to KFD */ 76 __u32 ctl_stack_size; /* to KFD */ 77 }; 78 79 struct kfd_ioctl_destroy_queue_args { 80 __u32 queue_id; /* to KFD */ 81 __u32 pad; 82 }; 83 84 struct kfd_ioctl_update_queue_args { 85 __u64 ring_base_address; /* to KFD */ 86 87 __u32 queue_id; /* to KFD */ 88 __u32 ring_size; /* to KFD */ 89 __u32 queue_percentage; /* to KFD */ 90 __u32 queue_priority; /* to KFD */ 91 }; 92 93 struct kfd_ioctl_set_cu_mask_args { 94 __u32 queue_id; /* to KFD */ 95 __u32 num_cu_mask; /* to KFD */ 96 __u64 cu_mask_ptr; /* to KFD */ 97 }; 98 99 struct kfd_ioctl_get_queue_wave_state_args { 100 __u64 ctl_stack_address; /* to KFD */ 101 __u32 ctl_stack_used_size; /* from KFD */ 102 __u32 save_area_used_size; /* from KFD */ 103 __u32 queue_id; /* to KFD */ 104 __u32 pad; 105 }; 106 107 struct kfd_ioctl_get_available_memory_args { 108 __u64 available; /* from KFD */ 109 __u32 gpu_id; /* to KFD */ 110 __u32 pad; 111 }; 112 113 /* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */ 114 #define KFD_IOC_CACHE_POLICY_COHERENT 0 115 #define KFD_IOC_CACHE_POLICY_NONCOHERENT 1 116 117 struct kfd_ioctl_set_memory_policy_args { 118 __u64 alternate_aperture_base; /* to KFD */ 119 __u64 alternate_aperture_size; /* to KFD */ 120 121 __u32 gpu_id; /* to KFD */ 122 __u32 default_policy; /* to KFD */ 123 __u32 alternate_policy; /* to KFD */ 124 __u32 pad; 125 }; 126 127 /* 128 * All counters are monotonic. They are used for profiling of compute jobs. 129 * The profiling is done by userspace. 130 * 131 * In case of GPU reset, the counter should not be affected. 132 */ 133 134 struct kfd_ioctl_get_clock_counters_args { 135 __u64 gpu_clock_counter; /* from KFD */ 136 __u64 cpu_clock_counter; /* from KFD */ 137 __u64 system_clock_counter; /* from KFD */ 138 __u64 system_clock_freq; /* from KFD */ 139 140 __u32 gpu_id; /* to KFD */ 141 __u32 pad; 142 }; 143 144 struct kfd_process_device_apertures { 145 __u64 lds_base; /* from KFD */ 146 __u64 lds_limit; /* from KFD */ 147 __u64 scratch_base; /* from KFD */ 148 __u64 scratch_limit; /* from KFD */ 149 __u64 gpuvm_base; /* from KFD */ 150 __u64 gpuvm_limit; /* from KFD */ 151 __u32 gpu_id; /* from KFD */ 152 __u32 pad; 153 }; 154 155 /* 156 * AMDKFD_IOC_GET_PROCESS_APERTURES is deprecated. Use 157 * AMDKFD_IOC_GET_PROCESS_APERTURES_NEW instead, which supports an 158 * unlimited number of GPUs. 159 */ 160 #define NUM_OF_SUPPORTED_GPUS 7 161 struct kfd_ioctl_get_process_apertures_args { 162 struct kfd_process_device_apertures 163 process_apertures[NUM_OF_SUPPORTED_GPUS];/* from KFD */ 164 165 /* from KFD, should be in the range [1 - NUM_OF_SUPPORTED_GPUS] */ 166 __u32 num_of_nodes; 167 __u32 pad; 168 }; 169 170 struct kfd_ioctl_get_process_apertures_new_args { 171 /* User allocated. Pointer to struct kfd_process_device_apertures 172 * filled in by Kernel 173 */ 174 __u64 kfd_process_device_apertures_ptr; 175 /* to KFD - indicates amount of memory present in 176 * kfd_process_device_apertures_ptr 177 * from KFD - Number of entries filled by KFD. 178 */ 179 __u32 num_of_nodes; 180 __u32 pad; 181 }; 182 183 #define MAX_ALLOWED_NUM_POINTS 100 184 #define MAX_ALLOWED_AW_BUFF_SIZE 4096 185 #define MAX_ALLOWED_WAC_BUFF_SIZE 128 186 187 struct kfd_ioctl_dbg_register_args { 188 __u32 gpu_id; /* to KFD */ 189 __u32 pad; 190 }; 191 192 struct kfd_ioctl_dbg_unregister_args { 193 __u32 gpu_id; /* to KFD */ 194 __u32 pad; 195 }; 196 197 struct kfd_ioctl_dbg_address_watch_args { 198 __u64 content_ptr; /* a pointer to the actual content */ 199 __u32 gpu_id; /* to KFD */ 200 __u32 buf_size_in_bytes; /*including gpu_id and buf_size */ 201 }; 202 203 struct kfd_ioctl_dbg_wave_control_args { 204 __u64 content_ptr; /* a pointer to the actual content */ 205 __u32 gpu_id; /* to KFD */ 206 __u32 buf_size_in_bytes; /*including gpu_id and buf_size */ 207 }; 208 209 #define KFD_INVALID_FD 0xffffffff 210 211 /* Matching HSA_EVENTTYPE */ 212 #define KFD_IOC_EVENT_SIGNAL 0 213 #define KFD_IOC_EVENT_NODECHANGE 1 214 #define KFD_IOC_EVENT_DEVICESTATECHANGE 2 215 #define KFD_IOC_EVENT_HW_EXCEPTION 3 216 #define KFD_IOC_EVENT_SYSTEM_EVENT 4 217 #define KFD_IOC_EVENT_DEBUG_EVENT 5 218 #define KFD_IOC_EVENT_PROFILE_EVENT 6 219 #define KFD_IOC_EVENT_QUEUE_EVENT 7 220 #define KFD_IOC_EVENT_MEMORY 8 221 222 #define KFD_IOC_WAIT_RESULT_COMPLETE 0 223 #define KFD_IOC_WAIT_RESULT_TIMEOUT 1 224 #define KFD_IOC_WAIT_RESULT_FAIL 2 225 226 #define KFD_SIGNAL_EVENT_LIMIT 4096 227 228 /* For kfd_event_data.hw_exception_data.reset_type. */ 229 #define KFD_HW_EXCEPTION_WHOLE_GPU_RESET 0 230 #define KFD_HW_EXCEPTION_PER_ENGINE_RESET 1 231 232 /* For kfd_event_data.hw_exception_data.reset_cause. */ 233 #define KFD_HW_EXCEPTION_GPU_HANG 0 234 #define KFD_HW_EXCEPTION_ECC 1 235 236 /* For kfd_hsa_memory_exception_data.ErrorType */ 237 #define KFD_MEM_ERR_NO_RAS 0 238 #define KFD_MEM_ERR_SRAM_ECC 1 239 #define KFD_MEM_ERR_POISON_CONSUMED 2 240 #define KFD_MEM_ERR_GPU_HANG 3 241 242 struct kfd_ioctl_create_event_args { 243 __u64 event_page_offset; /* from KFD */ 244 __u32 event_trigger_data; /* from KFD - signal events only */ 245 __u32 event_type; /* to KFD */ 246 __u32 auto_reset; /* to KFD */ 247 __u32 node_id; /* to KFD - only valid for certain 248 event types */ 249 __u32 event_id; /* from KFD */ 250 __u32 event_slot_index; /* from KFD */ 251 }; 252 253 struct kfd_ioctl_destroy_event_args { 254 __u32 event_id; /* to KFD */ 255 __u32 pad; 256 }; 257 258 struct kfd_ioctl_set_event_args { 259 __u32 event_id; /* to KFD */ 260 __u32 pad; 261 }; 262 263 struct kfd_ioctl_reset_event_args { 264 __u32 event_id; /* to KFD */ 265 __u32 pad; 266 }; 267 268 struct kfd_memory_exception_failure { 269 __u32 NotPresent; /* Page not present or supervisor privilege */ 270 __u32 ReadOnly; /* Write access to a read-only page */ 271 __u32 NoExecute; /* Execute access to a page marked NX */ 272 __u32 imprecise; /* Can't determine the exact fault address */ 273 }; 274 275 /* memory exception data */ 276 struct kfd_hsa_memory_exception_data { 277 struct kfd_memory_exception_failure failure; 278 __u64 va; 279 __u32 gpu_id; 280 __u32 ErrorType; /* 0 = no RAS error, 281 * 1 = ECC_SRAM, 282 * 2 = Link_SYNFLOOD (poison), 283 * 3 = GPU hang (not attributable to a specific cause), 284 * other values reserved 285 */ 286 }; 287 288 /* hw exception data */ 289 struct kfd_hsa_hw_exception_data { 290 __u32 reset_type; 291 __u32 reset_cause; 292 __u32 memory_lost; 293 __u32 gpu_id; 294 }; 295 296 /* Event data */ 297 struct kfd_event_data { 298 union { 299 struct kfd_hsa_memory_exception_data memory_exception_data; 300 struct kfd_hsa_hw_exception_data hw_exception_data; 301 }; /* From KFD */ 302 __u64 kfd_event_data_ext; /* pointer to an extension structure 303 for future exception types */ 304 __u32 event_id; /* to KFD */ 305 __u32 pad; 306 }; 307 308 struct kfd_ioctl_wait_events_args { 309 __u64 events_ptr; /* pointed to struct 310 kfd_event_data array, to KFD */ 311 __u32 num_events; /* to KFD */ 312 __u32 wait_for_all; /* to KFD */ 313 __u32 timeout; /* to KFD */ 314 __u32 wait_result; /* from KFD */ 315 }; 316 317 struct kfd_ioctl_set_scratch_backing_va_args { 318 __u64 va_addr; /* to KFD */ 319 __u32 gpu_id; /* to KFD */ 320 __u32 pad; 321 }; 322 323 struct kfd_ioctl_get_tile_config_args { 324 /* to KFD: pointer to tile array */ 325 __u64 tile_config_ptr; 326 /* to KFD: pointer to macro tile array */ 327 __u64 macro_tile_config_ptr; 328 /* to KFD: array size allocated by user mode 329 * from KFD: array size filled by kernel 330 */ 331 __u32 num_tile_configs; 332 /* to KFD: array size allocated by user mode 333 * from KFD: array size filled by kernel 334 */ 335 __u32 num_macro_tile_configs; 336 337 __u32 gpu_id; /* to KFD */ 338 __u32 gb_addr_config; /* from KFD */ 339 __u32 num_banks; /* from KFD */ 340 __u32 num_ranks; /* from KFD */ 341 /* struct size can be extended later if needed 342 * without breaking ABI compatibility 343 */ 344 }; 345 346 struct kfd_ioctl_set_trap_handler_args { 347 __u64 tba_addr; /* to KFD */ 348 __u64 tma_addr; /* to KFD */ 349 __u32 gpu_id; /* to KFD */ 350 __u32 pad; 351 }; 352 353 struct kfd_ioctl_acquire_vm_args { 354 __u32 drm_fd; /* to KFD */ 355 __u32 gpu_id; /* to KFD */ 356 }; 357 358 /* Allocation flags: memory types */ 359 #define KFD_IOC_ALLOC_MEM_FLAGS_VRAM (1 << 0) 360 #define KFD_IOC_ALLOC_MEM_FLAGS_GTT (1 << 1) 361 #define KFD_IOC_ALLOC_MEM_FLAGS_USERPTR (1 << 2) 362 #define KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL (1 << 3) 363 #define KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP (1 << 4) 364 /* Allocation flags: attributes/access options */ 365 #define KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE (1 << 31) 366 #define KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE (1 << 30) 367 #define KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC (1 << 29) 368 #define KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE (1 << 28) 369 #define KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM (1 << 27) 370 #define KFD_IOC_ALLOC_MEM_FLAGS_COHERENT (1 << 26) 371 #define KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED (1 << 25) 372 373 /* Allocate memory for later SVM (shared virtual memory) mapping. 374 * 375 * @va_addr: virtual address of the memory to be allocated 376 * all later mappings on all GPUs will use this address 377 * @size: size in bytes 378 * @handle: buffer handle returned to user mode, used to refer to 379 * this allocation for mapping, unmapping and freeing 380 * @mmap_offset: for CPU-mapping the allocation by mmapping a render node 381 * for userptrs this is overloaded to specify the CPU address 382 * @gpu_id: device identifier 383 * @flags: memory type and attributes. See KFD_IOC_ALLOC_MEM_FLAGS above 384 */ 385 struct kfd_ioctl_alloc_memory_of_gpu_args { 386 __u64 va_addr; /* to KFD */ 387 __u64 size; /* to KFD */ 388 __u64 handle; /* from KFD */ 389 __u64 mmap_offset; /* to KFD (userptr), from KFD (mmap offset) */ 390 __u32 gpu_id; /* to KFD */ 391 __u32 flags; 392 }; 393 394 /* Free memory allocated with kfd_ioctl_alloc_memory_of_gpu 395 * 396 * @handle: memory handle returned by alloc 397 */ 398 struct kfd_ioctl_free_memory_of_gpu_args { 399 __u64 handle; /* to KFD */ 400 }; 401 402 /* Map memory to one or more GPUs 403 * 404 * @handle: memory handle returned by alloc 405 * @device_ids_array_ptr: array of gpu_ids (__u32 per device) 406 * @n_devices: number of devices in the array 407 * @n_success: number of devices mapped successfully 408 * 409 * @n_success returns information to the caller how many devices from 410 * the start of the array have mapped the buffer successfully. It can 411 * be passed into a subsequent retry call to skip those devices. For 412 * the first call the caller should initialize it to 0. 413 * 414 * If the ioctl completes with return code 0 (success), n_success == 415 * n_devices. 416 */ 417 struct kfd_ioctl_map_memory_to_gpu_args { 418 __u64 handle; /* to KFD */ 419 __u64 device_ids_array_ptr; /* to KFD */ 420 __u32 n_devices; /* to KFD */ 421 __u32 n_success; /* to/from KFD */ 422 }; 423 424 /* Unmap memory from one or more GPUs 425 * 426 * same arguments as for mapping 427 */ 428 struct kfd_ioctl_unmap_memory_from_gpu_args { 429 __u64 handle; /* to KFD */ 430 __u64 device_ids_array_ptr; /* to KFD */ 431 __u32 n_devices; /* to KFD */ 432 __u32 n_success; /* to/from KFD */ 433 }; 434 435 /* Allocate GWS for specific queue 436 * 437 * @queue_id: queue's id that GWS is allocated for 438 * @num_gws: how many GWS to allocate 439 * @first_gws: index of the first GWS allocated. 440 * only support contiguous GWS allocation 441 */ 442 struct kfd_ioctl_alloc_queue_gws_args { 443 __u32 queue_id; /* to KFD */ 444 __u32 num_gws; /* to KFD */ 445 __u32 first_gws; /* from KFD */ 446 __u32 pad; 447 }; 448 449 struct kfd_ioctl_get_dmabuf_info_args { 450 __u64 size; /* from KFD */ 451 __u64 metadata_ptr; /* to KFD */ 452 __u32 metadata_size; /* to KFD (space allocated by user) 453 * from KFD (actual metadata size) 454 */ 455 __u32 gpu_id; /* from KFD */ 456 __u32 flags; /* from KFD (KFD_IOC_ALLOC_MEM_FLAGS) */ 457 __u32 dmabuf_fd; /* to KFD */ 458 }; 459 460 struct kfd_ioctl_import_dmabuf_args { 461 __u64 va_addr; /* to KFD */ 462 __u64 handle; /* from KFD */ 463 __u32 gpu_id; /* to KFD */ 464 __u32 dmabuf_fd; /* to KFD */ 465 }; 466 467 struct kfd_ioctl_export_dmabuf_args { 468 __u64 handle; /* to KFD */ 469 __u32 flags; /* to KFD */ 470 __u32 dmabuf_fd; /* from KFD */ 471 }; 472 473 /* 474 * KFD SMI(System Management Interface) events 475 */ 476 enum kfd_smi_event { 477 KFD_SMI_EVENT_NONE = 0, /* not used */ 478 KFD_SMI_EVENT_VMFAULT = 1, /* event start counting at 1 */ 479 KFD_SMI_EVENT_THERMAL_THROTTLE = 2, 480 KFD_SMI_EVENT_GPU_PRE_RESET = 3, 481 KFD_SMI_EVENT_GPU_POST_RESET = 4, 482 KFD_SMI_EVENT_MIGRATE_START = 5, 483 KFD_SMI_EVENT_MIGRATE_END = 6, 484 KFD_SMI_EVENT_PAGE_FAULT_START = 7, 485 KFD_SMI_EVENT_PAGE_FAULT_END = 8, 486 KFD_SMI_EVENT_QUEUE_EVICTION = 9, 487 KFD_SMI_EVENT_QUEUE_RESTORE = 10, 488 KFD_SMI_EVENT_UNMAP_FROM_GPU = 11, 489 490 /* 491 * max event number, as a flag bit to get events from all processes, 492 * this requires super user permission, otherwise will not be able to 493 * receive event from any process. Without this flag to receive events 494 * from same process. 495 */ 496 KFD_SMI_EVENT_ALL_PROCESS = 64 497 }; 498 499 enum KFD_MIGRATE_TRIGGERS { 500 KFD_MIGRATE_TRIGGER_PREFETCH, 501 KFD_MIGRATE_TRIGGER_PAGEFAULT_GPU, 502 KFD_MIGRATE_TRIGGER_PAGEFAULT_CPU, 503 KFD_MIGRATE_TRIGGER_TTM_EVICTION 504 }; 505 506 enum KFD_QUEUE_EVICTION_TRIGGERS { 507 KFD_QUEUE_EVICTION_TRIGGER_SVM, 508 KFD_QUEUE_EVICTION_TRIGGER_USERPTR, 509 KFD_QUEUE_EVICTION_TRIGGER_TTM, 510 KFD_QUEUE_EVICTION_TRIGGER_SUSPEND, 511 KFD_QUEUE_EVICTION_CRIU_CHECKPOINT, 512 KFD_QUEUE_EVICTION_CRIU_RESTORE 513 }; 514 515 enum KFD_SVM_UNMAP_TRIGGERS { 516 KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY, 517 KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY_MIGRATE, 518 KFD_SVM_UNMAP_TRIGGER_UNMAP_FROM_CPU 519 }; 520 521 #define KFD_SMI_EVENT_MASK_FROM_INDEX(i) (1ULL << ((i) - 1)) 522 #define KFD_SMI_EVENT_MSG_SIZE 96 523 524 struct kfd_ioctl_smi_events_args { 525 __u32 gpuid; /* to KFD */ 526 __u32 anon_fd; /* from KFD */ 527 }; 528 529 /************************************************************************************************** 530 * CRIU IOCTLs (Checkpoint Restore In Userspace) 531 * 532 * When checkpointing a process, the userspace application will perform: 533 * 1. PROCESS_INFO op to determine current process information. This pauses execution and evicts 534 * all the queues. 535 * 2. CHECKPOINT op to checkpoint process contents (BOs, queues, events, svm-ranges) 536 * 3. UNPAUSE op to un-evict all the queues 537 * 538 * When restoring a process, the CRIU userspace application will perform: 539 * 540 * 1. RESTORE op to restore process contents 541 * 2. RESUME op to start the process 542 * 543 * Note: Queues are forced into an evicted state after a successful PROCESS_INFO. User 544 * application needs to perform an UNPAUSE operation after calling PROCESS_INFO. 545 */ 546 547 enum kfd_criu_op { 548 KFD_CRIU_OP_PROCESS_INFO, 549 KFD_CRIU_OP_CHECKPOINT, 550 KFD_CRIU_OP_UNPAUSE, 551 KFD_CRIU_OP_RESTORE, 552 KFD_CRIU_OP_RESUME, 553 }; 554 555 /** 556 * kfd_ioctl_criu_args - Arguments perform CRIU operation 557 * @devices: [in/out] User pointer to memory location for devices information. 558 * This is an array of type kfd_criu_device_bucket. 559 * @bos: [in/out] User pointer to memory location for BOs information 560 * This is an array of type kfd_criu_bo_bucket. 561 * @priv_data: [in/out] User pointer to memory location for private data 562 * @priv_data_size: [in/out] Size of priv_data in bytes 563 * @num_devices: [in/out] Number of GPUs used by process. Size of @devices array. 564 * @num_bos [in/out] Number of BOs used by process. Size of @bos array. 565 * @num_objects: [in/out] Number of objects used by process. Objects are opaque to 566 * user application. 567 * @pid: [in/out] PID of the process being checkpointed 568 * @op [in] Type of operation (kfd_criu_op) 569 * 570 * Return: 0 on success, -errno on failure 571 */ 572 struct kfd_ioctl_criu_args { 573 __u64 devices; /* Used during ops: CHECKPOINT, RESTORE */ 574 __u64 bos; /* Used during ops: CHECKPOINT, RESTORE */ 575 __u64 priv_data; /* Used during ops: CHECKPOINT, RESTORE */ 576 __u64 priv_data_size; /* Used during ops: PROCESS_INFO, RESTORE */ 577 __u32 num_devices; /* Used during ops: PROCESS_INFO, RESTORE */ 578 __u32 num_bos; /* Used during ops: PROCESS_INFO, RESTORE */ 579 __u32 num_objects; /* Used during ops: PROCESS_INFO, RESTORE */ 580 __u32 pid; /* Used during ops: PROCESS_INFO, RESUME */ 581 __u32 op; 582 }; 583 584 struct kfd_criu_device_bucket { 585 __u32 user_gpu_id; 586 __u32 actual_gpu_id; 587 __u32 drm_fd; 588 __u32 pad; 589 }; 590 591 struct kfd_criu_bo_bucket { 592 __u64 addr; 593 __u64 size; 594 __u64 offset; 595 __u64 restored_offset; /* During restore, updated offset for BO */ 596 __u32 gpu_id; /* This is the user_gpu_id */ 597 __u32 alloc_flags; 598 __u32 dmabuf_fd; 599 __u32 pad; 600 }; 601 602 /* CRIU IOCTLs - END */ 603 /**************************************************************************************************/ 604 605 /* Register offset inside the remapped mmio page 606 */ 607 enum kfd_mmio_remap { 608 KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL = 0, 609 KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL = 4, 610 }; 611 612 /* Guarantee host access to memory */ 613 #define KFD_IOCTL_SVM_FLAG_HOST_ACCESS 0x00000001 614 /* Fine grained coherency between all devices with access */ 615 #define KFD_IOCTL_SVM_FLAG_COHERENT 0x00000002 616 /* Use any GPU in same hive as preferred device */ 617 #define KFD_IOCTL_SVM_FLAG_HIVE_LOCAL 0x00000004 618 /* GPUs only read, allows replication */ 619 #define KFD_IOCTL_SVM_FLAG_GPU_RO 0x00000008 620 /* Allow execution on GPU */ 621 #define KFD_IOCTL_SVM_FLAG_GPU_EXEC 0x00000010 622 /* GPUs mostly read, may allow similar optimizations as RO, but writes fault */ 623 #define KFD_IOCTL_SVM_FLAG_GPU_READ_MOSTLY 0x00000020 624 /* Keep GPU memory mapping always valid as if XNACK is disable */ 625 #define KFD_IOCTL_SVM_FLAG_GPU_ALWAYS_MAPPED 0x00000040 626 627 /** 628 * kfd_ioctl_svm_op - SVM ioctl operations 629 * 630 * @KFD_IOCTL_SVM_OP_SET_ATTR: Modify one or more attributes 631 * @KFD_IOCTL_SVM_OP_GET_ATTR: Query one or more attributes 632 */ 633 enum kfd_ioctl_svm_op { 634 KFD_IOCTL_SVM_OP_SET_ATTR, 635 KFD_IOCTL_SVM_OP_GET_ATTR 636 }; 637 638 /** kfd_ioctl_svm_location - Enum for preferred and prefetch locations 639 * 640 * GPU IDs are used to specify GPUs as preferred and prefetch locations. 641 * Below definitions are used for system memory or for leaving the preferred 642 * location unspecified. 643 */ 644 enum kfd_ioctl_svm_location { 645 KFD_IOCTL_SVM_LOCATION_SYSMEM = 0, 646 KFD_IOCTL_SVM_LOCATION_UNDEFINED = 0xffffffff 647 }; 648 649 /** 650 * kfd_ioctl_svm_attr_type - SVM attribute types 651 * 652 * @KFD_IOCTL_SVM_ATTR_PREFERRED_LOC: gpuid of the preferred location, 0 for 653 * system memory 654 * @KFD_IOCTL_SVM_ATTR_PREFETCH_LOC: gpuid of the prefetch location, 0 for 655 * system memory. Setting this triggers an 656 * immediate prefetch (migration). 657 * @KFD_IOCTL_SVM_ATTR_ACCESS: 658 * @KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE: 659 * @KFD_IOCTL_SVM_ATTR_NO_ACCESS: specify memory access for the gpuid given 660 * by the attribute value 661 * @KFD_IOCTL_SVM_ATTR_SET_FLAGS: bitmask of flags to set (see 662 * KFD_IOCTL_SVM_FLAG_...) 663 * @KFD_IOCTL_SVM_ATTR_CLR_FLAGS: bitmask of flags to clear 664 * @KFD_IOCTL_SVM_ATTR_GRANULARITY: migration granularity 665 * (log2 num pages) 666 */ 667 enum kfd_ioctl_svm_attr_type { 668 KFD_IOCTL_SVM_ATTR_PREFERRED_LOC, 669 KFD_IOCTL_SVM_ATTR_PREFETCH_LOC, 670 KFD_IOCTL_SVM_ATTR_ACCESS, 671 KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE, 672 KFD_IOCTL_SVM_ATTR_NO_ACCESS, 673 KFD_IOCTL_SVM_ATTR_SET_FLAGS, 674 KFD_IOCTL_SVM_ATTR_CLR_FLAGS, 675 KFD_IOCTL_SVM_ATTR_GRANULARITY 676 }; 677 678 /** 679 * kfd_ioctl_svm_attribute - Attributes as pairs of type and value 680 * 681 * The meaning of the @value depends on the attribute type. 682 * 683 * @type: attribute type (see enum @kfd_ioctl_svm_attr_type) 684 * @value: attribute value 685 */ 686 struct kfd_ioctl_svm_attribute { 687 __u32 type; 688 __u32 value; 689 }; 690 691 /** 692 * kfd_ioctl_svm_args - Arguments for SVM ioctl 693 * 694 * @op specifies the operation to perform (see enum 695 * @kfd_ioctl_svm_op). @start_addr and @size are common for all 696 * operations. 697 * 698 * A variable number of attributes can be given in @attrs. 699 * @nattr specifies the number of attributes. New attributes can be 700 * added in the future without breaking the ABI. If unknown attributes 701 * are given, the function returns -EINVAL. 702 * 703 * @KFD_IOCTL_SVM_OP_SET_ATTR sets attributes for a virtual address 704 * range. It may overlap existing virtual address ranges. If it does, 705 * the existing ranges will be split such that the attribute changes 706 * only apply to the specified address range. 707 * 708 * @KFD_IOCTL_SVM_OP_GET_ATTR returns the intersection of attributes 709 * over all memory in the given range and returns the result as the 710 * attribute value. If different pages have different preferred or 711 * prefetch locations, 0xffffffff will be returned for 712 * @KFD_IOCTL_SVM_ATTR_PREFERRED_LOC or 713 * @KFD_IOCTL_SVM_ATTR_PREFETCH_LOC resepctively. For 714 * @KFD_IOCTL_SVM_ATTR_SET_FLAGS, flags of all pages will be 715 * aggregated by bitwise AND. That means, a flag will be set in the 716 * output, if that flag is set for all pages in the range. For 717 * @KFD_IOCTL_SVM_ATTR_CLR_FLAGS, flags of all pages will be 718 * aggregated by bitwise NOR. That means, a flag will be set in the 719 * output, if that flag is clear for all pages in the range. 720 * The minimum migration granularity throughout the range will be 721 * returned for @KFD_IOCTL_SVM_ATTR_GRANULARITY. 722 * 723 * Querying of accessibility attributes works by initializing the 724 * attribute type to @KFD_IOCTL_SVM_ATTR_ACCESS and the value to the 725 * GPUID being queried. Multiple attributes can be given to allow 726 * querying multiple GPUIDs. The ioctl function overwrites the 727 * attribute type to indicate the access for the specified GPU. 728 */ 729 struct kfd_ioctl_svm_args { 730 __u64 start_addr; 731 __u64 size; 732 __u32 op; 733 __u32 nattr; 734 /* Variable length array of attributes */ 735 struct kfd_ioctl_svm_attribute attrs[]; 736 }; 737 738 /** 739 * kfd_ioctl_set_xnack_mode_args - Arguments for set_xnack_mode 740 * 741 * @xnack_enabled: [in/out] Whether to enable XNACK mode for this process 742 * 743 * @xnack_enabled indicates whether recoverable page faults should be 744 * enabled for the current process. 0 means disabled, positive means 745 * enabled, negative means leave unchanged. If enabled, virtual address 746 * translations on GFXv9 and later AMD GPUs can return XNACK and retry 747 * the access until a valid PTE is available. This is used to implement 748 * device page faults. 749 * 750 * On output, @xnack_enabled returns the (new) current mode (0 or 751 * positive). Therefore, a negative input value can be used to query 752 * the current mode without changing it. 753 * 754 * The XNACK mode fundamentally changes the way SVM managed memory works 755 * in the driver, with subtle effects on application performance and 756 * functionality. 757 * 758 * Enabling XNACK mode requires shader programs to be compiled 759 * differently. Furthermore, not all GPUs support changing the mode 760 * per-process. Therefore changing the mode is only allowed while no 761 * user mode queues exist in the process. This ensure that no shader 762 * code is running that may be compiled for the wrong mode. And GPUs 763 * that cannot change to the requested mode will prevent the XNACK 764 * mode from occurring. All GPUs used by the process must be in the 765 * same XNACK mode. 766 * 767 * GFXv8 or older GPUs do not support 48 bit virtual addresses or SVM. 768 * Therefore those GPUs are not considered for the XNACK mode switch. 769 * 770 * Return: 0 on success, -errno on failure 771 */ 772 struct kfd_ioctl_set_xnack_mode_args { 773 __s32 xnack_enabled; 774 }; 775 776 #define AMDKFD_IOCTL_BASE 'K' 777 #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) 778 #define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type) 779 #define AMDKFD_IOW(nr, type) _IOW(AMDKFD_IOCTL_BASE, nr, type) 780 #define AMDKFD_IOWR(nr, type) _IOWR(AMDKFD_IOCTL_BASE, nr, type) 781 782 #define AMDKFD_IOC_GET_VERSION \ 783 AMDKFD_IOR(0x01, struct kfd_ioctl_get_version_args) 784 785 #define AMDKFD_IOC_CREATE_QUEUE \ 786 AMDKFD_IOWR(0x02, struct kfd_ioctl_create_queue_args) 787 788 #define AMDKFD_IOC_DESTROY_QUEUE \ 789 AMDKFD_IOWR(0x03, struct kfd_ioctl_destroy_queue_args) 790 791 #define AMDKFD_IOC_SET_MEMORY_POLICY \ 792 AMDKFD_IOW(0x04, struct kfd_ioctl_set_memory_policy_args) 793 794 #define AMDKFD_IOC_GET_CLOCK_COUNTERS \ 795 AMDKFD_IOWR(0x05, struct kfd_ioctl_get_clock_counters_args) 796 797 #define AMDKFD_IOC_GET_PROCESS_APERTURES \ 798 AMDKFD_IOR(0x06, struct kfd_ioctl_get_process_apertures_args) 799 800 #define AMDKFD_IOC_UPDATE_QUEUE \ 801 AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args) 802 803 #define AMDKFD_IOC_CREATE_EVENT \ 804 AMDKFD_IOWR(0x08, struct kfd_ioctl_create_event_args) 805 806 #define AMDKFD_IOC_DESTROY_EVENT \ 807 AMDKFD_IOW(0x09, struct kfd_ioctl_destroy_event_args) 808 809 #define AMDKFD_IOC_SET_EVENT \ 810 AMDKFD_IOW(0x0A, struct kfd_ioctl_set_event_args) 811 812 #define AMDKFD_IOC_RESET_EVENT \ 813 AMDKFD_IOW(0x0B, struct kfd_ioctl_reset_event_args) 814 815 #define AMDKFD_IOC_WAIT_EVENTS \ 816 AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args) 817 818 #define AMDKFD_IOC_DBG_REGISTER_DEPRECATED \ 819 AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args) 820 821 #define AMDKFD_IOC_DBG_UNREGISTER_DEPRECATED \ 822 AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args) 823 824 #define AMDKFD_IOC_DBG_ADDRESS_WATCH_DEPRECATED \ 825 AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args) 826 827 #define AMDKFD_IOC_DBG_WAVE_CONTROL_DEPRECATED \ 828 AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args) 829 830 #define AMDKFD_IOC_SET_SCRATCH_BACKING_VA \ 831 AMDKFD_IOWR(0x11, struct kfd_ioctl_set_scratch_backing_va_args) 832 833 #define AMDKFD_IOC_GET_TILE_CONFIG \ 834 AMDKFD_IOWR(0x12, struct kfd_ioctl_get_tile_config_args) 835 836 #define AMDKFD_IOC_SET_TRAP_HANDLER \ 837 AMDKFD_IOW(0x13, struct kfd_ioctl_set_trap_handler_args) 838 839 #define AMDKFD_IOC_GET_PROCESS_APERTURES_NEW \ 840 AMDKFD_IOWR(0x14, \ 841 struct kfd_ioctl_get_process_apertures_new_args) 842 843 #define AMDKFD_IOC_ACQUIRE_VM \ 844 AMDKFD_IOW(0x15, struct kfd_ioctl_acquire_vm_args) 845 846 #define AMDKFD_IOC_ALLOC_MEMORY_OF_GPU \ 847 AMDKFD_IOWR(0x16, struct kfd_ioctl_alloc_memory_of_gpu_args) 848 849 #define AMDKFD_IOC_FREE_MEMORY_OF_GPU \ 850 AMDKFD_IOW(0x17, struct kfd_ioctl_free_memory_of_gpu_args) 851 852 #define AMDKFD_IOC_MAP_MEMORY_TO_GPU \ 853 AMDKFD_IOWR(0x18, struct kfd_ioctl_map_memory_to_gpu_args) 854 855 #define AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU \ 856 AMDKFD_IOWR(0x19, struct kfd_ioctl_unmap_memory_from_gpu_args) 857 858 #define AMDKFD_IOC_SET_CU_MASK \ 859 AMDKFD_IOW(0x1A, struct kfd_ioctl_set_cu_mask_args) 860 861 #define AMDKFD_IOC_GET_QUEUE_WAVE_STATE \ 862 AMDKFD_IOWR(0x1B, struct kfd_ioctl_get_queue_wave_state_args) 863 864 #define AMDKFD_IOC_GET_DMABUF_INFO \ 865 AMDKFD_IOWR(0x1C, struct kfd_ioctl_get_dmabuf_info_args) 866 867 #define AMDKFD_IOC_IMPORT_DMABUF \ 868 AMDKFD_IOWR(0x1D, struct kfd_ioctl_import_dmabuf_args) 869 870 #define AMDKFD_IOC_ALLOC_QUEUE_GWS \ 871 AMDKFD_IOWR(0x1E, struct kfd_ioctl_alloc_queue_gws_args) 872 873 #define AMDKFD_IOC_SMI_EVENTS \ 874 AMDKFD_IOWR(0x1F, struct kfd_ioctl_smi_events_args) 875 876 #define AMDKFD_IOC_SVM AMDKFD_IOWR(0x20, struct kfd_ioctl_svm_args) 877 878 #define AMDKFD_IOC_SET_XNACK_MODE \ 879 AMDKFD_IOWR(0x21, struct kfd_ioctl_set_xnack_mode_args) 880 881 #define AMDKFD_IOC_CRIU_OP \ 882 AMDKFD_IOWR(0x22, struct kfd_ioctl_criu_args) 883 884 #define AMDKFD_IOC_AVAILABLE_MEMORY \ 885 AMDKFD_IOWR(0x23, struct kfd_ioctl_get_available_memory_args) 886 887 #define AMDKFD_IOC_EXPORT_DMABUF \ 888 AMDKFD_IOWR(0x24, struct kfd_ioctl_export_dmabuf_args) 889 890 #define AMDKFD_COMMAND_START 0x01 891 #define AMDKFD_COMMAND_END 0x25 892 893 #endif 894