1 /* SPDX-License-Identifier: LGPL-2.1 WITH Linux-syscall-note */ 2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3 #ifndef _USR_IDXD_H_ 4 #define _USR_IDXD_H_ 5 6 #ifdef __KERNEL__ 7 #include <linux/types.h> 8 #else 9 #include <stdint.h> 10 #endif 11 12 /* Driver command error status */ 13 enum idxd_scmd_stat { 14 IDXD_SCMD_DEV_ENABLED = 0x80000010, 15 IDXD_SCMD_DEV_NOT_ENABLED = 0x80000020, 16 IDXD_SCMD_WQ_ENABLED = 0x80000021, 17 IDXD_SCMD_DEV_DMA_ERR = 0x80020000, 18 IDXD_SCMD_WQ_NO_GRP = 0x80030000, 19 IDXD_SCMD_WQ_NO_NAME = 0x80040000, 20 IDXD_SCMD_WQ_NO_SVM = 0x80050000, 21 IDXD_SCMD_WQ_NO_THRESH = 0x80060000, 22 IDXD_SCMD_WQ_PORTAL_ERR = 0x80070000, 23 IDXD_SCMD_WQ_RES_ALLOC_ERR = 0x80080000, 24 IDXD_SCMD_PERCPU_ERR = 0x80090000, 25 IDXD_SCMD_DMA_CHAN_ERR = 0x800a0000, 26 IDXD_SCMD_CDEV_ERR = 0x800b0000, 27 IDXD_SCMD_WQ_NO_SWQ_SUPPORT = 0x800c0000, 28 IDXD_SCMD_WQ_NONE_CONFIGURED = 0x800d0000, 29 IDXD_SCMD_WQ_NO_SIZE = 0x800e0000, 30 IDXD_SCMD_WQ_NO_PRIV = 0x800f0000, 31 IDXD_SCMD_WQ_IRQ_ERR = 0x80100000, 32 IDXD_SCMD_WQ_USER_NO_IOMMU = 0x80110000, 33 IDXD_SCMD_DEV_EVL_ERR = 0x80120000, 34 }; 35 36 #define IDXD_SCMD_SOFTERR_MASK 0x80000000 37 #define IDXD_SCMD_SOFTERR_SHIFT 16 38 39 /* Descriptor flags */ 40 #define IDXD_OP_FLAG_FENCE 0x0001 41 #define IDXD_OP_FLAG_BOF 0x0002 42 #define IDXD_OP_FLAG_CRAV 0x0004 43 #define IDXD_OP_FLAG_RCR 0x0008 44 #define IDXD_OP_FLAG_RCI 0x0010 45 #define IDXD_OP_FLAG_CRSTS 0x0020 46 #define IDXD_OP_FLAG_CR 0x0080 47 #define IDXD_OP_FLAG_CC 0x0100 48 #define IDXD_OP_FLAG_ADDR1_TCS 0x0200 49 #define IDXD_OP_FLAG_ADDR2_TCS 0x0400 50 #define IDXD_OP_FLAG_ADDR3_TCS 0x0800 51 #define IDXD_OP_FLAG_CR_TCS 0x1000 52 #define IDXD_OP_FLAG_STORD 0x2000 53 #define IDXD_OP_FLAG_DRDBK 0x4000 54 #define IDXD_OP_FLAG_DSTS 0x8000 55 56 /* IAX */ 57 #define IDXD_OP_FLAG_RD_SRC2_AECS 0x010000 58 #define IDXD_OP_FLAG_RD_SRC2_2ND 0x020000 59 #define IDXD_OP_FLAG_WR_SRC2_AECS_COMP 0x040000 60 #define IDXD_OP_FLAG_WR_SRC2_AECS_OVFL 0x080000 61 #define IDXD_OP_FLAG_SRC2_STS 0x100000 62 #define IDXD_OP_FLAG_CRC_RFC3720 0x200000 63 64 /* Opcode */ 65 enum dsa_opcode { 66 DSA_OPCODE_NOOP = 0, 67 DSA_OPCODE_BATCH, 68 DSA_OPCODE_DRAIN, 69 DSA_OPCODE_MEMMOVE, 70 DSA_OPCODE_MEMFILL, 71 DSA_OPCODE_COMPARE, 72 DSA_OPCODE_COMPVAL, 73 DSA_OPCODE_CR_DELTA, 74 DSA_OPCODE_AP_DELTA, 75 DSA_OPCODE_DUALCAST, 76 DSA_OPCODE_TRANSL_FETCH, 77 DSA_OPCODE_CRCGEN = 0x10, 78 DSA_OPCODE_COPY_CRC, 79 DSA_OPCODE_DIF_CHECK, 80 DSA_OPCODE_DIF_INS, 81 DSA_OPCODE_DIF_STRP, 82 DSA_OPCODE_DIF_UPDT, 83 DSA_OPCODE_DIX_GEN = 0x17, 84 DSA_OPCODE_CFLUSH = 0x20, 85 }; 86 87 enum iax_opcode { 88 IAX_OPCODE_NOOP = 0, 89 IAX_OPCODE_DRAIN = 2, 90 IAX_OPCODE_MEMMOVE, 91 IAX_OPCODE_DECOMPRESS = 0x42, 92 IAX_OPCODE_COMPRESS, 93 IAX_OPCODE_CRC64, 94 IAX_OPCODE_ZERO_DECOMP_32 = 0x48, 95 IAX_OPCODE_ZERO_DECOMP_16, 96 IAX_OPCODE_ZERO_COMP_32 = 0x4c, 97 IAX_OPCODE_ZERO_COMP_16, 98 IAX_OPCODE_SCAN = 0x50, 99 IAX_OPCODE_SET_MEMBER, 100 IAX_OPCODE_EXTRACT, 101 IAX_OPCODE_SELECT, 102 IAX_OPCODE_RLE_BURST, 103 IAX_OPCODE_FIND_UNIQUE, 104 IAX_OPCODE_EXPAND, 105 }; 106 107 /* Completion record status */ 108 enum dsa_completion_status { 109 DSA_COMP_NONE = 0, 110 DSA_COMP_SUCCESS, 111 DSA_COMP_SUCCESS_PRED, 112 DSA_COMP_PAGE_FAULT_NOBOF, 113 DSA_COMP_PAGE_FAULT_IR, 114 DSA_COMP_BATCH_FAIL, 115 DSA_COMP_BATCH_PAGE_FAULT, 116 DSA_COMP_DR_OFFSET_NOINC, 117 DSA_COMP_DR_OFFSET_ERANGE, 118 DSA_COMP_DIF_ERR, 119 DSA_COMP_BAD_OPCODE = 0x10, 120 DSA_COMP_INVALID_FLAGS, 121 DSA_COMP_NOZERO_RESERVE, 122 DSA_COMP_XFER_ERANGE, 123 DSA_COMP_DESC_CNT_ERANGE, 124 DSA_COMP_DR_ERANGE, 125 DSA_COMP_OVERLAP_BUFFERS, 126 DSA_COMP_DCAST_ERR, 127 DSA_COMP_DESCLIST_ALIGN, 128 DSA_COMP_INT_HANDLE_INVAL, 129 DSA_COMP_CRA_XLAT, 130 DSA_COMP_CRA_ALIGN, 131 DSA_COMP_ADDR_ALIGN, 132 DSA_COMP_PRIV_BAD, 133 DSA_COMP_TRAFFIC_CLASS_CONF, 134 DSA_COMP_PFAULT_RDBA, 135 DSA_COMP_HW_ERR1, 136 DSA_COMP_HW_ERR_DRB, 137 DSA_COMP_TRANSLATION_FAIL, 138 }; 139 140 enum iax_completion_status { 141 IAX_COMP_NONE = 0, 142 IAX_COMP_SUCCESS, 143 IAX_COMP_PAGE_FAULT_IR = 0x04, 144 IAX_COMP_ANALYTICS_ERROR = 0x0a, 145 IAX_COMP_OUTBUF_OVERFLOW, 146 IAX_COMP_BAD_OPCODE = 0x10, 147 IAX_COMP_INVALID_FLAGS, 148 IAX_COMP_NOZERO_RESERVE, 149 IAX_COMP_INVALID_SIZE, 150 IAX_COMP_OVERLAP_BUFFERS = 0x16, 151 IAX_COMP_INT_HANDLE_INVAL = 0x19, 152 IAX_COMP_CRA_XLAT, 153 IAX_COMP_CRA_ALIGN, 154 IAX_COMP_ADDR_ALIGN, 155 IAX_COMP_PRIV_BAD, 156 IAX_COMP_TRAFFIC_CLASS_CONF, 157 IAX_COMP_PFAULT_RDBA, 158 IAX_COMP_HW_ERR1, 159 IAX_COMP_HW_ERR_DRB, 160 IAX_COMP_TRANSLATION_FAIL, 161 IAX_COMP_PRS_TIMEOUT, 162 IAX_COMP_WATCHDOG, 163 IAX_COMP_INVALID_COMP_FLAG = 0x30, 164 IAX_COMP_INVALID_FILTER_FLAG, 165 IAX_COMP_INVALID_INPUT_SIZE, 166 IAX_COMP_INVALID_NUM_ELEMS, 167 IAX_COMP_INVALID_SRC1_WIDTH, 168 IAX_COMP_INVALID_INVERT_OUT, 169 }; 170 171 #define DSA_COMP_STATUS_MASK 0x7f 172 #define DSA_COMP_STATUS_WRITE 0x80 173 174 struct dsa_hw_desc { 175 uint32_t pasid:20; 176 uint32_t rsvd:11; 177 uint32_t priv:1; 178 uint32_t flags:24; 179 uint32_t opcode:8; 180 uint64_t completion_addr; 181 union { 182 uint64_t src_addr; 183 uint64_t rdback_addr; 184 uint64_t pattern; 185 uint64_t desc_list_addr; 186 uint64_t pattern_lower; 187 uint64_t transl_fetch_addr; 188 }; 189 union { 190 uint64_t dst_addr; 191 uint64_t rdback_addr2; 192 uint64_t src2_addr; 193 uint64_t comp_pattern; 194 }; 195 union { 196 uint32_t xfer_size; 197 uint32_t desc_count; 198 uint32_t region_size; 199 }; 200 uint16_t int_handle; 201 uint16_t rsvd1; 202 union { 203 uint8_t expected_res; 204 /* create delta record */ 205 struct { 206 uint64_t delta_addr; 207 uint32_t max_delta_size; 208 uint32_t delt_rsvd; 209 uint8_t expected_res_mask; 210 }; 211 uint32_t delta_rec_size; 212 uint64_t dest2; 213 /* CRC */ 214 struct { 215 uint32_t crc_seed; 216 uint32_t crc_rsvd; 217 uint64_t seed_addr; 218 }; 219 /* DIF check or strip */ 220 struct { 221 uint8_t src_dif_flags; 222 uint8_t dif_chk_res; 223 uint8_t dif_chk_flags; 224 uint8_t dif_chk_res2[5]; 225 uint32_t chk_ref_tag_seed; 226 uint16_t chk_app_tag_mask; 227 uint16_t chk_app_tag_seed; 228 }; 229 /* DIF insert */ 230 struct { 231 uint8_t dif_ins_res; 232 uint8_t dest_dif_flag; 233 uint8_t dif_ins_flags; 234 uint8_t dif_ins_res2[13]; 235 uint32_t ins_ref_tag_seed; 236 uint16_t ins_app_tag_mask; 237 uint16_t ins_app_tag_seed; 238 }; 239 /* DIF update */ 240 struct { 241 uint8_t src_upd_flags; 242 uint8_t upd_dest_flags; 243 uint8_t dif_upd_flags; 244 uint8_t dif_upd_res[5]; 245 uint32_t src_ref_tag_seed; 246 uint16_t src_app_tag_mask; 247 uint16_t src_app_tag_seed; 248 uint32_t dest_ref_tag_seed; 249 uint16_t dest_app_tag_mask; 250 uint16_t dest_app_tag_seed; 251 }; 252 253 /* Fill */ 254 uint64_t pattern_upper; 255 256 /* Translation fetch */ 257 struct { 258 uint64_t transl_fetch_res; 259 uint32_t region_stride; 260 }; 261 262 /* DIX generate */ 263 struct { 264 uint8_t dix_gen_res; 265 uint8_t dest_dif_flags; 266 uint8_t dif_flags; 267 uint8_t dix_gen_res2[13]; 268 uint32_t ref_tag_seed; 269 uint16_t app_tag_mask; 270 uint16_t app_tag_seed; 271 }; 272 273 uint8_t op_specific[24]; 274 }; 275 } __attribute__((packed)); 276 277 struct iax_hw_desc { 278 uint32_t pasid:20; 279 uint32_t rsvd:11; 280 uint32_t priv:1; 281 uint32_t flags:24; 282 uint32_t opcode:8; 283 uint64_t completion_addr; 284 uint64_t src1_addr; 285 uint64_t dst_addr; 286 uint32_t src1_size; 287 uint16_t int_handle; 288 union { 289 uint16_t compr_flags; 290 uint16_t decompr_flags; 291 }; 292 uint64_t src2_addr; 293 uint32_t max_dst_size; 294 uint32_t src2_size; 295 uint32_t filter_flags; 296 uint32_t num_inputs; 297 } __attribute__((packed)); 298 299 struct dsa_raw_desc { 300 uint64_t field[8]; 301 } __attribute__((packed)); 302 303 /* 304 * The status field will be modified by hardware, therefore it should be 305 * volatile and prevent the compiler from optimize the read. 306 */ 307 struct dsa_completion_record { 308 volatile uint8_t status; 309 union { 310 uint8_t result; 311 uint8_t dif_status; 312 }; 313 uint16_t rsvd; 314 uint32_t bytes_completed; 315 uint64_t fault_addr; 316 union { 317 /* common record */ 318 struct { 319 uint32_t invalid_flags:24; 320 uint32_t rsvd2:8; 321 }; 322 323 uint32_t delta_rec_size; 324 uint64_t crc_val; 325 326 /* DIF check & strip */ 327 struct { 328 uint32_t dif_chk_ref_tag; 329 uint16_t dif_chk_app_tag_mask; 330 uint16_t dif_chk_app_tag; 331 }; 332 333 /* DIF insert */ 334 struct { 335 uint64_t dif_ins_res; 336 uint32_t dif_ins_ref_tag; 337 uint16_t dif_ins_app_tag_mask; 338 uint16_t dif_ins_app_tag; 339 }; 340 341 /* DIF update */ 342 struct { 343 uint32_t dif_upd_src_ref_tag; 344 uint16_t dif_upd_src_app_tag_mask; 345 uint16_t dif_upd_src_app_tag; 346 uint32_t dif_upd_dest_ref_tag; 347 uint16_t dif_upd_dest_app_tag_mask; 348 uint16_t dif_upd_dest_app_tag; 349 }; 350 351 /* DIX generate */ 352 struct { 353 uint64_t dix_gen_res; 354 uint32_t dix_ref_tag; 355 uint16_t dix_app_tag_mask; 356 uint16_t dix_app_tag; 357 }; 358 359 uint8_t op_specific[16]; 360 }; 361 } __attribute__((packed)); 362 363 struct dsa_raw_completion_record { 364 uint64_t field[4]; 365 } __attribute__((packed)); 366 367 struct iax_completion_record { 368 volatile uint8_t status; 369 uint8_t error_code; 370 uint16_t rsvd; 371 uint32_t bytes_completed; 372 uint64_t fault_addr; 373 uint32_t invalid_flags; 374 uint32_t rsvd2; 375 uint32_t output_size; 376 uint8_t output_bits; 377 uint8_t rsvd3; 378 uint16_t xor_csum; 379 uint32_t crc; 380 uint32_t min; 381 uint32_t max; 382 uint32_t sum; 383 uint64_t rsvd4[2]; 384 } __attribute__((packed)); 385 386 struct iax_raw_completion_record { 387 uint64_t field[8]; 388 } __attribute__((packed)); 389 390 #endif 391