1 /* SPDX-License-Identifier: LGPL-2.1 WITH Linux-syscall-note */ 2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3 #ifndef _USR_IDXD_H_ 4 #define _USR_IDXD_H_ 5 6 #ifdef __KERNEL__ 7 #include <linux/types.h> 8 #else 9 #include <stdint.h> 10 #endif 11 12 /* Driver command error status */ 13 enum idxd_scmd_stat { 14 IDXD_SCMD_DEV_ENABLED = 0x80000010, 15 IDXD_SCMD_DEV_NOT_ENABLED = 0x80000020, 16 IDXD_SCMD_WQ_ENABLED = 0x80000021, 17 IDXD_SCMD_DEV_DMA_ERR = 0x80020000, 18 IDXD_SCMD_WQ_NO_GRP = 0x80030000, 19 IDXD_SCMD_WQ_NO_NAME = 0x80040000, 20 IDXD_SCMD_WQ_NO_SVM = 0x80050000, 21 IDXD_SCMD_WQ_NO_THRESH = 0x80060000, 22 IDXD_SCMD_WQ_PORTAL_ERR = 0x80070000, 23 IDXD_SCMD_WQ_RES_ALLOC_ERR = 0x80080000, 24 IDXD_SCMD_PERCPU_ERR = 0x80090000, 25 IDXD_SCMD_DMA_CHAN_ERR = 0x800a0000, 26 IDXD_SCMD_CDEV_ERR = 0x800b0000, 27 IDXD_SCMD_WQ_NO_SWQ_SUPPORT = 0x800c0000, 28 IDXD_SCMD_WQ_NONE_CONFIGURED = 0x800d0000, 29 IDXD_SCMD_WQ_NO_SIZE = 0x800e0000, 30 IDXD_SCMD_WQ_NO_PRIV = 0x800f0000, 31 IDXD_SCMD_WQ_IRQ_ERR = 0x80100000, 32 IDXD_SCMD_WQ_USER_NO_IOMMU = 0x80110000, 33 }; 34 35 #define IDXD_SCMD_SOFTERR_MASK 0x80000000 36 #define IDXD_SCMD_SOFTERR_SHIFT 16 37 38 /* Descriptor flags */ 39 #define IDXD_OP_FLAG_FENCE 0x0001 40 #define IDXD_OP_FLAG_BOF 0x0002 41 #define IDXD_OP_FLAG_CRAV 0x0004 42 #define IDXD_OP_FLAG_RCR 0x0008 43 #define IDXD_OP_FLAG_RCI 0x0010 44 #define IDXD_OP_FLAG_CRSTS 0x0020 45 #define IDXD_OP_FLAG_CR 0x0080 46 #define IDXD_OP_FLAG_CC 0x0100 47 #define IDXD_OP_FLAG_ADDR1_TCS 0x0200 48 #define IDXD_OP_FLAG_ADDR2_TCS 0x0400 49 #define IDXD_OP_FLAG_ADDR3_TCS 0x0800 50 #define IDXD_OP_FLAG_CR_TCS 0x1000 51 #define IDXD_OP_FLAG_STORD 0x2000 52 #define IDXD_OP_FLAG_DRDBK 0x4000 53 #define IDXD_OP_FLAG_DSTS 0x8000 54 55 /* IAX */ 56 #define IDXD_OP_FLAG_RD_SRC2_AECS 0x010000 57 #define IDXD_OP_FLAG_RD_SRC2_2ND 0x020000 58 #define IDXD_OP_FLAG_WR_SRC2_AECS_COMP 0x040000 59 #define IDXD_OP_FLAG_WR_SRC2_AECS_OVFL 0x080000 60 #define IDXD_OP_FLAG_SRC2_STS 0x100000 61 #define IDXD_OP_FLAG_CRC_RFC3720 0x200000 62 63 /* Opcode */ 64 enum dsa_opcode { 65 DSA_OPCODE_NOOP = 0, 66 DSA_OPCODE_BATCH, 67 DSA_OPCODE_DRAIN, 68 DSA_OPCODE_MEMMOVE, 69 DSA_OPCODE_MEMFILL, 70 DSA_OPCODE_COMPARE, 71 DSA_OPCODE_COMPVAL, 72 DSA_OPCODE_CR_DELTA, 73 DSA_OPCODE_AP_DELTA, 74 DSA_OPCODE_DUALCAST, 75 DSA_OPCODE_CRCGEN = 0x10, 76 DSA_OPCODE_COPY_CRC, 77 DSA_OPCODE_DIF_CHECK, 78 DSA_OPCODE_DIF_INS, 79 DSA_OPCODE_DIF_STRP, 80 DSA_OPCODE_DIF_UPDT, 81 DSA_OPCODE_DIX_GEN = 0x17, 82 DSA_OPCODE_CFLUSH = 0x20, 83 }; 84 85 enum iax_opcode { 86 IAX_OPCODE_NOOP = 0, 87 IAX_OPCODE_DRAIN = 2, 88 IAX_OPCODE_MEMMOVE, 89 IAX_OPCODE_DECOMPRESS = 0x42, 90 IAX_OPCODE_COMPRESS, 91 IAX_OPCODE_CRC64, 92 IAX_OPCODE_ZERO_DECOMP_32 = 0x48, 93 IAX_OPCODE_ZERO_DECOMP_16, 94 IAX_OPCODE_ZERO_COMP_32 = 0x4c, 95 IAX_OPCODE_ZERO_COMP_16, 96 IAX_OPCODE_SCAN = 0x50, 97 IAX_OPCODE_SET_MEMBER, 98 IAX_OPCODE_EXTRACT, 99 IAX_OPCODE_SELECT, 100 IAX_OPCODE_RLE_BURST, 101 IAX_OPCODE_FIND_UNIQUE, 102 IAX_OPCODE_EXPAND, 103 }; 104 105 /* Completion record status */ 106 enum dsa_completion_status { 107 DSA_COMP_NONE = 0, 108 DSA_COMP_SUCCESS, 109 DSA_COMP_SUCCESS_PRED, 110 DSA_COMP_PAGE_FAULT_NOBOF, 111 DSA_COMP_PAGE_FAULT_IR, 112 DSA_COMP_BATCH_FAIL, 113 DSA_COMP_BATCH_PAGE_FAULT, 114 DSA_COMP_DR_OFFSET_NOINC, 115 DSA_COMP_DR_OFFSET_ERANGE, 116 DSA_COMP_DIF_ERR, 117 DSA_COMP_BAD_OPCODE = 0x10, 118 DSA_COMP_INVALID_FLAGS, 119 DSA_COMP_NOZERO_RESERVE, 120 DSA_COMP_XFER_ERANGE, 121 DSA_COMP_DESC_CNT_ERANGE, 122 DSA_COMP_DR_ERANGE, 123 DSA_COMP_OVERLAP_BUFFERS, 124 DSA_COMP_DCAST_ERR, 125 DSA_COMP_DESCLIST_ALIGN, 126 DSA_COMP_INT_HANDLE_INVAL, 127 DSA_COMP_CRA_XLAT, 128 DSA_COMP_CRA_ALIGN, 129 DSA_COMP_ADDR_ALIGN, 130 DSA_COMP_PRIV_BAD, 131 DSA_COMP_TRAFFIC_CLASS_CONF, 132 DSA_COMP_PFAULT_RDBA, 133 DSA_COMP_HW_ERR1, 134 DSA_COMP_HW_ERR_DRB, 135 DSA_COMP_TRANSLATION_FAIL, 136 }; 137 138 enum iax_completion_status { 139 IAX_COMP_NONE = 0, 140 IAX_COMP_SUCCESS, 141 IAX_COMP_PAGE_FAULT_IR = 0x04, 142 IAX_COMP_ANALYTICS_ERROR = 0x0a, 143 IAX_COMP_OUTBUF_OVERFLOW, 144 IAX_COMP_BAD_OPCODE = 0x10, 145 IAX_COMP_INVALID_FLAGS, 146 IAX_COMP_NOZERO_RESERVE, 147 IAX_COMP_INVALID_SIZE, 148 IAX_COMP_OVERLAP_BUFFERS = 0x16, 149 IAX_COMP_INT_HANDLE_INVAL = 0x19, 150 IAX_COMP_CRA_XLAT, 151 IAX_COMP_CRA_ALIGN, 152 IAX_COMP_ADDR_ALIGN, 153 IAX_COMP_PRIV_BAD, 154 IAX_COMP_TRAFFIC_CLASS_CONF, 155 IAX_COMP_PFAULT_RDBA, 156 IAX_COMP_HW_ERR1, 157 IAX_COMP_HW_ERR_DRB, 158 IAX_COMP_TRANSLATION_FAIL, 159 IAX_COMP_PRS_TIMEOUT, 160 IAX_COMP_WATCHDOG, 161 IAX_COMP_INVALID_COMP_FLAG = 0x30, 162 IAX_COMP_INVALID_FILTER_FLAG, 163 IAX_COMP_INVALID_INPUT_SIZE, 164 IAX_COMP_INVALID_NUM_ELEMS, 165 IAX_COMP_INVALID_SRC1_WIDTH, 166 IAX_COMP_INVALID_INVERT_OUT, 167 }; 168 169 #define DSA_COMP_STATUS_MASK 0x7f 170 #define DSA_COMP_STATUS_WRITE 0x80 171 172 struct dsa_hw_desc { 173 uint32_t pasid:20; 174 uint32_t rsvd:11; 175 uint32_t priv:1; 176 uint32_t flags:24; 177 uint32_t opcode:8; 178 uint64_t completion_addr; 179 union { 180 uint64_t src_addr; 181 uint64_t rdback_addr; 182 uint64_t pattern; 183 uint64_t desc_list_addr; 184 uint64_t pattern_lower; 185 }; 186 union { 187 uint64_t dst_addr; 188 uint64_t rdback_addr2; 189 uint64_t src2_addr; 190 uint64_t comp_pattern; 191 }; 192 union { 193 uint32_t xfer_size; 194 uint32_t desc_count; 195 }; 196 uint16_t int_handle; 197 uint16_t rsvd1; 198 union { 199 uint8_t expected_res; 200 /* create delta record */ 201 struct { 202 uint64_t delta_addr; 203 uint32_t max_delta_size; 204 uint32_t delt_rsvd; 205 uint8_t expected_res_mask; 206 }; 207 uint32_t delta_rec_size; 208 uint64_t dest2; 209 /* CRC */ 210 struct { 211 uint32_t crc_seed; 212 uint32_t crc_rsvd; 213 uint64_t seed_addr; 214 }; 215 /* DIF check or strip */ 216 struct { 217 uint8_t src_dif_flags; 218 uint8_t dif_chk_res; 219 uint8_t dif_chk_flags; 220 uint8_t dif_chk_res2[5]; 221 uint32_t chk_ref_tag_seed; 222 uint16_t chk_app_tag_mask; 223 uint16_t chk_app_tag_seed; 224 }; 225 /* DIF insert */ 226 struct { 227 uint8_t dif_ins_res; 228 uint8_t dest_dif_flag; 229 uint8_t dif_ins_flags; 230 uint8_t dif_ins_res2[13]; 231 uint32_t ins_ref_tag_seed; 232 uint16_t ins_app_tag_mask; 233 uint16_t ins_app_tag_seed; 234 }; 235 /* DIF update */ 236 struct { 237 uint8_t src_upd_flags; 238 uint8_t upd_dest_flags; 239 uint8_t dif_upd_flags; 240 uint8_t dif_upd_res[5]; 241 uint32_t src_ref_tag_seed; 242 uint16_t src_app_tag_mask; 243 uint16_t src_app_tag_seed; 244 uint32_t dest_ref_tag_seed; 245 uint16_t dest_app_tag_mask; 246 uint16_t dest_app_tag_seed; 247 }; 248 249 /* Fill */ 250 uint64_t pattern_upper; 251 252 /* DIX generate */ 253 struct { 254 uint8_t dix_gen_res; 255 uint8_t dest_dif_flags; 256 uint8_t dif_flags; 257 uint8_t dix_gen_res2[13]; 258 uint32_t ref_tag_seed; 259 uint16_t app_tag_mask; 260 uint16_t app_tag_seed; 261 }; 262 263 uint8_t op_specific[24]; 264 }; 265 } __attribute__((packed)); 266 267 struct iax_hw_desc { 268 uint32_t pasid:20; 269 uint32_t rsvd:11; 270 uint32_t priv:1; 271 uint32_t flags:24; 272 uint32_t opcode:8; 273 uint64_t completion_addr; 274 uint64_t src1_addr; 275 uint64_t dst_addr; 276 uint32_t src1_size; 277 uint16_t int_handle; 278 union { 279 uint16_t compr_flags; 280 uint16_t decompr_flags; 281 }; 282 uint64_t src2_addr; 283 uint32_t max_dst_size; 284 uint32_t src2_size; 285 uint32_t filter_flags; 286 uint32_t num_inputs; 287 } __attribute__((packed)); 288 289 struct dsa_raw_desc { 290 uint64_t field[8]; 291 } __attribute__((packed)); 292 293 /* 294 * The status field will be modified by hardware, therefore it should be 295 * volatile and prevent the compiler from optimize the read. 296 */ 297 struct dsa_completion_record { 298 volatile uint8_t status; 299 union { 300 uint8_t result; 301 uint8_t dif_status; 302 }; 303 uint16_t rsvd; 304 uint32_t bytes_completed; 305 uint64_t fault_addr; 306 union { 307 /* common record */ 308 struct { 309 uint32_t invalid_flags:24; 310 uint32_t rsvd2:8; 311 }; 312 313 uint32_t delta_rec_size; 314 uint64_t crc_val; 315 316 /* DIF check & strip */ 317 struct { 318 uint32_t dif_chk_ref_tag; 319 uint16_t dif_chk_app_tag_mask; 320 uint16_t dif_chk_app_tag; 321 }; 322 323 /* DIF insert */ 324 struct { 325 uint64_t dif_ins_res; 326 uint32_t dif_ins_ref_tag; 327 uint16_t dif_ins_app_tag_mask; 328 uint16_t dif_ins_app_tag; 329 }; 330 331 /* DIF update */ 332 struct { 333 uint32_t dif_upd_src_ref_tag; 334 uint16_t dif_upd_src_app_tag_mask; 335 uint16_t dif_upd_src_app_tag; 336 uint32_t dif_upd_dest_ref_tag; 337 uint16_t dif_upd_dest_app_tag_mask; 338 uint16_t dif_upd_dest_app_tag; 339 }; 340 341 /* DIX generate */ 342 struct { 343 uint64_t dix_gen_res; 344 uint32_t dix_ref_tag; 345 uint16_t dix_app_tag_mask; 346 uint16_t dix_app_tag; 347 }; 348 349 uint8_t op_specific[16]; 350 }; 351 } __attribute__((packed)); 352 353 struct dsa_raw_completion_record { 354 uint64_t field[4]; 355 } __attribute__((packed)); 356 357 struct iax_completion_record { 358 volatile uint8_t status; 359 uint8_t error_code; 360 uint16_t rsvd; 361 uint32_t bytes_completed; 362 uint64_t fault_addr; 363 uint32_t invalid_flags; 364 uint32_t rsvd2; 365 uint32_t output_size; 366 uint8_t output_bits; 367 uint8_t rsvd3; 368 uint16_t xor_csum; 369 uint32_t crc; 370 uint32_t min; 371 uint32_t max; 372 uint32_t sum; 373 uint64_t rsvd4[2]; 374 } __attribute__((packed)); 375 376 struct iax_raw_completion_record { 377 uint64_t field[8]; 378 } __attribute__((packed)); 379 380 #endif 381