1 /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ 2 /* 3 * Copyright (C) 2020-2023 Intel Corporation 4 */ 5 6 #ifndef __UAPI_IVPU_DRM_H__ 7 #define __UAPI_IVPU_DRM_H__ 8 9 #include "drm.h" 10 11 #if defined(__cplusplus) 12 extern "C" { 13 #endif 14 15 #define DRM_IVPU_DRIVER_MAJOR 1 16 #define DRM_IVPU_DRIVER_MINOR 0 17 18 #define DRM_IVPU_GET_PARAM 0x00 19 #define DRM_IVPU_SET_PARAM 0x01 20 #define DRM_IVPU_BO_CREATE 0x02 21 #define DRM_IVPU_BO_INFO 0x03 22 23 #define DRM_IOCTL_IVPU_GET_PARAM \ 24 DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_GET_PARAM, struct drm_ivpu_param) 25 26 #define DRM_IOCTL_IVPU_SET_PARAM \ 27 DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_SET_PARAM, struct drm_ivpu_param) 28 29 #define DRM_IOCTL_IVPU_BO_CREATE \ 30 DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_CREATE, struct drm_ivpu_bo_create) 31 32 #define DRM_IOCTL_IVPU_BO_INFO \ 33 DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_INFO, struct drm_ivpu_bo_info) 34 35 /** 36 * DOC: contexts 37 * 38 * VPU contexts have private virtual address space, job queues and priority. 39 * Each context is identified by an unique ID. Context is created on open(). 40 */ 41 42 #define DRM_IVPU_PARAM_DEVICE_ID 0 43 #define DRM_IVPU_PARAM_DEVICE_REVISION 1 44 #define DRM_IVPU_PARAM_PLATFORM_TYPE 2 45 #define DRM_IVPU_PARAM_CORE_CLOCK_RATE 3 46 #define DRM_IVPU_PARAM_NUM_CONTEXTS 4 47 #define DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS 5 48 #define DRM_IVPU_PARAM_CONTEXT_PRIORITY 6 49 #define DRM_IVPU_PARAM_CONTEXT_ID 7 50 #define DRM_IVPU_PARAM_FW_API_VERSION 8 51 #define DRM_IVPU_PARAM_ENGINE_HEARTBEAT 9 52 #define DRM_IVPU_PARAM_UNIQUE_INFERENCE_ID 10 53 #define DRM_IVPU_PARAM_TILE_CONFIG 11 54 #define DRM_IVPU_PARAM_SKU 12 55 56 #define DRM_IVPU_PLATFORM_TYPE_SILICON 0 57 58 #define DRM_IVPU_CONTEXT_PRIORITY_IDLE 0 59 #define DRM_IVPU_CONTEXT_PRIORITY_NORMAL 1 60 #define DRM_IVPU_CONTEXT_PRIORITY_FOCUS 2 61 #define DRM_IVPU_CONTEXT_PRIORITY_REALTIME 3 62 63 /** 64 * struct drm_ivpu_param - Get/Set VPU parameters 65 */ 66 struct drm_ivpu_param { 67 /** 68 * @param: 69 * 70 * Supported params: 71 * 72 * %DRM_IVPU_PARAM_DEVICE_ID: 73 * PCI Device ID of the VPU device (read-only) 74 * 75 * %DRM_IVPU_PARAM_DEVICE_REVISION: 76 * VPU device revision (read-only) 77 * 78 * %DRM_IVPU_PARAM_PLATFORM_TYPE: 79 * Returns %DRM_IVPU_PLATFORM_TYPE_SILICON on real hardware or device specific 80 * platform type when executing on a simulator or emulator (read-only) 81 * 82 * %DRM_IVPU_PARAM_CORE_CLOCK_RATE: 83 * Current PLL frequency (read-only) 84 * 85 * %DRM_IVPU_PARAM_NUM_CONTEXTS: 86 * Maximum number of simultaneously existing contexts (read-only) 87 * 88 * %DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS: 89 * Lowest VPU virtual address available in the current context (read-only) 90 * 91 * %DRM_IVPU_PARAM_CONTEXT_PRIORITY: 92 * Value of current context scheduling priority (read-write). 93 * See DRM_IVPU_CONTEXT_PRIORITY_* for possible values. 94 * 95 * %DRM_IVPU_PARAM_CONTEXT_ID: 96 * Current context ID, always greater than 0 (read-only) 97 * 98 * %DRM_IVPU_PARAM_FW_API_VERSION: 99 * Firmware API version array (read-only) 100 * 101 * %DRM_IVPU_PARAM_ENGINE_HEARTBEAT: 102 * Heartbeat value from an engine (read-only). 103 * Engine ID (i.e. DRM_IVPU_ENGINE_COMPUTE) is given via index. 104 * 105 * %DRM_IVPU_PARAM_UNIQUE_INFERENCE_ID: 106 * Device-unique inference ID (read-only) 107 * 108 * %DRM_IVPU_PARAM_TILE_CONFIG: 109 * VPU tile configuration (read-only) 110 * 111 * %DRM_IVPU_PARAM_SKU: 112 * VPU SKU ID (read-only) 113 * 114 */ 115 __u32 param; 116 117 /** @index: Index for params that have multiple instances */ 118 __u32 index; 119 120 /** @value: Param value */ 121 __u64 value; 122 }; 123 124 #define DRM_IVPU_BO_HIGH_MEM 0x00000001 125 #define DRM_IVPU_BO_MAPPABLE 0x00000002 126 127 #define DRM_IVPU_BO_CACHED 0x00000000 128 #define DRM_IVPU_BO_UNCACHED 0x00010000 129 #define DRM_IVPU_BO_WC 0x00020000 130 #define DRM_IVPU_BO_CACHE_MASK 0x00030000 131 132 #define DRM_IVPU_BO_FLAGS \ 133 (DRM_IVPU_BO_HIGH_MEM | \ 134 DRM_IVPU_BO_MAPPABLE | \ 135 DRM_IVPU_BO_CACHE_MASK) 136 137 /** 138 * struct drm_ivpu_bo_create - Create BO backed by SHMEM 139 * 140 * Create GEM buffer object allocated in SHMEM memory. 141 */ 142 struct drm_ivpu_bo_create { 143 /** @size: The size in bytes of the allocated memory */ 144 __u64 size; 145 146 /** 147 * @flags: 148 * 149 * Supported flags: 150 * 151 * %DRM_IVPU_BO_HIGH_MEM: 152 * 153 * Allocate VPU address from >4GB range. 154 * Buffer object with vpu address >4GB can be always accessed by the 155 * VPU DMA engine, but some HW generation may not be able to access 156 * this memory from then firmware running on the VPU management processor. 157 * Suitable for input, output and some scratch buffers. 158 * 159 * %DRM_IVPU_BO_MAPPABLE: 160 * 161 * Buffer object can be mapped using mmap(). 162 * 163 * %DRM_IVPU_BO_CACHED: 164 * 165 * Allocated BO will be cached on host side (WB) and snooped on the VPU side. 166 * This is the default caching mode. 167 * 168 * %DRM_IVPU_BO_UNCACHED: 169 * 170 * Allocated BO will not be cached on host side nor snooped on the VPU side. 171 * 172 * %DRM_IVPU_BO_WC: 173 * 174 * Allocated BO will use write combining buffer for writes but reads will be 175 * uncached. 176 */ 177 __u32 flags; 178 179 /** @handle: Returned GEM object handle */ 180 __u32 handle; 181 182 /** @vpu_addr: Returned VPU virtual address */ 183 __u64 vpu_addr; 184 }; 185 186 /** 187 * struct drm_ivpu_bo_info - Query buffer object info 188 */ 189 struct drm_ivpu_bo_info { 190 /** @handle: Handle of the queried BO */ 191 __u32 handle; 192 193 /** @flags: Returned flags used to create the BO */ 194 __u32 flags; 195 196 /** @vpu_addr: Returned VPU virtual address */ 197 __u64 vpu_addr; 198 199 /** 200 * @mmap_offset: 201 * 202 * Returned offset to be used in mmap(). 0 in case the BO is not mappable. 203 */ 204 __u64 mmap_offset; 205 206 /** @size: Returned GEM object size, aligned to PAGE_SIZE */ 207 __u64 size; 208 }; 209 210 #if defined(__cplusplus) 211 } 212 #endif 213 214 #endif /* __UAPI_IVPU_DRM_H__ */ 215