1 /* exynos_drm.h 2 * 3 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 4 * Authors: 5 * Inki Dae <[email protected]> 6 * Joonyoung Shim <[email protected]> 7 * Seung-Woo Kim <[email protected]> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 */ 14 15 #ifndef _UAPI_EXYNOS_DRM_H_ 16 #define _UAPI_EXYNOS_DRM_H_ 17 18 #include <drm/drm.h> 19 20 /** 21 * User-desired buffer creation information structure. 22 * 23 * @size: user-desired memory allocation size. 24 * - this size value would be page-aligned internally. 25 * @flags: user request for setting memory type or cache attributes. 26 * @handle: returned a handle to created gem object. 27 * - this handle will be set by gem module of kernel side. 28 */ 29 struct drm_exynos_gem_create { 30 uint64_t size; 31 unsigned int flags; 32 unsigned int handle; 33 }; 34 35 /** 36 * A structure for mapping buffer. 37 * 38 * @handle: a handle to gem object created. 39 * @pad: just padding to be 64-bit aligned. 40 * @size: memory size to be mapped. 41 * @mapped: having user virtual address mmaped. 42 * - this variable would be filled by exynos gem module 43 * of kernel side with user virtual address which is allocated 44 * by do_mmap(). 45 */ 46 struct drm_exynos_gem_mmap { 47 unsigned int handle; 48 unsigned int pad; 49 uint64_t size; 50 uint64_t mapped; 51 }; 52 53 /** 54 * A structure to gem information. 55 * 56 * @handle: a handle to gem object created. 57 * @flags: flag value including memory type and cache attribute and 58 * this value would be set by driver. 59 * @size: size to memory region allocated by gem and this size would 60 * be set by driver. 61 */ 62 struct drm_exynos_gem_info { 63 unsigned int handle; 64 unsigned int flags; 65 uint64_t size; 66 }; 67 68 /** 69 * A structure for user connection request of virtual display. 70 * 71 * @connection: indicate whether doing connetion or not by user. 72 * @extensions: if this value is 1 then the vidi driver would need additional 73 * 128bytes edid data. 74 * @edid: the edid data pointer from user side. 75 */ 76 struct drm_exynos_vidi_connection { 77 unsigned int connection; 78 unsigned int extensions; 79 uint64_t edid; 80 }; 81 82 /* memory type definitions. */ 83 enum e_drm_exynos_gem_mem_type { 84 /* Physically Continuous memory and used as default. */ 85 EXYNOS_BO_CONTIG = 0 << 0, 86 /* Physically Non-Continuous memory. */ 87 EXYNOS_BO_NONCONTIG = 1 << 0, 88 /* non-cachable mapping and used as default. */ 89 EXYNOS_BO_NONCACHABLE = 0 << 1, 90 /* cachable mapping. */ 91 EXYNOS_BO_CACHABLE = 1 << 1, 92 /* write-combine mapping. */ 93 EXYNOS_BO_WC = 1 << 2, 94 EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE | 95 EXYNOS_BO_WC 96 }; 97 98 struct drm_exynos_g2d_get_ver { 99 __u32 major; 100 __u32 minor; 101 }; 102 103 struct drm_exynos_g2d_cmd { 104 __u32 offset; 105 __u32 data; 106 }; 107 108 enum drm_exynos_g2d_buf_type { 109 G2D_BUF_USERPTR = 1 << 31, 110 }; 111 112 enum drm_exynos_g2d_event_type { 113 G2D_EVENT_NOT, 114 G2D_EVENT_NONSTOP, 115 G2D_EVENT_STOP, /* not yet */ 116 }; 117 118 struct drm_exynos_g2d_userptr { 119 unsigned long userptr; 120 unsigned long size; 121 }; 122 123 struct drm_exynos_g2d_set_cmdlist { 124 __u64 cmd; 125 __u64 cmd_buf; 126 __u32 cmd_nr; 127 __u32 cmd_buf_nr; 128 129 /* for g2d event */ 130 __u64 event_type; 131 __u64 user_data; 132 }; 133 134 struct drm_exynos_g2d_exec { 135 __u64 async; 136 }; 137 138 enum drm_exynos_ops_id { 139 EXYNOS_DRM_OPS_SRC, 140 EXYNOS_DRM_OPS_DST, 141 EXYNOS_DRM_OPS_MAX, 142 }; 143 144 struct drm_exynos_sz { 145 __u32 hsize; 146 __u32 vsize; 147 }; 148 149 struct drm_exynos_pos { 150 __u32 x; 151 __u32 y; 152 __u32 w; 153 __u32 h; 154 }; 155 156 enum drm_exynos_flip { 157 EXYNOS_DRM_FLIP_NONE = (0 << 0), 158 EXYNOS_DRM_FLIP_VERTICAL = (1 << 0), 159 EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1), 160 EXYNOS_DRM_FLIP_BOTH = EXYNOS_DRM_FLIP_VERTICAL | 161 EXYNOS_DRM_FLIP_HORIZONTAL, 162 }; 163 164 enum drm_exynos_degree { 165 EXYNOS_DRM_DEGREE_0, 166 EXYNOS_DRM_DEGREE_90, 167 EXYNOS_DRM_DEGREE_180, 168 EXYNOS_DRM_DEGREE_270, 169 }; 170 171 enum drm_exynos_planer { 172 EXYNOS_DRM_PLANAR_Y, 173 EXYNOS_DRM_PLANAR_CB, 174 EXYNOS_DRM_PLANAR_CR, 175 EXYNOS_DRM_PLANAR_MAX, 176 }; 177 178 /** 179 * A structure for ipp supported property list. 180 * 181 * @version: version of this structure. 182 * @ipp_id: id of ipp driver. 183 * @count: count of ipp driver. 184 * @writeback: flag of writeback supporting. 185 * @flip: flag of flip supporting. 186 * @degree: flag of degree information. 187 * @csc: flag of csc supporting. 188 * @crop: flag of crop supporting. 189 * @scale: flag of scale supporting. 190 * @refresh_min: min hz of refresh. 191 * @refresh_max: max hz of refresh. 192 * @crop_min: crop min resolution. 193 * @crop_max: crop max resolution. 194 * @scale_min: scale min resolution. 195 * @scale_max: scale max resolution. 196 */ 197 struct drm_exynos_ipp_prop_list { 198 __u32 version; 199 __u32 ipp_id; 200 __u32 count; 201 __u32 writeback; 202 __u32 flip; 203 __u32 degree; 204 __u32 csc; 205 __u32 crop; 206 __u32 scale; 207 __u32 refresh_min; 208 __u32 refresh_max; 209 __u32 reserved; 210 struct drm_exynos_sz crop_min; 211 struct drm_exynos_sz crop_max; 212 struct drm_exynos_sz scale_min; 213 struct drm_exynos_sz scale_max; 214 }; 215 216 /** 217 * A structure for ipp config. 218 * 219 * @ops_id: property of operation directions. 220 * @flip: property of mirror, flip. 221 * @degree: property of rotation degree. 222 * @fmt: property of image format. 223 * @sz: property of image size. 224 * @pos: property of image position(src-cropped,dst-scaler). 225 */ 226 struct drm_exynos_ipp_config { 227 enum drm_exynos_ops_id ops_id; 228 enum drm_exynos_flip flip; 229 enum drm_exynos_degree degree; 230 __u32 fmt; 231 struct drm_exynos_sz sz; 232 struct drm_exynos_pos pos; 233 }; 234 235 enum drm_exynos_ipp_cmd { 236 IPP_CMD_NONE, 237 IPP_CMD_M2M, 238 IPP_CMD_WB, 239 IPP_CMD_OUTPUT, 240 IPP_CMD_MAX, 241 }; 242 243 /** 244 * A structure for ipp property. 245 * 246 * @config: source, destination config. 247 * @cmd: definition of command. 248 * @ipp_id: id of ipp driver. 249 * @prop_id: id of property. 250 * @refresh_rate: refresh rate. 251 */ 252 struct drm_exynos_ipp_property { 253 struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX]; 254 enum drm_exynos_ipp_cmd cmd; 255 __u32 ipp_id; 256 __u32 prop_id; 257 __u32 refresh_rate; 258 }; 259 260 enum drm_exynos_ipp_buf_type { 261 IPP_BUF_ENQUEUE, 262 IPP_BUF_DEQUEUE, 263 }; 264 265 /** 266 * A structure for ipp buffer operations. 267 * 268 * @ops_id: operation directions. 269 * @buf_type: definition of buffer. 270 * @prop_id: id of property. 271 * @buf_id: id of buffer. 272 * @handle: Y, Cb, Cr each planar handle. 273 * @user_data: user data. 274 */ 275 struct drm_exynos_ipp_queue_buf { 276 enum drm_exynos_ops_id ops_id; 277 enum drm_exynos_ipp_buf_type buf_type; 278 __u32 prop_id; 279 __u32 buf_id; 280 __u32 handle[EXYNOS_DRM_PLANAR_MAX]; 281 __u32 reserved; 282 __u64 user_data; 283 }; 284 285 enum drm_exynos_ipp_ctrl { 286 IPP_CTRL_PLAY, 287 IPP_CTRL_STOP, 288 IPP_CTRL_PAUSE, 289 IPP_CTRL_RESUME, 290 IPP_CTRL_MAX, 291 }; 292 293 /** 294 * A structure for ipp start/stop operations. 295 * 296 * @prop_id: id of property. 297 * @ctrl: definition of control. 298 */ 299 struct drm_exynos_ipp_cmd_ctrl { 300 __u32 prop_id; 301 enum drm_exynos_ipp_ctrl ctrl; 302 }; 303 304 #define DRM_EXYNOS_GEM_CREATE 0x00 305 #define DRM_EXYNOS_GEM_MMAP 0x02 306 /* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */ 307 #define DRM_EXYNOS_GEM_GET 0x04 308 #define DRM_EXYNOS_VIDI_CONNECTION 0x07 309 310 /* G2D */ 311 #define DRM_EXYNOS_G2D_GET_VER 0x20 312 #define DRM_EXYNOS_G2D_SET_CMDLIST 0x21 313 #define DRM_EXYNOS_G2D_EXEC 0x22 314 315 /* IPP - Image Post Processing */ 316 #define DRM_EXYNOS_IPP_GET_PROPERTY 0x30 317 #define DRM_EXYNOS_IPP_SET_PROPERTY 0x31 318 #define DRM_EXYNOS_IPP_QUEUE_BUF 0x32 319 #define DRM_EXYNOS_IPP_CMD_CTRL 0x33 320 321 #define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \ 322 DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create) 323 324 #define DRM_IOCTL_EXYNOS_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + \ 325 DRM_EXYNOS_GEM_MMAP, struct drm_exynos_gem_mmap) 326 327 #define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + \ 328 DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info) 329 330 #define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + \ 331 DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection) 332 333 #define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \ 334 DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver) 335 #define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \ 336 DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist) 337 #define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \ 338 DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec) 339 340 #define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \ 341 DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list) 342 #define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \ 343 DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property) 344 #define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF DRM_IOWR(DRM_COMMAND_BASE + \ 345 DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf) 346 #define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL DRM_IOWR(DRM_COMMAND_BASE + \ 347 DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl) 348 349 /* EXYNOS specific events */ 350 #define DRM_EXYNOS_G2D_EVENT 0x80000000 351 #define DRM_EXYNOS_IPP_EVENT 0x80000001 352 353 struct drm_exynos_g2d_event { 354 struct drm_event base; 355 __u64 user_data; 356 __u32 tv_sec; 357 __u32 tv_usec; 358 __u32 cmdlist_no; 359 __u32 reserved; 360 }; 361 362 struct drm_exynos_ipp_event { 363 struct drm_event base; 364 __u64 user_data; 365 __u32 tv_sec; 366 __u32 tv_usec; 367 __u32 prop_id; 368 __u32 reserved; 369 __u32 buf_id[EXYNOS_DRM_OPS_MAX]; 370 }; 371 372 #endif /* _UAPI_EXYNOS_DRM_H_ */ 373