1 /* exynos_drm.h 2 * 3 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 4 * Authors: 5 * Inki Dae <[email protected]> 6 * Joonyoung Shim <[email protected]> 7 * Seung-Woo Kim <[email protected]> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 */ 14 15 #ifndef _UAPI_EXYNOS_DRM_H_ 16 #define _UAPI_EXYNOS_DRM_H_ 17 18 #include <drm/drm.h> 19 20 /** 21 * User-desired buffer creation information structure. 22 * 23 * @size: user-desired memory allocation size. 24 * - this size value would be page-aligned internally. 25 * @flags: user request for setting memory type or cache attributes. 26 * @handle: returned a handle to created gem object. 27 * - this handle will be set by gem module of kernel side. 28 */ 29 struct drm_exynos_gem_create { 30 uint64_t size; 31 unsigned int flags; 32 unsigned int handle; 33 }; 34 35 /** 36 * A structure for getting buffer offset. 37 * 38 * @handle: a pointer to gem object created. 39 * @pad: just padding to be 64-bit aligned. 40 * @offset: relatived offset value of the memory region allocated. 41 * - this value should be set by user. 42 */ 43 struct drm_exynos_gem_map_off { 44 unsigned int handle; 45 unsigned int pad; 46 uint64_t offset; 47 }; 48 49 /** 50 * A structure for mapping buffer. 51 * 52 * @handle: a handle to gem object created. 53 * @pad: just padding to be 64-bit aligned. 54 * @size: memory size to be mapped. 55 * @mapped: having user virtual address mmaped. 56 * - this variable would be filled by exynos gem module 57 * of kernel side with user virtual address which is allocated 58 * by do_mmap(). 59 */ 60 struct drm_exynos_gem_mmap { 61 unsigned int handle; 62 unsigned int pad; 63 uint64_t size; 64 uint64_t mapped; 65 }; 66 67 /** 68 * A structure to gem information. 69 * 70 * @handle: a handle to gem object created. 71 * @flags: flag value including memory type and cache attribute and 72 * this value would be set by driver. 73 * @size: size to memory region allocated by gem and this size would 74 * be set by driver. 75 */ 76 struct drm_exynos_gem_info { 77 unsigned int handle; 78 unsigned int flags; 79 uint64_t size; 80 }; 81 82 /** 83 * A structure for user connection request of virtual display. 84 * 85 * @connection: indicate whether doing connetion or not by user. 86 * @extensions: if this value is 1 then the vidi driver would need additional 87 * 128bytes edid data. 88 * @edid: the edid data pointer from user side. 89 */ 90 struct drm_exynos_vidi_connection { 91 unsigned int connection; 92 unsigned int extensions; 93 uint64_t edid; 94 }; 95 96 /* memory type definitions. */ 97 enum e_drm_exynos_gem_mem_type { 98 /* Physically Continuous memory and used as default. */ 99 EXYNOS_BO_CONTIG = 0 << 0, 100 /* Physically Non-Continuous memory. */ 101 EXYNOS_BO_NONCONTIG = 1 << 0, 102 /* non-cachable mapping and used as default. */ 103 EXYNOS_BO_NONCACHABLE = 0 << 1, 104 /* cachable mapping. */ 105 EXYNOS_BO_CACHABLE = 1 << 1, 106 /* write-combine mapping. */ 107 EXYNOS_BO_WC = 1 << 2, 108 EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE | 109 EXYNOS_BO_WC 110 }; 111 112 struct drm_exynos_g2d_get_ver { 113 __u32 major; 114 __u32 minor; 115 }; 116 117 struct drm_exynos_g2d_cmd { 118 __u32 offset; 119 __u32 data; 120 }; 121 122 enum drm_exynos_g2d_buf_type { 123 G2D_BUF_USERPTR = 1 << 31, 124 }; 125 126 enum drm_exynos_g2d_event_type { 127 G2D_EVENT_NOT, 128 G2D_EVENT_NONSTOP, 129 G2D_EVENT_STOP, /* not yet */ 130 }; 131 132 struct drm_exynos_g2d_userptr { 133 unsigned long userptr; 134 unsigned long size; 135 }; 136 137 struct drm_exynos_g2d_set_cmdlist { 138 __u64 cmd; 139 __u64 cmd_buf; 140 __u32 cmd_nr; 141 __u32 cmd_buf_nr; 142 143 /* for g2d event */ 144 __u64 event_type; 145 __u64 user_data; 146 }; 147 148 struct drm_exynos_g2d_exec { 149 __u64 async; 150 }; 151 152 enum drm_exynos_ops_id { 153 EXYNOS_DRM_OPS_SRC, 154 EXYNOS_DRM_OPS_DST, 155 EXYNOS_DRM_OPS_MAX, 156 }; 157 158 struct drm_exynos_sz { 159 __u32 hsize; 160 __u32 vsize; 161 }; 162 163 struct drm_exynos_pos { 164 __u32 x; 165 __u32 y; 166 __u32 w; 167 __u32 h; 168 }; 169 170 enum drm_exynos_flip { 171 EXYNOS_DRM_FLIP_NONE = (0 << 0), 172 EXYNOS_DRM_FLIP_VERTICAL = (1 << 0), 173 EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1), 174 }; 175 176 enum drm_exynos_degree { 177 EXYNOS_DRM_DEGREE_0, 178 EXYNOS_DRM_DEGREE_90, 179 EXYNOS_DRM_DEGREE_180, 180 EXYNOS_DRM_DEGREE_270, 181 }; 182 183 enum drm_exynos_planer { 184 EXYNOS_DRM_PLANAR_Y, 185 EXYNOS_DRM_PLANAR_CB, 186 EXYNOS_DRM_PLANAR_CR, 187 EXYNOS_DRM_PLANAR_MAX, 188 }; 189 190 /** 191 * A structure for ipp supported property list. 192 * 193 * @version: version of this structure. 194 * @ipp_id: id of ipp driver. 195 * @count: count of ipp driver. 196 * @writeback: flag of writeback supporting. 197 * @flip: flag of flip supporting. 198 * @degree: flag of degree information. 199 * @csc: flag of csc supporting. 200 * @crop: flag of crop supporting. 201 * @scale: flag of scale supporting. 202 * @refresh_min: min hz of refresh. 203 * @refresh_max: max hz of refresh. 204 * @crop_min: crop min resolution. 205 * @crop_max: crop max resolution. 206 * @scale_min: scale min resolution. 207 * @scale_max: scale max resolution. 208 */ 209 struct drm_exynos_ipp_prop_list { 210 __u32 version; 211 __u32 ipp_id; 212 __u32 count; 213 __u32 writeback; 214 __u32 flip; 215 __u32 degree; 216 __u32 csc; 217 __u32 crop; 218 __u32 scale; 219 __u32 refresh_min; 220 __u32 refresh_max; 221 __u32 reserved; 222 struct drm_exynos_sz crop_min; 223 struct drm_exynos_sz crop_max; 224 struct drm_exynos_sz scale_min; 225 struct drm_exynos_sz scale_max; 226 }; 227 228 /** 229 * A structure for ipp config. 230 * 231 * @ops_id: property of operation directions. 232 * @flip: property of mirror, flip. 233 * @degree: property of rotation degree. 234 * @fmt: property of image format. 235 * @sz: property of image size. 236 * @pos: property of image position(src-cropped,dst-scaler). 237 */ 238 struct drm_exynos_ipp_config { 239 enum drm_exynos_ops_id ops_id; 240 enum drm_exynos_flip flip; 241 enum drm_exynos_degree degree; 242 __u32 fmt; 243 struct drm_exynos_sz sz; 244 struct drm_exynos_pos pos; 245 }; 246 247 enum drm_exynos_ipp_cmd { 248 IPP_CMD_NONE, 249 IPP_CMD_M2M, 250 IPP_CMD_WB, 251 IPP_CMD_OUTPUT, 252 IPP_CMD_MAX, 253 }; 254 255 /** 256 * A structure for ipp property. 257 * 258 * @config: source, destination config. 259 * @cmd: definition of command. 260 * @ipp_id: id of ipp driver. 261 * @prop_id: id of property. 262 * @refresh_rate: refresh rate. 263 */ 264 struct drm_exynos_ipp_property { 265 struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX]; 266 enum drm_exynos_ipp_cmd cmd; 267 __u32 ipp_id; 268 __u32 prop_id; 269 __u32 refresh_rate; 270 }; 271 272 enum drm_exynos_ipp_buf_type { 273 IPP_BUF_ENQUEUE, 274 IPP_BUF_DEQUEUE, 275 }; 276 277 /** 278 * A structure for ipp buffer operations. 279 * 280 * @ops_id: operation directions. 281 * @buf_type: definition of buffer. 282 * @prop_id: id of property. 283 * @buf_id: id of buffer. 284 * @handle: Y, Cb, Cr each planar handle. 285 * @user_data: user data. 286 */ 287 struct drm_exynos_ipp_queue_buf { 288 enum drm_exynos_ops_id ops_id; 289 enum drm_exynos_ipp_buf_type buf_type; 290 __u32 prop_id; 291 __u32 buf_id; 292 __u32 handle[EXYNOS_DRM_PLANAR_MAX]; 293 __u32 reserved; 294 __u64 user_data; 295 }; 296 297 enum drm_exynos_ipp_ctrl { 298 IPP_CTRL_PLAY, 299 IPP_CTRL_STOP, 300 IPP_CTRL_PAUSE, 301 IPP_CTRL_RESUME, 302 IPP_CTRL_MAX, 303 }; 304 305 /** 306 * A structure for ipp start/stop operations. 307 * 308 * @prop_id: id of property. 309 * @ctrl: definition of control. 310 */ 311 struct drm_exynos_ipp_cmd_ctrl { 312 __u32 prop_id; 313 enum drm_exynos_ipp_ctrl ctrl; 314 }; 315 316 #define DRM_EXYNOS_GEM_CREATE 0x00 317 #define DRM_EXYNOS_GEM_MAP_OFFSET 0x01 318 #define DRM_EXYNOS_GEM_MMAP 0x02 319 /* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */ 320 #define DRM_EXYNOS_GEM_GET 0x04 321 #define DRM_EXYNOS_VIDI_CONNECTION 0x07 322 323 /* G2D */ 324 #define DRM_EXYNOS_G2D_GET_VER 0x20 325 #define DRM_EXYNOS_G2D_SET_CMDLIST 0x21 326 #define DRM_EXYNOS_G2D_EXEC 0x22 327 328 /* IPP - Image Post Processing */ 329 #define DRM_EXYNOS_IPP_GET_PROPERTY 0x30 330 #define DRM_EXYNOS_IPP_SET_PROPERTY 0x31 331 #define DRM_EXYNOS_IPP_QUEUE_BUF 0x32 332 #define DRM_EXYNOS_IPP_CMD_CTRL 0x33 333 334 #define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \ 335 DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create) 336 337 #define DRM_IOCTL_EXYNOS_GEM_MAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + \ 338 DRM_EXYNOS_GEM_MAP_OFFSET, struct drm_exynos_gem_map_off) 339 340 #define DRM_IOCTL_EXYNOS_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + \ 341 DRM_EXYNOS_GEM_MMAP, struct drm_exynos_gem_mmap) 342 343 #define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + \ 344 DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info) 345 346 #define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + \ 347 DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection) 348 349 #define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \ 350 DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver) 351 #define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \ 352 DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist) 353 #define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \ 354 DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec) 355 356 #define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \ 357 DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list) 358 #define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \ 359 DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property) 360 #define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF DRM_IOWR(DRM_COMMAND_BASE + \ 361 DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf) 362 #define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL DRM_IOWR(DRM_COMMAND_BASE + \ 363 DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl) 364 365 /* EXYNOS specific events */ 366 #define DRM_EXYNOS_G2D_EVENT 0x80000000 367 #define DRM_EXYNOS_IPP_EVENT 0x80000001 368 369 struct drm_exynos_g2d_event { 370 struct drm_event base; 371 __u64 user_data; 372 __u32 tv_sec; 373 __u32 tv_usec; 374 __u32 cmdlist_no; 375 __u32 reserved; 376 }; 377 378 struct drm_exynos_ipp_event { 379 struct drm_event base; 380 __u64 user_data; 381 __u32 tv_sec; 382 __u32 tv_usec; 383 __u32 prop_id; 384 __u32 reserved; 385 __u32 buf_id[EXYNOS_DRM_OPS_MAX]; 386 }; 387 388 #endif /* _UAPI_EXYNOS_DRM_H_ */ 389