1*46fe7771SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 27e10cf74SJon Hunter /* 37e10cf74SJon Hunter * Functions and macros to control the flowcontroller 47e10cf74SJon Hunter * 57e10cf74SJon Hunter * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved. 67e10cf74SJon Hunter */ 77e10cf74SJon Hunter 87e10cf74SJon Hunter #ifndef __SOC_TEGRA_FLOWCTRL_H__ 97e10cf74SJon Hunter #define __SOC_TEGRA_FLOWCTRL_H__ 107e10cf74SJon Hunter 117e10cf74SJon Hunter #define FLOW_CTRL_HALT_CPU0_EVENTS 0x0 127e10cf74SJon Hunter #define FLOW_CTRL_WAITEVENT (2 << 29) 137e10cf74SJon Hunter #define FLOW_CTRL_WAIT_FOR_INTERRUPT (4 << 29) 147e10cf74SJon Hunter #define FLOW_CTRL_JTAG_RESUME (1 << 28) 157e10cf74SJon Hunter #define FLOW_CTRL_SCLK_RESUME (1 << 27) 167e10cf74SJon Hunter #define FLOW_CTRL_HALT_CPU_IRQ (1 << 10) 177e10cf74SJon Hunter #define FLOW_CTRL_HALT_CPU_FIQ (1 << 8) 187e10cf74SJon Hunter #define FLOW_CTRL_HALT_LIC_IRQ (1 << 11) 197e10cf74SJon Hunter #define FLOW_CTRL_HALT_LIC_FIQ (1 << 10) 207e10cf74SJon Hunter #define FLOW_CTRL_HALT_GIC_IRQ (1 << 9) 217e10cf74SJon Hunter #define FLOW_CTRL_HALT_GIC_FIQ (1 << 8) 227e10cf74SJon Hunter #define FLOW_CTRL_CPU0_CSR 0x8 237e10cf74SJon Hunter #define FLOW_CTRL_CSR_INTR_FLAG (1 << 15) 247e10cf74SJon Hunter #define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14) 257e10cf74SJon Hunter #define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL (1 << 13) 267e10cf74SJon Hunter #define FLOW_CTRL_CSR_ENABLE_EXT_NCPU (1 << 12) 277e10cf74SJon Hunter #define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \ 287e10cf74SJon Hunter FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \ 297e10cf74SJon Hunter FLOW_CTRL_CSR_ENABLE_EXT_CRAIL) 307e10cf74SJon Hunter #define FLOW_CTRL_CSR_ENABLE (1 << 0) 317e10cf74SJon Hunter #define FLOW_CTRL_HALT_CPU1_EVENTS 0x14 327e10cf74SJon Hunter #define FLOW_CTRL_CPU1_CSR 0x18 337e10cf74SJon Hunter 347e10cf74SJon Hunter #define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 (1 << 4) 357e10cf74SJon Hunter #define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP (3 << 4) 367e10cf74SJon Hunter #define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP 0 377e10cf74SJon Hunter 387e10cf74SJon Hunter #define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 (1 << 8) 397e10cf74SJon Hunter #define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP (0xF << 4) 407e10cf74SJon Hunter #define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP (0xF << 8) 417e10cf74SJon Hunter 427e10cf74SJon Hunter #ifndef __ASSEMBLY__ 437e10cf74SJon Hunter #ifdef CONFIG_SOC_TEGRA_FLOWCTRL 447e10cf74SJon Hunter u32 flowctrl_read_cpu_csr(unsigned int cpuid); 457e10cf74SJon Hunter void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value); 467e10cf74SJon Hunter void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value); 477e10cf74SJon Hunter 487e10cf74SJon Hunter void flowctrl_cpu_suspend_enter(unsigned int cpuid); 497e10cf74SJon Hunter void flowctrl_cpu_suspend_exit(unsigned int cpuid); 507e10cf74SJon Hunter #else flowctrl_read_cpu_csr(unsigned int cpuid)517e10cf74SJon Hunterstatic inline u32 flowctrl_read_cpu_csr(unsigned int cpuid) 527e10cf74SJon Hunter { 537e10cf74SJon Hunter return 0; 547e10cf74SJon Hunter } 557e10cf74SJon Hunter flowctrl_write_cpu_csr(unsigned int cpuid,u32 value)567e10cf74SJon Hunterstatic inline void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value) 577e10cf74SJon Hunter { 587e10cf74SJon Hunter } 597e10cf74SJon Hunter flowctrl_write_cpu_halt(unsigned int cpuid,u32 value)607e10cf74SJon Hunterstatic inline void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value) {} 617e10cf74SJon Hunter flowctrl_cpu_suspend_enter(unsigned int cpuid)627e10cf74SJon Hunterstatic inline void flowctrl_cpu_suspend_enter(unsigned int cpuid) 637e10cf74SJon Hunter { 647e10cf74SJon Hunter } 657e10cf74SJon Hunter flowctrl_cpu_suspend_exit(unsigned int cpuid)667e10cf74SJon Hunterstatic inline void flowctrl_cpu_suspend_exit(unsigned int cpuid) 677e10cf74SJon Hunter { 687e10cf74SJon Hunter } 697e10cf74SJon Hunter #endif /* CONFIG_SOC_TEGRA_FLOWCTRL */ 707e10cf74SJon Hunter #endif /* __ASSEMBLY */ 717e10cf74SJon Hunter #endif /* __SOC_TEGRA_FLOWCTRL_H__ */ 72