1 /* 2 * SyncLink Multiprotocol Serial Adapter Driver 3 * 4 * $Id: synclink.h,v 3.14 2006/07/17 20:15:43 paulkf Exp $ 5 * 6 * Copyright (C) 1998-2000 by Microgate Corporation 7 * 8 * Redistribution of this file is permitted under 9 * the terms of the GNU Public License (GPL) 10 */ 11 12 #ifndef _SYNCLINK_H_ 13 #define _SYNCLINK_H_ 14 #define SYNCLINK_H_VERSION 3.6 15 16 #define BOOLEAN int 17 #define TRUE 1 18 #define FALSE 0 19 20 #define BIT0 0x0001 21 #define BIT1 0x0002 22 #define BIT2 0x0004 23 #define BIT3 0x0008 24 #define BIT4 0x0010 25 #define BIT5 0x0020 26 #define BIT6 0x0040 27 #define BIT7 0x0080 28 #define BIT8 0x0100 29 #define BIT9 0x0200 30 #define BIT10 0x0400 31 #define BIT11 0x0800 32 #define BIT12 0x1000 33 #define BIT13 0x2000 34 #define BIT14 0x4000 35 #define BIT15 0x8000 36 #define BIT16 0x00010000 37 #define BIT17 0x00020000 38 #define BIT18 0x00040000 39 #define BIT19 0x00080000 40 #define BIT20 0x00100000 41 #define BIT21 0x00200000 42 #define BIT22 0x00400000 43 #define BIT23 0x00800000 44 #define BIT24 0x01000000 45 #define BIT25 0x02000000 46 #define BIT26 0x04000000 47 #define BIT27 0x08000000 48 #define BIT28 0x10000000 49 #define BIT29 0x20000000 50 #define BIT30 0x40000000 51 #define BIT31 0x80000000 52 53 54 #define HDLC_MAX_FRAME_SIZE 65535 55 #define MAX_ASYNC_TRANSMIT 4096 56 #define MAX_ASYNC_BUFFER_SIZE 4096 57 58 #define ASYNC_PARITY_NONE 0 59 #define ASYNC_PARITY_EVEN 1 60 #define ASYNC_PARITY_ODD 2 61 #define ASYNC_PARITY_SPACE 3 62 63 #define HDLC_FLAG_UNDERRUN_ABORT7 0x0000 64 #define HDLC_FLAG_UNDERRUN_ABORT15 0x0001 65 #define HDLC_FLAG_UNDERRUN_FLAG 0x0002 66 #define HDLC_FLAG_UNDERRUN_CRC 0x0004 67 #define HDLC_FLAG_SHARE_ZERO 0x0010 68 #define HDLC_FLAG_AUTO_CTS 0x0020 69 #define HDLC_FLAG_AUTO_DCD 0x0040 70 #define HDLC_FLAG_AUTO_RTS 0x0080 71 #define HDLC_FLAG_RXC_DPLL 0x0100 72 #define HDLC_FLAG_RXC_BRG 0x0200 73 #define HDLC_FLAG_RXC_TXCPIN 0x8000 74 #define HDLC_FLAG_RXC_RXCPIN 0x0000 75 #define HDLC_FLAG_TXC_DPLL 0x0400 76 #define HDLC_FLAG_TXC_BRG 0x0800 77 #define HDLC_FLAG_TXC_TXCPIN 0x0000 78 #define HDLC_FLAG_TXC_RXCPIN 0x0008 79 #define HDLC_FLAG_DPLL_DIV8 0x1000 80 #define HDLC_FLAG_DPLL_DIV16 0x2000 81 #define HDLC_FLAG_DPLL_DIV32 0x0000 82 #define HDLC_FLAG_HDLC_LOOPMODE 0x4000 83 84 #define HDLC_CRC_NONE 0 85 #define HDLC_CRC_16_CCITT 1 86 #define HDLC_CRC_32_CCITT 2 87 #define HDLC_CRC_MASK 0x00ff 88 #define HDLC_CRC_RETURN_EX 0x8000 89 90 #define RX_OK 0 91 #define RX_CRC_ERROR 1 92 93 #define HDLC_TXIDLE_FLAGS 0 94 #define HDLC_TXIDLE_ALT_ZEROS_ONES 1 95 #define HDLC_TXIDLE_ZEROS 2 96 #define HDLC_TXIDLE_ONES 3 97 #define HDLC_TXIDLE_ALT_MARK_SPACE 4 98 #define HDLC_TXIDLE_SPACE 5 99 #define HDLC_TXIDLE_MARK 6 100 #define HDLC_TXIDLE_CUSTOM_8 0x10000000 101 #define HDLC_TXIDLE_CUSTOM_16 0x20000000 102 103 #define HDLC_ENCODING_NRZ 0 104 #define HDLC_ENCODING_NRZB 1 105 #define HDLC_ENCODING_NRZI_MARK 2 106 #define HDLC_ENCODING_NRZI_SPACE 3 107 #define HDLC_ENCODING_NRZI HDLC_ENCODING_NRZI_SPACE 108 #define HDLC_ENCODING_BIPHASE_MARK 4 109 #define HDLC_ENCODING_BIPHASE_SPACE 5 110 #define HDLC_ENCODING_BIPHASE_LEVEL 6 111 #define HDLC_ENCODING_DIFF_BIPHASE_LEVEL 7 112 113 #define HDLC_PREAMBLE_LENGTH_8BITS 0 114 #define HDLC_PREAMBLE_LENGTH_16BITS 1 115 #define HDLC_PREAMBLE_LENGTH_32BITS 2 116 #define HDLC_PREAMBLE_LENGTH_64BITS 3 117 118 #define HDLC_PREAMBLE_PATTERN_NONE 0 119 #define HDLC_PREAMBLE_PATTERN_ZEROS 1 120 #define HDLC_PREAMBLE_PATTERN_FLAGS 2 121 #define HDLC_PREAMBLE_PATTERN_10 3 122 #define HDLC_PREAMBLE_PATTERN_01 4 123 #define HDLC_PREAMBLE_PATTERN_ONES 5 124 125 #define MGSL_MODE_ASYNC 1 126 #define MGSL_MODE_HDLC 2 127 #define MGSL_MODE_MONOSYNC 3 128 #define MGSL_MODE_BISYNC 4 129 #define MGSL_MODE_RAW 6 130 131 #define MGSL_BUS_TYPE_ISA 1 132 #define MGSL_BUS_TYPE_EISA 2 133 #define MGSL_BUS_TYPE_PCI 5 134 135 #define MGSL_INTERFACE_MASK 0xf 136 #define MGSL_INTERFACE_DISABLE 0 137 #define MGSL_INTERFACE_RS232 1 138 #define MGSL_INTERFACE_V35 2 139 #define MGSL_INTERFACE_RS422 3 140 #define MGSL_INTERFACE_RTS_EN 0x10 141 #define MGSL_INTERFACE_LL 0x20 142 #define MGSL_INTERFACE_RL 0x40 143 144 typedef struct _MGSL_PARAMS 145 { 146 /* Common */ 147 148 unsigned long mode; /* Asynchronous or HDLC */ 149 unsigned char loopback; /* internal loopback mode */ 150 151 /* HDLC Only */ 152 153 unsigned short flags; 154 unsigned char encoding; /* NRZ, NRZI, etc. */ 155 unsigned long clock_speed; /* external clock speed in bits per second */ 156 unsigned char addr_filter; /* receive HDLC address filter, 0xFF = disable */ 157 unsigned short crc_type; /* None, CRC16-CCITT, or CRC32-CCITT */ 158 unsigned char preamble_length; 159 unsigned char preamble; 160 161 /* Async Only */ 162 163 unsigned long data_rate; /* bits per second */ 164 unsigned char data_bits; /* 7 or 8 data bits */ 165 unsigned char stop_bits; /* 1 or 2 stop bits */ 166 unsigned char parity; /* none, even, or odd */ 167 168 } MGSL_PARAMS, *PMGSL_PARAMS; 169 170 #define MICROGATE_VENDOR_ID 0x13c0 171 #define SYNCLINK_DEVICE_ID 0x0010 172 #define MGSCC_DEVICE_ID 0x0020 173 #define SYNCLINK_SCA_DEVICE_ID 0x0030 174 #define SYNCLINK_GT_DEVICE_ID 0x0070 175 #define SYNCLINK_GT4_DEVICE_ID 0x0080 176 #define SYNCLINK_AC_DEVICE_ID 0x0090 177 #define SYNCLINK_GT2_DEVICE_ID 0x00A0 178 #define MGSL_MAX_SERIAL_NUMBER 30 179 180 /* 181 ** device diagnostics status 182 */ 183 184 #define DiagStatus_OK 0 185 #define DiagStatus_AddressFailure 1 186 #define DiagStatus_AddressConflict 2 187 #define DiagStatus_IrqFailure 3 188 #define DiagStatus_IrqConflict 4 189 #define DiagStatus_DmaFailure 5 190 #define DiagStatus_DmaConflict 6 191 #define DiagStatus_PciAdapterNotFound 7 192 #define DiagStatus_CantAssignPciResources 8 193 #define DiagStatus_CantAssignPciMemAddr 9 194 #define DiagStatus_CantAssignPciIoAddr 10 195 #define DiagStatus_CantAssignPciIrq 11 196 #define DiagStatus_MemoryError 12 197 198 #define SerialSignal_DCD 0x01 /* Data Carrier Detect */ 199 #define SerialSignal_TXD 0x02 /* Transmit Data */ 200 #define SerialSignal_RI 0x04 /* Ring Indicator */ 201 #define SerialSignal_RXD 0x08 /* Receive Data */ 202 #define SerialSignal_CTS 0x10 /* Clear to Send */ 203 #define SerialSignal_RTS 0x20 /* Request to Send */ 204 #define SerialSignal_DSR 0x40 /* Data Set Ready */ 205 #define SerialSignal_DTR 0x80 /* Data Terminal Ready */ 206 207 208 /* 209 * Counters of the input lines (CTS, DSR, RI, CD) interrupts 210 */ 211 struct mgsl_icount { 212 __u32 cts, dsr, rng, dcd, tx, rx; 213 __u32 frame, parity, overrun, brk; 214 __u32 buf_overrun; 215 __u32 txok; 216 __u32 txunder; 217 __u32 txabort; 218 __u32 txtimeout; 219 __u32 rxshort; 220 __u32 rxlong; 221 __u32 rxabort; 222 __u32 rxover; 223 __u32 rxcrc; 224 __u32 rxok; 225 __u32 exithunt; 226 __u32 rxidle; 227 }; 228 229 struct gpio_desc { 230 __u32 state; 231 __u32 smask; 232 __u32 dir; 233 __u32 dmask; 234 }; 235 236 #define DEBUG_LEVEL_DATA 1 237 #define DEBUG_LEVEL_ERROR 2 238 #define DEBUG_LEVEL_INFO 3 239 #define DEBUG_LEVEL_BH 4 240 #define DEBUG_LEVEL_ISR 5 241 242 /* 243 ** Event bit flags for use with MgslWaitEvent 244 */ 245 246 #define MgslEvent_DsrActive 0x0001 247 #define MgslEvent_DsrInactive 0x0002 248 #define MgslEvent_Dsr 0x0003 249 #define MgslEvent_CtsActive 0x0004 250 #define MgslEvent_CtsInactive 0x0008 251 #define MgslEvent_Cts 0x000c 252 #define MgslEvent_DcdActive 0x0010 253 #define MgslEvent_DcdInactive 0x0020 254 #define MgslEvent_Dcd 0x0030 255 #define MgslEvent_RiActive 0x0040 256 #define MgslEvent_RiInactive 0x0080 257 #define MgslEvent_Ri 0x00c0 258 #define MgslEvent_ExitHuntMode 0x0100 259 #define MgslEvent_IdleReceived 0x0200 260 261 /* Private IOCTL codes: 262 * 263 * MGSL_IOCSPARAMS set MGSL_PARAMS structure values 264 * MGSL_IOCGPARAMS get current MGSL_PARAMS structure values 265 * MGSL_IOCSTXIDLE set current transmit idle mode 266 * MGSL_IOCGTXIDLE get current transmit idle mode 267 * MGSL_IOCTXENABLE enable or disable transmitter 268 * MGSL_IOCRXENABLE enable or disable receiver 269 * MGSL_IOCTXABORT abort transmitting frame (HDLC) 270 * MGSL_IOCGSTATS return current statistics 271 * MGSL_IOCWAITEVENT wait for specified event to occur 272 * MGSL_LOOPTXDONE transmit in HDLC LoopMode done 273 * MGSL_IOCSIF set the serial interface type 274 * MGSL_IOCGIF get the serial interface type 275 */ 276 #define MGSL_MAGIC_IOC 'm' 277 #define MGSL_IOCSPARAMS _IOW(MGSL_MAGIC_IOC,0,struct _MGSL_PARAMS) 278 #define MGSL_IOCGPARAMS _IOR(MGSL_MAGIC_IOC,1,struct _MGSL_PARAMS) 279 #define MGSL_IOCSTXIDLE _IO(MGSL_MAGIC_IOC,2) 280 #define MGSL_IOCGTXIDLE _IO(MGSL_MAGIC_IOC,3) 281 #define MGSL_IOCTXENABLE _IO(MGSL_MAGIC_IOC,4) 282 #define MGSL_IOCRXENABLE _IO(MGSL_MAGIC_IOC,5) 283 #define MGSL_IOCTXABORT _IO(MGSL_MAGIC_IOC,6) 284 #define MGSL_IOCGSTATS _IO(MGSL_MAGIC_IOC,7) 285 #define MGSL_IOCWAITEVENT _IOWR(MGSL_MAGIC_IOC,8,int) 286 #define MGSL_IOCCLRMODCOUNT _IO(MGSL_MAGIC_IOC,15) 287 #define MGSL_IOCLOOPTXDONE _IO(MGSL_MAGIC_IOC,9) 288 #define MGSL_IOCSIF _IO(MGSL_MAGIC_IOC,10) 289 #define MGSL_IOCGIF _IO(MGSL_MAGIC_IOC,11) 290 #define MGSL_IOCSGPIO _IOW(MGSL_MAGIC_IOC,16,struct gpio_desc) 291 #define MGSL_IOCGGPIO _IOR(MGSL_MAGIC_IOC,17,struct gpio_desc) 292 #define MGSL_IOCWAITGPIO _IOWR(MGSL_MAGIC_IOC,18,struct gpio_desc) 293 294 #endif /* _SYNCLINK_H_ */ 295