1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 21edb9ca6SSiva Reddy /* 3*5adcb8b1SKrzysztof Kozlowski * 10G controller driver for Samsung Exynos SoCs 41edb9ca6SSiva Reddy * 51edb9ca6SSiva Reddy * Copyright (C) 2013 Samsung Electronics Co., Ltd. 61edb9ca6SSiva Reddy * http://www.samsung.com 71edb9ca6SSiva Reddy * 81edb9ca6SSiva Reddy * Author: Siva Reddy Kallam <[email protected]> 91edb9ca6SSiva Reddy */ 101edb9ca6SSiva Reddy #ifndef __SXGBE_PLATFORM_H__ 111edb9ca6SSiva Reddy #define __SXGBE_PLATFORM_H__ 121edb9ca6SSiva Reddy 130c65b2b9SAndrew Lunn #include <linux/phy.h> 140c65b2b9SAndrew Lunn 151edb9ca6SSiva Reddy /* MDC Clock Selection define*/ 161edb9ca6SSiva Reddy #define SXGBE_CSR_100_150M 0x0 /* MDC = clk_scr_i/62 */ 171edb9ca6SSiva Reddy #define SXGBE_CSR_150_250M 0x1 /* MDC = clk_scr_i/102 */ 181edb9ca6SSiva Reddy #define SXGBE_CSR_250_300M 0x2 /* MDC = clk_scr_i/122 */ 191edb9ca6SSiva Reddy #define SXGBE_CSR_300_350M 0x3 /* MDC = clk_scr_i/142 */ 201edb9ca6SSiva Reddy #define SXGBE_CSR_350_400M 0x4 /* MDC = clk_scr_i/162 */ 211edb9ca6SSiva Reddy #define SXGBE_CSR_400_500M 0x5 /* MDC = clk_scr_i/202 */ 221edb9ca6SSiva Reddy 231edb9ca6SSiva Reddy /* Platfrom data for platform device structure's 241edb9ca6SSiva Reddy * platform_data field 251edb9ca6SSiva Reddy */ 261edb9ca6SSiva Reddy struct sxgbe_mdio_bus_data { 271edb9ca6SSiva Reddy unsigned int phy_mask; 281edb9ca6SSiva Reddy int *irqs; 291edb9ca6SSiva Reddy int probed_phy_irq; 301edb9ca6SSiva Reddy }; 311edb9ca6SSiva Reddy 321edb9ca6SSiva Reddy struct sxgbe_dma_cfg { 331edb9ca6SSiva Reddy int pbl; 341edb9ca6SSiva Reddy int fixed_burst; 351edb9ca6SSiva Reddy int burst_map; 361edb9ca6SSiva Reddy int adv_addr_mode; 371edb9ca6SSiva Reddy }; 381edb9ca6SSiva Reddy 391edb9ca6SSiva Reddy struct sxgbe_plat_data { 401edb9ca6SSiva Reddy char *phy_bus_name; 411edb9ca6SSiva Reddy int bus_id; 421edb9ca6SSiva Reddy int phy_addr; 430c65b2b9SAndrew Lunn phy_interface_t interface; 441edb9ca6SSiva Reddy struct sxgbe_mdio_bus_data *mdio_bus_data; 451edb9ca6SSiva Reddy struct sxgbe_dma_cfg *dma_cfg; 461edb9ca6SSiva Reddy int clk_csr; 471edb9ca6SSiva Reddy int pmt; 481edb9ca6SSiva Reddy int force_sf_dma_mode; 491edb9ca6SSiva Reddy int force_thresh_dma_mode; 501edb9ca6SSiva Reddy int riwt_off; 511edb9ca6SSiva Reddy }; 521edb9ca6SSiva Reddy 531edb9ca6SSiva Reddy #endif /* __SXGBE_PLATFORM_H__ */ 54