1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Microsemi Switchtec PCIe Driver 4 * Copyright (c) 2017, Microsemi Corporation 5 */ 6 7 #ifndef _SWITCHTEC_H 8 #define _SWITCHTEC_H 9 10 #include <linux/pci.h> 11 #include <linux/cdev.h> 12 13 #define SWITCHTEC_MRPC_PAYLOAD_SIZE 1024 14 #define SWITCHTEC_MAX_PFF_CSR 255 15 16 #define SWITCHTEC_EVENT_OCCURRED BIT(0) 17 #define SWITCHTEC_EVENT_CLEAR BIT(0) 18 #define SWITCHTEC_EVENT_EN_LOG BIT(1) 19 #define SWITCHTEC_EVENT_EN_CLI BIT(2) 20 #define SWITCHTEC_EVENT_EN_IRQ BIT(3) 21 #define SWITCHTEC_EVENT_FATAL BIT(4) 22 23 #define SWITCHTEC_DMA_MRPC_EN BIT(0) 24 enum { 25 SWITCHTEC_GAS_MRPC_OFFSET = 0x0000, 26 SWITCHTEC_GAS_TOP_CFG_OFFSET = 0x1000, 27 SWITCHTEC_GAS_SW_EVENT_OFFSET = 0x1800, 28 SWITCHTEC_GAS_SYS_INFO_OFFSET = 0x2000, 29 SWITCHTEC_GAS_FLASH_INFO_OFFSET = 0x2200, 30 SWITCHTEC_GAS_PART_CFG_OFFSET = 0x4000, 31 SWITCHTEC_GAS_NTB_OFFSET = 0x10000, 32 SWITCHTEC_GAS_PFF_CSR_OFFSET = 0x134000, 33 }; 34 35 enum switchtec_gen { 36 SWITCHTEC_GEN3, 37 }; 38 39 struct mrpc_regs { 40 u8 input_data[SWITCHTEC_MRPC_PAYLOAD_SIZE]; 41 u8 output_data[SWITCHTEC_MRPC_PAYLOAD_SIZE]; 42 u32 cmd; 43 u32 status; 44 u32 ret_value; 45 u32 dma_en; 46 u64 dma_addr; 47 u32 dma_vector; 48 u32 dma_ver; 49 } __packed; 50 51 enum mrpc_status { 52 SWITCHTEC_MRPC_STATUS_INPROGRESS = 1, 53 SWITCHTEC_MRPC_STATUS_DONE = 2, 54 SWITCHTEC_MRPC_STATUS_ERROR = 0xFF, 55 SWITCHTEC_MRPC_STATUS_INTERRUPTED = 0x100, 56 }; 57 58 struct sw_event_regs { 59 u64 event_report_ctrl; 60 u64 reserved1; 61 u64 part_event_bitmap; 62 u64 reserved2; 63 u32 global_summary; 64 u32 reserved3[3]; 65 u32 stack_error_event_hdr; 66 u32 stack_error_event_data; 67 u32 reserved4[4]; 68 u32 ppu_error_event_hdr; 69 u32 ppu_error_event_data; 70 u32 reserved5[4]; 71 u32 isp_error_event_hdr; 72 u32 isp_error_event_data; 73 u32 reserved6[4]; 74 u32 sys_reset_event_hdr; 75 u32 reserved7[5]; 76 u32 fw_exception_hdr; 77 u32 reserved8[5]; 78 u32 fw_nmi_hdr; 79 u32 reserved9[5]; 80 u32 fw_non_fatal_hdr; 81 u32 reserved10[5]; 82 u32 fw_fatal_hdr; 83 u32 reserved11[5]; 84 u32 twi_mrpc_comp_hdr; 85 u32 twi_mrpc_comp_data; 86 u32 reserved12[4]; 87 u32 twi_mrpc_comp_async_hdr; 88 u32 twi_mrpc_comp_async_data; 89 u32 reserved13[4]; 90 u32 cli_mrpc_comp_hdr; 91 u32 cli_mrpc_comp_data; 92 u32 reserved14[4]; 93 u32 cli_mrpc_comp_async_hdr; 94 u32 cli_mrpc_comp_async_data; 95 u32 reserved15[4]; 96 u32 gpio_interrupt_hdr; 97 u32 gpio_interrupt_data; 98 u32 reserved16[4]; 99 u32 gfms_event_hdr; 100 u32 gfms_event_data; 101 u32 reserved17[4]; 102 } __packed; 103 104 enum { 105 SWITCHTEC_GEN3_CFG0_RUNNING = 0x04, 106 SWITCHTEC_GEN3_CFG1_RUNNING = 0x05, 107 SWITCHTEC_GEN3_IMG0_RUNNING = 0x03, 108 SWITCHTEC_GEN3_IMG1_RUNNING = 0x07, 109 }; 110 111 struct sys_info_regs { 112 u32 device_id; 113 u32 device_version; 114 u32 firmware_version; 115 u32 reserved1; 116 u32 vendor_table_revision; 117 u32 table_format_version; 118 u32 partition_id; 119 u32 cfg_file_fmt_version; 120 u16 cfg_running; 121 u16 img_running; 122 u32 reserved2[57]; 123 char vendor_id[8]; 124 char product_id[16]; 125 char product_revision[4]; 126 char component_vendor[8]; 127 u16 component_id; 128 u8 component_revision; 129 } __packed; 130 131 struct flash_info_regs { 132 u32 flash_part_map_upd_idx; 133 134 struct active_partition_info { 135 u32 address; 136 u32 build_version; 137 u32 build_string; 138 } active_img; 139 140 struct active_partition_info active_cfg; 141 struct active_partition_info inactive_img; 142 struct active_partition_info inactive_cfg; 143 144 u32 flash_length; 145 146 struct partition_info { 147 u32 address; 148 u32 length; 149 } cfg0; 150 151 struct partition_info cfg1; 152 struct partition_info img0; 153 struct partition_info img1; 154 struct partition_info nvlog; 155 struct partition_info vendor[8]; 156 }; 157 158 enum { 159 SWITCHTEC_NTB_REG_INFO_OFFSET = 0x0000, 160 SWITCHTEC_NTB_REG_CTRL_OFFSET = 0x4000, 161 SWITCHTEC_NTB_REG_DBMSG_OFFSET = 0x64000, 162 }; 163 164 struct ntb_info_regs { 165 u8 partition_count; 166 u8 partition_id; 167 u16 reserved1; 168 u64 ep_map; 169 u16 requester_id; 170 u16 reserved2; 171 u32 reserved3[4]; 172 struct nt_partition_info { 173 u32 xlink_enabled; 174 u32 target_part_low; 175 u32 target_part_high; 176 u32 reserved; 177 } ntp_info[48]; 178 } __packed; 179 180 struct part_cfg_regs { 181 u32 status; 182 u32 state; 183 u32 port_cnt; 184 u32 usp_port_mode; 185 u32 usp_pff_inst_id; 186 u32 vep_pff_inst_id; 187 u32 dsp_pff_inst_id[47]; 188 u32 reserved1[11]; 189 u16 vep_vector_number; 190 u16 usp_vector_number; 191 u32 port_event_bitmap; 192 u32 reserved2[3]; 193 u32 part_event_summary; 194 u32 reserved3[3]; 195 u32 part_reset_hdr; 196 u32 part_reset_data[5]; 197 u32 mrpc_comp_hdr; 198 u32 mrpc_comp_data[5]; 199 u32 mrpc_comp_async_hdr; 200 u32 mrpc_comp_async_data[5]; 201 u32 dyn_binding_hdr; 202 u32 dyn_binding_data[5]; 203 u32 intercomm_notify_hdr; 204 u32 intercomm_notify_data[5]; 205 u32 reserved4[153]; 206 } __packed; 207 208 enum { 209 NTB_CTRL_PART_OP_LOCK = 0x1, 210 NTB_CTRL_PART_OP_CFG = 0x2, 211 NTB_CTRL_PART_OP_RESET = 0x3, 212 213 NTB_CTRL_PART_STATUS_NORMAL = 0x1, 214 NTB_CTRL_PART_STATUS_LOCKED = 0x2, 215 NTB_CTRL_PART_STATUS_LOCKING = 0x3, 216 NTB_CTRL_PART_STATUS_CONFIGURING = 0x4, 217 NTB_CTRL_PART_STATUS_RESETTING = 0x5, 218 219 NTB_CTRL_BAR_VALID = 1 << 0, 220 NTB_CTRL_BAR_DIR_WIN_EN = 1 << 4, 221 NTB_CTRL_BAR_LUT_WIN_EN = 1 << 5, 222 223 NTB_CTRL_REQ_ID_EN = 1 << 0, 224 225 NTB_CTRL_LUT_EN = 1 << 0, 226 227 NTB_PART_CTRL_ID_PROT_DIS = 1 << 0, 228 }; 229 230 struct ntb_ctrl_regs { 231 u32 partition_status; 232 u32 partition_op; 233 u32 partition_ctrl; 234 u32 bar_setup; 235 u32 bar_error; 236 u16 lut_table_entries; 237 u16 lut_table_offset; 238 u32 lut_error; 239 u16 req_id_table_size; 240 u16 req_id_table_offset; 241 u32 req_id_error; 242 u32 reserved1[7]; 243 struct { 244 u32 ctl; 245 u32 win_size; 246 u64 xlate_addr; 247 } bar_entry[6]; 248 struct { 249 u32 win_size; 250 u32 reserved[3]; 251 } bar_ext_entry[6]; 252 u32 reserved2[192]; 253 u32 req_id_table[512]; 254 u32 reserved3[256]; 255 u64 lut_entry[512]; 256 } __packed; 257 258 #define NTB_DBMSG_IMSG_STATUS BIT_ULL(32) 259 #define NTB_DBMSG_IMSG_MASK BIT_ULL(40) 260 261 struct ntb_dbmsg_regs { 262 u32 reserved1[1024]; 263 u64 odb; 264 u64 odb_mask; 265 u64 idb; 266 u64 idb_mask; 267 u8 idb_vec_map[64]; 268 u32 msg_map; 269 u32 reserved2; 270 struct { 271 u32 msg; 272 u32 status; 273 } omsg[4]; 274 275 struct { 276 u32 msg; 277 u8 status; 278 u8 mask; 279 u8 src; 280 u8 reserved; 281 } imsg[4]; 282 283 u8 reserved3[3928]; 284 u8 msix_table[1024]; 285 u8 reserved4[3072]; 286 u8 pba[24]; 287 u8 reserved5[4072]; 288 } __packed; 289 290 enum { 291 SWITCHTEC_PART_CFG_EVENT_RESET = 1 << 0, 292 SWITCHTEC_PART_CFG_EVENT_MRPC_CMP = 1 << 1, 293 SWITCHTEC_PART_CFG_EVENT_MRPC_ASYNC_CMP = 1 << 2, 294 SWITCHTEC_PART_CFG_EVENT_DYN_PART_CMP = 1 << 3, 295 }; 296 297 struct pff_csr_regs { 298 u16 vendor_id; 299 u16 device_id; 300 u16 pcicmd; 301 u16 pcists; 302 u32 pci_class; 303 u32 pci_opts; 304 union { 305 u32 pci_bar[6]; 306 u64 pci_bar64[3]; 307 }; 308 u32 pci_cardbus; 309 u32 pci_subsystem_id; 310 u32 pci_expansion_rom; 311 u32 pci_cap_ptr; 312 u32 reserved1; 313 u32 pci_irq; 314 u32 pci_cap_region[48]; 315 u32 pcie_cap_region[448]; 316 u32 indirect_gas_window[128]; 317 u32 indirect_gas_window_off; 318 u32 reserved[127]; 319 u32 pff_event_summary; 320 u32 reserved2[3]; 321 u32 aer_in_p2p_hdr; 322 u32 aer_in_p2p_data[5]; 323 u32 aer_in_vep_hdr; 324 u32 aer_in_vep_data[5]; 325 u32 dpc_hdr; 326 u32 dpc_data[5]; 327 u32 cts_hdr; 328 u32 cts_data[5]; 329 u32 uec_hdr; 330 u32 uec_data[5]; 331 u32 hotplug_hdr; 332 u32 hotplug_data[5]; 333 u32 ier_hdr; 334 u32 ier_data[5]; 335 u32 threshold_hdr; 336 u32 threshold_data[5]; 337 u32 power_mgmt_hdr; 338 u32 power_mgmt_data[5]; 339 u32 tlp_throttling_hdr; 340 u32 tlp_throttling_data[5]; 341 u32 force_speed_hdr; 342 u32 force_speed_data[5]; 343 u32 credit_timeout_hdr; 344 u32 credit_timeout_data[5]; 345 u32 link_state_hdr; 346 u32 link_state_data[5]; 347 u32 reserved4[174]; 348 } __packed; 349 350 struct switchtec_ntb; 351 352 struct dma_mrpc_output { 353 u32 status; 354 u32 cmd_id; 355 u32 rtn_code; 356 u32 output_size; 357 u8 data[SWITCHTEC_MRPC_PAYLOAD_SIZE]; 358 }; 359 360 struct switchtec_dev { 361 struct pci_dev *pdev; 362 struct device dev; 363 struct cdev cdev; 364 365 enum switchtec_gen gen; 366 367 int partition; 368 int partition_count; 369 int pff_csr_count; 370 char pff_local[SWITCHTEC_MAX_PFF_CSR]; 371 372 void __iomem *mmio; 373 struct mrpc_regs __iomem *mmio_mrpc; 374 struct sw_event_regs __iomem *mmio_sw_event; 375 struct sys_info_regs __iomem *mmio_sys_info; 376 struct flash_info_regs __iomem *mmio_flash_info; 377 struct ntb_info_regs __iomem *mmio_ntb; 378 struct part_cfg_regs __iomem *mmio_part_cfg; 379 struct part_cfg_regs __iomem *mmio_part_cfg_all; 380 struct pff_csr_regs __iomem *mmio_pff_csr; 381 382 /* 383 * The mrpc mutex must be held when accessing the other 384 * mrpc_ fields, alive flag and stuser->state field 385 */ 386 struct mutex mrpc_mutex; 387 struct list_head mrpc_queue; 388 int mrpc_busy; 389 struct work_struct mrpc_work; 390 struct delayed_work mrpc_timeout; 391 bool alive; 392 393 wait_queue_head_t event_wq; 394 atomic_t event_cnt; 395 396 struct work_struct link_event_work; 397 void (*link_notifier)(struct switchtec_dev *stdev); 398 u8 link_event_count[SWITCHTEC_MAX_PFF_CSR]; 399 400 struct switchtec_ntb *sndev; 401 402 struct dma_mrpc_output *dma_mrpc; 403 dma_addr_t dma_mrpc_dma_addr; 404 }; 405 406 static inline struct switchtec_dev *to_stdev(struct device *dev) 407 { 408 return container_of(dev, struct switchtec_dev, dev); 409 } 410 411 extern struct class *switchtec_class; 412 413 #endif 414