1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Microsemi Switchtec PCIe Driver 4 * Copyright (c) 2017, Microsemi Corporation 5 */ 6 7 #ifndef _SWITCHTEC_H 8 #define _SWITCHTEC_H 9 10 #include <linux/pci.h> 11 #include <linux/cdev.h> 12 13 #define SWITCHTEC_MRPC_PAYLOAD_SIZE 1024 14 #define SWITCHTEC_MAX_PFF_CSR 255 15 16 #define SWITCHTEC_EVENT_OCCURRED BIT(0) 17 #define SWITCHTEC_EVENT_CLEAR BIT(0) 18 #define SWITCHTEC_EVENT_EN_LOG BIT(1) 19 #define SWITCHTEC_EVENT_EN_CLI BIT(2) 20 #define SWITCHTEC_EVENT_EN_IRQ BIT(3) 21 #define SWITCHTEC_EVENT_FATAL BIT(4) 22 23 #define SWITCHTEC_DMA_MRPC_EN BIT(0) 24 enum { 25 SWITCHTEC_GAS_MRPC_OFFSET = 0x0000, 26 SWITCHTEC_GAS_TOP_CFG_OFFSET = 0x1000, 27 SWITCHTEC_GAS_SW_EVENT_OFFSET = 0x1800, 28 SWITCHTEC_GAS_SYS_INFO_OFFSET = 0x2000, 29 SWITCHTEC_GAS_FLASH_INFO_OFFSET = 0x2200, 30 SWITCHTEC_GAS_PART_CFG_OFFSET = 0x4000, 31 SWITCHTEC_GAS_NTB_OFFSET = 0x10000, 32 SWITCHTEC_GAS_PFF_CSR_OFFSET = 0x134000, 33 }; 34 35 enum switchtec_gen { 36 SWITCHTEC_GEN3, 37 SWITCHTEC_GEN4, 38 }; 39 40 struct mrpc_regs { 41 u8 input_data[SWITCHTEC_MRPC_PAYLOAD_SIZE]; 42 u8 output_data[SWITCHTEC_MRPC_PAYLOAD_SIZE]; 43 u32 cmd; 44 u32 status; 45 u32 ret_value; 46 u32 dma_en; 47 u64 dma_addr; 48 u32 dma_vector; 49 u32 dma_ver; 50 } __packed; 51 52 enum mrpc_status { 53 SWITCHTEC_MRPC_STATUS_INPROGRESS = 1, 54 SWITCHTEC_MRPC_STATUS_DONE = 2, 55 SWITCHTEC_MRPC_STATUS_ERROR = 0xFF, 56 SWITCHTEC_MRPC_STATUS_INTERRUPTED = 0x100, 57 }; 58 59 struct sw_event_regs { 60 u64 event_report_ctrl; 61 u64 reserved1; 62 u64 part_event_bitmap; 63 u64 reserved2; 64 u32 global_summary; 65 u32 reserved3[3]; 66 u32 stack_error_event_hdr; 67 u32 stack_error_event_data; 68 u32 reserved4[4]; 69 u32 ppu_error_event_hdr; 70 u32 ppu_error_event_data; 71 u32 reserved5[4]; 72 u32 isp_error_event_hdr; 73 u32 isp_error_event_data; 74 u32 reserved6[4]; 75 u32 sys_reset_event_hdr; 76 u32 reserved7[5]; 77 u32 fw_exception_hdr; 78 u32 reserved8[5]; 79 u32 fw_nmi_hdr; 80 u32 reserved9[5]; 81 u32 fw_non_fatal_hdr; 82 u32 reserved10[5]; 83 u32 fw_fatal_hdr; 84 u32 reserved11[5]; 85 u32 twi_mrpc_comp_hdr; 86 u32 twi_mrpc_comp_data; 87 u32 reserved12[4]; 88 u32 twi_mrpc_comp_async_hdr; 89 u32 twi_mrpc_comp_async_data; 90 u32 reserved13[4]; 91 u32 cli_mrpc_comp_hdr; 92 u32 cli_mrpc_comp_data; 93 u32 reserved14[4]; 94 u32 cli_mrpc_comp_async_hdr; 95 u32 cli_mrpc_comp_async_data; 96 u32 reserved15[4]; 97 u32 gpio_interrupt_hdr; 98 u32 gpio_interrupt_data; 99 u32 reserved16[4]; 100 u32 gfms_event_hdr; 101 u32 gfms_event_data; 102 u32 reserved17[4]; 103 } __packed; 104 105 enum { 106 SWITCHTEC_GEN3_CFG0_RUNNING = 0x04, 107 SWITCHTEC_GEN3_CFG1_RUNNING = 0x05, 108 SWITCHTEC_GEN3_IMG0_RUNNING = 0x03, 109 SWITCHTEC_GEN3_IMG1_RUNNING = 0x07, 110 }; 111 112 struct sys_info_regs_gen3 { 113 u32 reserved1; 114 u32 vendor_table_revision; 115 u32 table_format_version; 116 u32 partition_id; 117 u32 cfg_file_fmt_version; 118 u16 cfg_running; 119 u16 img_running; 120 u32 reserved2[57]; 121 char vendor_id[8]; 122 char product_id[16]; 123 char product_revision[4]; 124 char component_vendor[8]; 125 u16 component_id; 126 u8 component_revision; 127 } __packed; 128 129 struct sys_info_regs_gen4 { 130 u16 gas_layout_ver; 131 u8 evlist_ver; 132 u8 reserved1; 133 u16 mgmt_cmd_set_ver; 134 u16 fabric_cmd_set_ver; 135 u32 reserved2[2]; 136 u8 mrpc_uart_ver; 137 u8 mrpc_twi_ver; 138 u8 mrpc_eth_ver; 139 u8 mrpc_inband_ver; 140 u32 reserved3[7]; 141 u32 fw_update_tmo; 142 u32 xml_version_cfg; 143 u32 xml_version_img; 144 u32 partition_id; 145 u16 bl2_running; 146 u16 cfg_running; 147 u16 img_running; 148 u16 key_running; 149 u32 reserved4[43]; 150 u32 vendor_seeprom_twi; 151 u32 vendor_table_revision; 152 u32 vendor_specific_info[2]; 153 u16 p2p_vendor_id; 154 u16 p2p_device_id; 155 u8 p2p_revision_id; 156 u8 reserved5[3]; 157 u32 p2p_class_id; 158 u16 subsystem_vendor_id; 159 u16 subsystem_id; 160 u32 p2p_serial_number[2]; 161 u8 mac_addr[6]; 162 u8 reserved6[2]; 163 u32 reserved7[3]; 164 char vendor_id[8]; 165 char product_id[24]; 166 char product_revision[2]; 167 u16 reserved8; 168 } __packed; 169 170 struct sys_info_regs { 171 u32 device_id; 172 u32 device_version; 173 u32 firmware_version; 174 union { 175 struct sys_info_regs_gen3 gen3; 176 struct sys_info_regs_gen4 gen4; 177 }; 178 } __packed; 179 180 struct partition_info { 181 u32 address; 182 u32 length; 183 }; 184 185 struct flash_info_regs_gen3 { 186 u32 flash_part_map_upd_idx; 187 188 struct active_partition_info_gen3 { 189 u32 address; 190 u32 build_version; 191 u32 build_string; 192 } active_img; 193 194 struct active_partition_info_gen3 active_cfg; 195 struct active_partition_info_gen3 inactive_img; 196 struct active_partition_info_gen3 inactive_cfg; 197 198 u32 flash_length; 199 200 struct partition_info cfg0; 201 struct partition_info cfg1; 202 struct partition_info img0; 203 struct partition_info img1; 204 struct partition_info nvlog; 205 struct partition_info vendor[8]; 206 }; 207 208 struct flash_info_regs { 209 union { 210 struct flash_info_regs_gen3 gen3; 211 }; 212 }; 213 214 enum { 215 SWITCHTEC_NTB_REG_INFO_OFFSET = 0x0000, 216 SWITCHTEC_NTB_REG_CTRL_OFFSET = 0x4000, 217 SWITCHTEC_NTB_REG_DBMSG_OFFSET = 0x64000, 218 }; 219 220 struct ntb_info_regs { 221 u8 partition_count; 222 u8 partition_id; 223 u16 reserved1; 224 u64 ep_map; 225 u16 requester_id; 226 u16 reserved2; 227 u32 reserved3[4]; 228 struct nt_partition_info { 229 u32 xlink_enabled; 230 u32 target_part_low; 231 u32 target_part_high; 232 u32 reserved; 233 } ntp_info[48]; 234 } __packed; 235 236 struct part_cfg_regs { 237 u32 status; 238 u32 state; 239 u32 port_cnt; 240 u32 usp_port_mode; 241 u32 usp_pff_inst_id; 242 u32 vep_pff_inst_id; 243 u32 dsp_pff_inst_id[47]; 244 u32 reserved1[11]; 245 u16 vep_vector_number; 246 u16 usp_vector_number; 247 u32 port_event_bitmap; 248 u32 reserved2[3]; 249 u32 part_event_summary; 250 u32 reserved3[3]; 251 u32 part_reset_hdr; 252 u32 part_reset_data[5]; 253 u32 mrpc_comp_hdr; 254 u32 mrpc_comp_data[5]; 255 u32 mrpc_comp_async_hdr; 256 u32 mrpc_comp_async_data[5]; 257 u32 dyn_binding_hdr; 258 u32 dyn_binding_data[5]; 259 u32 intercomm_notify_hdr; 260 u32 intercomm_notify_data[5]; 261 u32 reserved4[153]; 262 } __packed; 263 264 enum { 265 NTB_CTRL_PART_OP_LOCK = 0x1, 266 NTB_CTRL_PART_OP_CFG = 0x2, 267 NTB_CTRL_PART_OP_RESET = 0x3, 268 269 NTB_CTRL_PART_STATUS_NORMAL = 0x1, 270 NTB_CTRL_PART_STATUS_LOCKED = 0x2, 271 NTB_CTRL_PART_STATUS_LOCKING = 0x3, 272 NTB_CTRL_PART_STATUS_CONFIGURING = 0x4, 273 NTB_CTRL_PART_STATUS_RESETTING = 0x5, 274 275 NTB_CTRL_BAR_VALID = 1 << 0, 276 NTB_CTRL_BAR_DIR_WIN_EN = 1 << 4, 277 NTB_CTRL_BAR_LUT_WIN_EN = 1 << 5, 278 279 NTB_CTRL_REQ_ID_EN = 1 << 0, 280 281 NTB_CTRL_LUT_EN = 1 << 0, 282 283 NTB_PART_CTRL_ID_PROT_DIS = 1 << 0, 284 }; 285 286 struct ntb_ctrl_regs { 287 u32 partition_status; 288 u32 partition_op; 289 u32 partition_ctrl; 290 u32 bar_setup; 291 u32 bar_error; 292 u16 lut_table_entries; 293 u16 lut_table_offset; 294 u32 lut_error; 295 u16 req_id_table_size; 296 u16 req_id_table_offset; 297 u32 req_id_error; 298 u32 reserved1[7]; 299 struct { 300 u32 ctl; 301 u32 win_size; 302 u64 xlate_addr; 303 } bar_entry[6]; 304 struct { 305 u32 win_size; 306 u32 reserved[3]; 307 } bar_ext_entry[6]; 308 u32 reserved2[192]; 309 u32 req_id_table[512]; 310 u32 reserved3[256]; 311 u64 lut_entry[512]; 312 } __packed; 313 314 #define NTB_DBMSG_IMSG_STATUS BIT_ULL(32) 315 #define NTB_DBMSG_IMSG_MASK BIT_ULL(40) 316 317 struct ntb_dbmsg_regs { 318 u32 reserved1[1024]; 319 u64 odb; 320 u64 odb_mask; 321 u64 idb; 322 u64 idb_mask; 323 u8 idb_vec_map[64]; 324 u32 msg_map; 325 u32 reserved2; 326 struct { 327 u32 msg; 328 u32 status; 329 } omsg[4]; 330 331 struct { 332 u32 msg; 333 u8 status; 334 u8 mask; 335 u8 src; 336 u8 reserved; 337 } imsg[4]; 338 339 u8 reserved3[3928]; 340 u8 msix_table[1024]; 341 u8 reserved4[3072]; 342 u8 pba[24]; 343 u8 reserved5[4072]; 344 } __packed; 345 346 enum { 347 SWITCHTEC_PART_CFG_EVENT_RESET = 1 << 0, 348 SWITCHTEC_PART_CFG_EVENT_MRPC_CMP = 1 << 1, 349 SWITCHTEC_PART_CFG_EVENT_MRPC_ASYNC_CMP = 1 << 2, 350 SWITCHTEC_PART_CFG_EVENT_DYN_PART_CMP = 1 << 3, 351 }; 352 353 struct pff_csr_regs { 354 u16 vendor_id; 355 u16 device_id; 356 u16 pcicmd; 357 u16 pcists; 358 u32 pci_class; 359 u32 pci_opts; 360 union { 361 u32 pci_bar[6]; 362 u64 pci_bar64[3]; 363 }; 364 u32 pci_cardbus; 365 u32 pci_subsystem_id; 366 u32 pci_expansion_rom; 367 u32 pci_cap_ptr; 368 u32 reserved1; 369 u32 pci_irq; 370 u32 pci_cap_region[48]; 371 u32 pcie_cap_region[448]; 372 u32 indirect_gas_window[128]; 373 u32 indirect_gas_window_off; 374 u32 reserved[127]; 375 u32 pff_event_summary; 376 u32 reserved2[3]; 377 u32 aer_in_p2p_hdr; 378 u32 aer_in_p2p_data[5]; 379 u32 aer_in_vep_hdr; 380 u32 aer_in_vep_data[5]; 381 u32 dpc_hdr; 382 u32 dpc_data[5]; 383 u32 cts_hdr; 384 u32 cts_data[5]; 385 u32 uec_hdr; 386 u32 uec_data[5]; 387 u32 hotplug_hdr; 388 u32 hotplug_data[5]; 389 u32 ier_hdr; 390 u32 ier_data[5]; 391 u32 threshold_hdr; 392 u32 threshold_data[5]; 393 u32 power_mgmt_hdr; 394 u32 power_mgmt_data[5]; 395 u32 tlp_throttling_hdr; 396 u32 tlp_throttling_data[5]; 397 u32 force_speed_hdr; 398 u32 force_speed_data[5]; 399 u32 credit_timeout_hdr; 400 u32 credit_timeout_data[5]; 401 u32 link_state_hdr; 402 u32 link_state_data[5]; 403 u32 reserved4[174]; 404 } __packed; 405 406 struct switchtec_ntb; 407 408 struct dma_mrpc_output { 409 u32 status; 410 u32 cmd_id; 411 u32 rtn_code; 412 u32 output_size; 413 u8 data[SWITCHTEC_MRPC_PAYLOAD_SIZE]; 414 }; 415 416 struct switchtec_dev { 417 struct pci_dev *pdev; 418 struct device dev; 419 struct cdev cdev; 420 421 enum switchtec_gen gen; 422 423 int partition; 424 int partition_count; 425 int pff_csr_count; 426 char pff_local[SWITCHTEC_MAX_PFF_CSR]; 427 428 void __iomem *mmio; 429 struct mrpc_regs __iomem *mmio_mrpc; 430 struct sw_event_regs __iomem *mmio_sw_event; 431 struct sys_info_regs __iomem *mmio_sys_info; 432 struct flash_info_regs __iomem *mmio_flash_info; 433 struct ntb_info_regs __iomem *mmio_ntb; 434 struct part_cfg_regs __iomem *mmio_part_cfg; 435 struct part_cfg_regs __iomem *mmio_part_cfg_all; 436 struct pff_csr_regs __iomem *mmio_pff_csr; 437 438 /* 439 * The mrpc mutex must be held when accessing the other 440 * mrpc_ fields, alive flag and stuser->state field 441 */ 442 struct mutex mrpc_mutex; 443 struct list_head mrpc_queue; 444 int mrpc_busy; 445 struct work_struct mrpc_work; 446 struct delayed_work mrpc_timeout; 447 bool alive; 448 449 wait_queue_head_t event_wq; 450 atomic_t event_cnt; 451 452 struct work_struct link_event_work; 453 void (*link_notifier)(struct switchtec_dev *stdev); 454 u8 link_event_count[SWITCHTEC_MAX_PFF_CSR]; 455 456 struct switchtec_ntb *sndev; 457 458 struct dma_mrpc_output *dma_mrpc; 459 dma_addr_t dma_mrpc_dma_addr; 460 }; 461 462 static inline struct switchtec_dev *to_stdev(struct device *dev) 463 { 464 return container_of(dev, struct switchtec_dev, dev); 465 } 466 467 extern struct class *switchtec_class; 468 469 #endif 470