1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Microsemi Switchtec PCIe Driver 4 * Copyright (c) 2017, Microsemi Corporation 5 */ 6 7 #ifndef _SWITCHTEC_H 8 #define _SWITCHTEC_H 9 10 #include <linux/pci.h> 11 #include <linux/cdev.h> 12 13 #define SWITCHTEC_MRPC_PAYLOAD_SIZE 1024 14 #define SWITCHTEC_MAX_PFF_CSR 255 15 16 #define SWITCHTEC_EVENT_OCCURRED BIT(0) 17 #define SWITCHTEC_EVENT_CLEAR BIT(0) 18 #define SWITCHTEC_EVENT_EN_LOG BIT(1) 19 #define SWITCHTEC_EVENT_EN_CLI BIT(2) 20 #define SWITCHTEC_EVENT_EN_IRQ BIT(3) 21 #define SWITCHTEC_EVENT_FATAL BIT(4) 22 23 #define SWITCHTEC_DMA_MRPC_EN BIT(0) 24 enum { 25 SWITCHTEC_GAS_MRPC_OFFSET = 0x0000, 26 SWITCHTEC_GAS_TOP_CFG_OFFSET = 0x1000, 27 SWITCHTEC_GAS_SW_EVENT_OFFSET = 0x1800, 28 SWITCHTEC_GAS_SYS_INFO_OFFSET = 0x2000, 29 SWITCHTEC_GAS_FLASH_INFO_OFFSET = 0x2200, 30 SWITCHTEC_GAS_PART_CFG_OFFSET = 0x4000, 31 SWITCHTEC_GAS_NTB_OFFSET = 0x10000, 32 SWITCHTEC_GAS_PFF_CSR_OFFSET = 0x134000, 33 }; 34 35 enum switchtec_gen { 36 SWITCHTEC_GEN3, 37 }; 38 39 struct mrpc_regs { 40 u8 input_data[SWITCHTEC_MRPC_PAYLOAD_SIZE]; 41 u8 output_data[SWITCHTEC_MRPC_PAYLOAD_SIZE]; 42 u32 cmd; 43 u32 status; 44 u32 ret_value; 45 u32 dma_en; 46 u64 dma_addr; 47 u32 dma_vector; 48 u32 dma_ver; 49 } __packed; 50 51 enum mrpc_status { 52 SWITCHTEC_MRPC_STATUS_INPROGRESS = 1, 53 SWITCHTEC_MRPC_STATUS_DONE = 2, 54 SWITCHTEC_MRPC_STATUS_ERROR = 0xFF, 55 SWITCHTEC_MRPC_STATUS_INTERRUPTED = 0x100, 56 }; 57 58 struct sw_event_regs { 59 u64 event_report_ctrl; 60 u64 reserved1; 61 u64 part_event_bitmap; 62 u64 reserved2; 63 u32 global_summary; 64 u32 reserved3[3]; 65 u32 stack_error_event_hdr; 66 u32 stack_error_event_data; 67 u32 reserved4[4]; 68 u32 ppu_error_event_hdr; 69 u32 ppu_error_event_data; 70 u32 reserved5[4]; 71 u32 isp_error_event_hdr; 72 u32 isp_error_event_data; 73 u32 reserved6[4]; 74 u32 sys_reset_event_hdr; 75 u32 reserved7[5]; 76 u32 fw_exception_hdr; 77 u32 reserved8[5]; 78 u32 fw_nmi_hdr; 79 u32 reserved9[5]; 80 u32 fw_non_fatal_hdr; 81 u32 reserved10[5]; 82 u32 fw_fatal_hdr; 83 u32 reserved11[5]; 84 u32 twi_mrpc_comp_hdr; 85 u32 twi_mrpc_comp_data; 86 u32 reserved12[4]; 87 u32 twi_mrpc_comp_async_hdr; 88 u32 twi_mrpc_comp_async_data; 89 u32 reserved13[4]; 90 u32 cli_mrpc_comp_hdr; 91 u32 cli_mrpc_comp_data; 92 u32 reserved14[4]; 93 u32 cli_mrpc_comp_async_hdr; 94 u32 cli_mrpc_comp_async_data; 95 u32 reserved15[4]; 96 u32 gpio_interrupt_hdr; 97 u32 gpio_interrupt_data; 98 u32 reserved16[4]; 99 u32 gfms_event_hdr; 100 u32 gfms_event_data; 101 u32 reserved17[4]; 102 } __packed; 103 104 enum { 105 SWITCHTEC_GEN3_CFG0_RUNNING = 0x04, 106 SWITCHTEC_GEN3_CFG1_RUNNING = 0x05, 107 SWITCHTEC_GEN3_IMG0_RUNNING = 0x03, 108 SWITCHTEC_GEN3_IMG1_RUNNING = 0x07, 109 }; 110 111 struct sys_info_regs_gen3 { 112 u32 reserved1; 113 u32 vendor_table_revision; 114 u32 table_format_version; 115 u32 partition_id; 116 u32 cfg_file_fmt_version; 117 u16 cfg_running; 118 u16 img_running; 119 u32 reserved2[57]; 120 char vendor_id[8]; 121 char product_id[16]; 122 char product_revision[4]; 123 char component_vendor[8]; 124 u16 component_id; 125 u8 component_revision; 126 } __packed; 127 128 struct sys_info_regs { 129 u32 device_id; 130 u32 device_version; 131 u32 firmware_version; 132 union { 133 struct sys_info_regs_gen3 gen3; 134 }; 135 } __packed; 136 137 struct partition_info { 138 u32 address; 139 u32 length; 140 }; 141 142 struct flash_info_regs_gen3 { 143 u32 flash_part_map_upd_idx; 144 145 struct active_partition_info_gen3 { 146 u32 address; 147 u32 build_version; 148 u32 build_string; 149 } active_img; 150 151 struct active_partition_info_gen3 active_cfg; 152 struct active_partition_info_gen3 inactive_img; 153 struct active_partition_info_gen3 inactive_cfg; 154 155 u32 flash_length; 156 157 struct partition_info cfg0; 158 struct partition_info cfg1; 159 struct partition_info img0; 160 struct partition_info img1; 161 struct partition_info nvlog; 162 struct partition_info vendor[8]; 163 }; 164 165 struct flash_info_regs { 166 union { 167 struct flash_info_regs_gen3 gen3; 168 }; 169 }; 170 171 enum { 172 SWITCHTEC_NTB_REG_INFO_OFFSET = 0x0000, 173 SWITCHTEC_NTB_REG_CTRL_OFFSET = 0x4000, 174 SWITCHTEC_NTB_REG_DBMSG_OFFSET = 0x64000, 175 }; 176 177 struct ntb_info_regs { 178 u8 partition_count; 179 u8 partition_id; 180 u16 reserved1; 181 u64 ep_map; 182 u16 requester_id; 183 u16 reserved2; 184 u32 reserved3[4]; 185 struct nt_partition_info { 186 u32 xlink_enabled; 187 u32 target_part_low; 188 u32 target_part_high; 189 u32 reserved; 190 } ntp_info[48]; 191 } __packed; 192 193 struct part_cfg_regs { 194 u32 status; 195 u32 state; 196 u32 port_cnt; 197 u32 usp_port_mode; 198 u32 usp_pff_inst_id; 199 u32 vep_pff_inst_id; 200 u32 dsp_pff_inst_id[47]; 201 u32 reserved1[11]; 202 u16 vep_vector_number; 203 u16 usp_vector_number; 204 u32 port_event_bitmap; 205 u32 reserved2[3]; 206 u32 part_event_summary; 207 u32 reserved3[3]; 208 u32 part_reset_hdr; 209 u32 part_reset_data[5]; 210 u32 mrpc_comp_hdr; 211 u32 mrpc_comp_data[5]; 212 u32 mrpc_comp_async_hdr; 213 u32 mrpc_comp_async_data[5]; 214 u32 dyn_binding_hdr; 215 u32 dyn_binding_data[5]; 216 u32 intercomm_notify_hdr; 217 u32 intercomm_notify_data[5]; 218 u32 reserved4[153]; 219 } __packed; 220 221 enum { 222 NTB_CTRL_PART_OP_LOCK = 0x1, 223 NTB_CTRL_PART_OP_CFG = 0x2, 224 NTB_CTRL_PART_OP_RESET = 0x3, 225 226 NTB_CTRL_PART_STATUS_NORMAL = 0x1, 227 NTB_CTRL_PART_STATUS_LOCKED = 0x2, 228 NTB_CTRL_PART_STATUS_LOCKING = 0x3, 229 NTB_CTRL_PART_STATUS_CONFIGURING = 0x4, 230 NTB_CTRL_PART_STATUS_RESETTING = 0x5, 231 232 NTB_CTRL_BAR_VALID = 1 << 0, 233 NTB_CTRL_BAR_DIR_WIN_EN = 1 << 4, 234 NTB_CTRL_BAR_LUT_WIN_EN = 1 << 5, 235 236 NTB_CTRL_REQ_ID_EN = 1 << 0, 237 238 NTB_CTRL_LUT_EN = 1 << 0, 239 240 NTB_PART_CTRL_ID_PROT_DIS = 1 << 0, 241 }; 242 243 struct ntb_ctrl_regs { 244 u32 partition_status; 245 u32 partition_op; 246 u32 partition_ctrl; 247 u32 bar_setup; 248 u32 bar_error; 249 u16 lut_table_entries; 250 u16 lut_table_offset; 251 u32 lut_error; 252 u16 req_id_table_size; 253 u16 req_id_table_offset; 254 u32 req_id_error; 255 u32 reserved1[7]; 256 struct { 257 u32 ctl; 258 u32 win_size; 259 u64 xlate_addr; 260 } bar_entry[6]; 261 struct { 262 u32 win_size; 263 u32 reserved[3]; 264 } bar_ext_entry[6]; 265 u32 reserved2[192]; 266 u32 req_id_table[512]; 267 u32 reserved3[256]; 268 u64 lut_entry[512]; 269 } __packed; 270 271 #define NTB_DBMSG_IMSG_STATUS BIT_ULL(32) 272 #define NTB_DBMSG_IMSG_MASK BIT_ULL(40) 273 274 struct ntb_dbmsg_regs { 275 u32 reserved1[1024]; 276 u64 odb; 277 u64 odb_mask; 278 u64 idb; 279 u64 idb_mask; 280 u8 idb_vec_map[64]; 281 u32 msg_map; 282 u32 reserved2; 283 struct { 284 u32 msg; 285 u32 status; 286 } omsg[4]; 287 288 struct { 289 u32 msg; 290 u8 status; 291 u8 mask; 292 u8 src; 293 u8 reserved; 294 } imsg[4]; 295 296 u8 reserved3[3928]; 297 u8 msix_table[1024]; 298 u8 reserved4[3072]; 299 u8 pba[24]; 300 u8 reserved5[4072]; 301 } __packed; 302 303 enum { 304 SWITCHTEC_PART_CFG_EVENT_RESET = 1 << 0, 305 SWITCHTEC_PART_CFG_EVENT_MRPC_CMP = 1 << 1, 306 SWITCHTEC_PART_CFG_EVENT_MRPC_ASYNC_CMP = 1 << 2, 307 SWITCHTEC_PART_CFG_EVENT_DYN_PART_CMP = 1 << 3, 308 }; 309 310 struct pff_csr_regs { 311 u16 vendor_id; 312 u16 device_id; 313 u16 pcicmd; 314 u16 pcists; 315 u32 pci_class; 316 u32 pci_opts; 317 union { 318 u32 pci_bar[6]; 319 u64 pci_bar64[3]; 320 }; 321 u32 pci_cardbus; 322 u32 pci_subsystem_id; 323 u32 pci_expansion_rom; 324 u32 pci_cap_ptr; 325 u32 reserved1; 326 u32 pci_irq; 327 u32 pci_cap_region[48]; 328 u32 pcie_cap_region[448]; 329 u32 indirect_gas_window[128]; 330 u32 indirect_gas_window_off; 331 u32 reserved[127]; 332 u32 pff_event_summary; 333 u32 reserved2[3]; 334 u32 aer_in_p2p_hdr; 335 u32 aer_in_p2p_data[5]; 336 u32 aer_in_vep_hdr; 337 u32 aer_in_vep_data[5]; 338 u32 dpc_hdr; 339 u32 dpc_data[5]; 340 u32 cts_hdr; 341 u32 cts_data[5]; 342 u32 uec_hdr; 343 u32 uec_data[5]; 344 u32 hotplug_hdr; 345 u32 hotplug_data[5]; 346 u32 ier_hdr; 347 u32 ier_data[5]; 348 u32 threshold_hdr; 349 u32 threshold_data[5]; 350 u32 power_mgmt_hdr; 351 u32 power_mgmt_data[5]; 352 u32 tlp_throttling_hdr; 353 u32 tlp_throttling_data[5]; 354 u32 force_speed_hdr; 355 u32 force_speed_data[5]; 356 u32 credit_timeout_hdr; 357 u32 credit_timeout_data[5]; 358 u32 link_state_hdr; 359 u32 link_state_data[5]; 360 u32 reserved4[174]; 361 } __packed; 362 363 struct switchtec_ntb; 364 365 struct dma_mrpc_output { 366 u32 status; 367 u32 cmd_id; 368 u32 rtn_code; 369 u32 output_size; 370 u8 data[SWITCHTEC_MRPC_PAYLOAD_SIZE]; 371 }; 372 373 struct switchtec_dev { 374 struct pci_dev *pdev; 375 struct device dev; 376 struct cdev cdev; 377 378 enum switchtec_gen gen; 379 380 int partition; 381 int partition_count; 382 int pff_csr_count; 383 char pff_local[SWITCHTEC_MAX_PFF_CSR]; 384 385 void __iomem *mmio; 386 struct mrpc_regs __iomem *mmio_mrpc; 387 struct sw_event_regs __iomem *mmio_sw_event; 388 struct sys_info_regs __iomem *mmio_sys_info; 389 struct flash_info_regs __iomem *mmio_flash_info; 390 struct ntb_info_regs __iomem *mmio_ntb; 391 struct part_cfg_regs __iomem *mmio_part_cfg; 392 struct part_cfg_regs __iomem *mmio_part_cfg_all; 393 struct pff_csr_regs __iomem *mmio_pff_csr; 394 395 /* 396 * The mrpc mutex must be held when accessing the other 397 * mrpc_ fields, alive flag and stuser->state field 398 */ 399 struct mutex mrpc_mutex; 400 struct list_head mrpc_queue; 401 int mrpc_busy; 402 struct work_struct mrpc_work; 403 struct delayed_work mrpc_timeout; 404 bool alive; 405 406 wait_queue_head_t event_wq; 407 atomic_t event_cnt; 408 409 struct work_struct link_event_work; 410 void (*link_notifier)(struct switchtec_dev *stdev); 411 u8 link_event_count[SWITCHTEC_MAX_PFF_CSR]; 412 413 struct switchtec_ntb *sndev; 414 415 struct dma_mrpc_output *dma_mrpc; 416 dma_addr_t dma_mrpc_dma_addr; 417 }; 418 419 static inline struct switchtec_dev *to_stdev(struct device *dev) 420 { 421 return container_of(dev, struct switchtec_dev, dev); 422 } 423 424 extern struct class *switchtec_class; 425 426 #endif 427