1 /* 2 * Microsemi Switchtec PCIe Driver 3 * Copyright (c) 2017, Microsemi Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 */ 15 16 #ifndef _SWITCHTEC_H 17 #define _SWITCHTEC_H 18 19 #include <linux/pci.h> 20 #include <linux/cdev.h> 21 22 #define MICROSEMI_VENDOR_ID 0x11f8 23 #define MICROSEMI_NTB_CLASSCODE 0x068000 24 #define MICROSEMI_MGMT_CLASSCODE 0x058000 25 26 #define SWITCHTEC_MRPC_PAYLOAD_SIZE 1024 27 #define SWITCHTEC_MAX_PFF_CSR 48 28 29 #define SWITCHTEC_EVENT_OCCURRED BIT(0) 30 #define SWITCHTEC_EVENT_CLEAR BIT(0) 31 #define SWITCHTEC_EVENT_EN_LOG BIT(1) 32 #define SWITCHTEC_EVENT_EN_CLI BIT(2) 33 #define SWITCHTEC_EVENT_EN_IRQ BIT(3) 34 #define SWITCHTEC_EVENT_FATAL BIT(4) 35 36 enum { 37 SWITCHTEC_GAS_MRPC_OFFSET = 0x0000, 38 SWITCHTEC_GAS_TOP_CFG_OFFSET = 0x1000, 39 SWITCHTEC_GAS_SW_EVENT_OFFSET = 0x1800, 40 SWITCHTEC_GAS_SYS_INFO_OFFSET = 0x2000, 41 SWITCHTEC_GAS_FLASH_INFO_OFFSET = 0x2200, 42 SWITCHTEC_GAS_PART_CFG_OFFSET = 0x4000, 43 SWITCHTEC_GAS_NTB_OFFSET = 0x10000, 44 SWITCHTEC_GAS_PFF_CSR_OFFSET = 0x134000, 45 }; 46 47 struct mrpc_regs { 48 u8 input_data[SWITCHTEC_MRPC_PAYLOAD_SIZE]; 49 u8 output_data[SWITCHTEC_MRPC_PAYLOAD_SIZE]; 50 u32 cmd; 51 u32 status; 52 u32 ret_value; 53 } __packed; 54 55 enum mrpc_status { 56 SWITCHTEC_MRPC_STATUS_INPROGRESS = 1, 57 SWITCHTEC_MRPC_STATUS_DONE = 2, 58 SWITCHTEC_MRPC_STATUS_ERROR = 0xFF, 59 SWITCHTEC_MRPC_STATUS_INTERRUPTED = 0x100, 60 }; 61 62 struct sw_event_regs { 63 u64 event_report_ctrl; 64 u64 reserved1; 65 u64 part_event_bitmap; 66 u64 reserved2; 67 u32 global_summary; 68 u32 reserved3[3]; 69 u32 stack_error_event_hdr; 70 u32 stack_error_event_data; 71 u32 reserved4[4]; 72 u32 ppu_error_event_hdr; 73 u32 ppu_error_event_data; 74 u32 reserved5[4]; 75 u32 isp_error_event_hdr; 76 u32 isp_error_event_data; 77 u32 reserved6[4]; 78 u32 sys_reset_event_hdr; 79 u32 reserved7[5]; 80 u32 fw_exception_hdr; 81 u32 reserved8[5]; 82 u32 fw_nmi_hdr; 83 u32 reserved9[5]; 84 u32 fw_non_fatal_hdr; 85 u32 reserved10[5]; 86 u32 fw_fatal_hdr; 87 u32 reserved11[5]; 88 u32 twi_mrpc_comp_hdr; 89 u32 twi_mrpc_comp_data; 90 u32 reserved12[4]; 91 u32 twi_mrpc_comp_async_hdr; 92 u32 twi_mrpc_comp_async_data; 93 u32 reserved13[4]; 94 u32 cli_mrpc_comp_hdr; 95 u32 cli_mrpc_comp_data; 96 u32 reserved14[4]; 97 u32 cli_mrpc_comp_async_hdr; 98 u32 cli_mrpc_comp_async_data; 99 u32 reserved15[4]; 100 u32 gpio_interrupt_hdr; 101 u32 gpio_interrupt_data; 102 u32 reserved16[4]; 103 u32 gfms_event_hdr; 104 u32 gfms_event_data; 105 u32 reserved17[4]; 106 } __packed; 107 108 enum { 109 SWITCHTEC_CFG0_RUNNING = 0x04, 110 SWITCHTEC_CFG1_RUNNING = 0x05, 111 SWITCHTEC_IMG0_RUNNING = 0x03, 112 SWITCHTEC_IMG1_RUNNING = 0x07, 113 }; 114 115 struct sys_info_regs { 116 u32 device_id; 117 u32 device_version; 118 u32 firmware_version; 119 u32 reserved1; 120 u32 vendor_table_revision; 121 u32 table_format_version; 122 u32 partition_id; 123 u32 cfg_file_fmt_version; 124 u16 cfg_running; 125 u16 img_running; 126 u32 reserved2[57]; 127 char vendor_id[8]; 128 char product_id[16]; 129 char product_revision[4]; 130 char component_vendor[8]; 131 u16 component_id; 132 u8 component_revision; 133 } __packed; 134 135 struct flash_info_regs { 136 u32 flash_part_map_upd_idx; 137 138 struct active_partition_info { 139 u32 address; 140 u32 build_version; 141 u32 build_string; 142 } active_img; 143 144 struct active_partition_info active_cfg; 145 struct active_partition_info inactive_img; 146 struct active_partition_info inactive_cfg; 147 148 u32 flash_length; 149 150 struct partition_info { 151 u32 address; 152 u32 length; 153 } cfg0; 154 155 struct partition_info cfg1; 156 struct partition_info img0; 157 struct partition_info img1; 158 struct partition_info nvlog; 159 struct partition_info vendor[8]; 160 }; 161 162 enum { 163 SWITCHTEC_NTB_REG_INFO_OFFSET = 0x0000, 164 SWITCHTEC_NTB_REG_CTRL_OFFSET = 0x4000, 165 SWITCHTEC_NTB_REG_DBMSG_OFFSET = 0x64000, 166 }; 167 168 struct ntb_info_regs { 169 u8 partition_count; 170 u8 partition_id; 171 u16 reserved1; 172 u64 ep_map; 173 u16 requester_id; 174 u16 reserved2; 175 u32 reserved3[4]; 176 struct nt_partition_info { 177 u32 xlink_enabled; 178 u32 target_part_low; 179 u32 target_part_high; 180 u32 reserved; 181 } ntp_info[48]; 182 } __packed; 183 184 struct part_cfg_regs { 185 u32 status; 186 u32 state; 187 u32 port_cnt; 188 u32 usp_port_mode; 189 u32 usp_pff_inst_id; 190 u32 vep_pff_inst_id; 191 u32 dsp_pff_inst_id[47]; 192 u32 reserved1[11]; 193 u16 vep_vector_number; 194 u16 usp_vector_number; 195 u32 port_event_bitmap; 196 u32 reserved2[3]; 197 u32 part_event_summary; 198 u32 reserved3[3]; 199 u32 part_reset_hdr; 200 u32 part_reset_data[5]; 201 u32 mrpc_comp_hdr; 202 u32 mrpc_comp_data[5]; 203 u32 mrpc_comp_async_hdr; 204 u32 mrpc_comp_async_data[5]; 205 u32 dyn_binding_hdr; 206 u32 dyn_binding_data[5]; 207 u32 reserved4[159]; 208 } __packed; 209 210 enum { 211 NTB_CTRL_PART_OP_LOCK = 0x1, 212 NTB_CTRL_PART_OP_CFG = 0x2, 213 NTB_CTRL_PART_OP_RESET = 0x3, 214 215 NTB_CTRL_PART_STATUS_NORMAL = 0x1, 216 NTB_CTRL_PART_STATUS_LOCKED = 0x2, 217 NTB_CTRL_PART_STATUS_LOCKING = 0x3, 218 NTB_CTRL_PART_STATUS_CONFIGURING = 0x4, 219 NTB_CTRL_PART_STATUS_RESETTING = 0x5, 220 221 NTB_CTRL_BAR_VALID = 1 << 0, 222 NTB_CTRL_BAR_DIR_WIN_EN = 1 << 4, 223 NTB_CTRL_BAR_LUT_WIN_EN = 1 << 5, 224 225 NTB_CTRL_REQ_ID_EN = 1 << 0, 226 227 NTB_CTRL_LUT_EN = 1 << 0, 228 229 NTB_PART_CTRL_ID_PROT_DIS = 1 << 0, 230 }; 231 232 struct ntb_ctrl_regs { 233 u32 partition_status; 234 u32 partition_op; 235 u32 partition_ctrl; 236 u32 bar_setup; 237 u32 bar_error; 238 u16 lut_table_entries; 239 u16 lut_table_offset; 240 u32 lut_error; 241 u16 req_id_table_size; 242 u16 req_id_table_offset; 243 u32 req_id_error; 244 u32 reserved1[7]; 245 struct { 246 u32 ctl; 247 u32 win_size; 248 u64 xlate_addr; 249 } bar_entry[6]; 250 u32 reserved2[216]; 251 u32 req_id_table[256]; 252 u32 reserved3[512]; 253 u64 lut_entry[512]; 254 } __packed; 255 256 #define NTB_DBMSG_IMSG_STATUS BIT_ULL(32) 257 #define NTB_DBMSG_IMSG_MASK BIT_ULL(40) 258 259 struct ntb_dbmsg_regs { 260 u32 reserved1[1024]; 261 u64 odb; 262 u64 odb_mask; 263 u64 idb; 264 u64 idb_mask; 265 u8 idb_vec_map[64]; 266 u32 msg_map; 267 u32 reserved2; 268 struct { 269 u32 msg; 270 u32 status; 271 } omsg[4]; 272 273 struct { 274 u32 msg; 275 u8 status; 276 u8 mask; 277 u8 src; 278 u8 reserved; 279 } imsg[4]; 280 281 u8 reserved3[3928]; 282 u8 msix_table[1024]; 283 u8 reserved4[3072]; 284 u8 pba[24]; 285 u8 reserved5[4072]; 286 } __packed; 287 288 enum { 289 SWITCHTEC_PART_CFG_EVENT_RESET = 1 << 0, 290 SWITCHTEC_PART_CFG_EVENT_MRPC_CMP = 1 << 1, 291 SWITCHTEC_PART_CFG_EVENT_MRPC_ASYNC_CMP = 1 << 2, 292 SWITCHTEC_PART_CFG_EVENT_DYN_PART_CMP = 1 << 3, 293 }; 294 295 struct pff_csr_regs { 296 u16 vendor_id; 297 u16 device_id; 298 u16 pcicmd; 299 u16 pcists; 300 u32 pci_class; 301 u32 pci_opts; 302 union { 303 u32 pci_bar[6]; 304 u64 pci_bar64[3]; 305 }; 306 u32 pci_cardbus; 307 u32 pci_subsystem_id; 308 u32 pci_expansion_rom; 309 u32 pci_cap_ptr; 310 u32 reserved1; 311 u32 pci_irq; 312 u32 pci_cap_region[48]; 313 u32 pcie_cap_region[448]; 314 u32 indirect_gas_window[128]; 315 u32 indirect_gas_window_off; 316 u32 reserved[127]; 317 u32 pff_event_summary; 318 u32 reserved2[3]; 319 u32 aer_in_p2p_hdr; 320 u32 aer_in_p2p_data[5]; 321 u32 aer_in_vep_hdr; 322 u32 aer_in_vep_data[5]; 323 u32 dpc_hdr; 324 u32 dpc_data[5]; 325 u32 cts_hdr; 326 u32 cts_data[5]; 327 u32 reserved3[6]; 328 u32 hotplug_hdr; 329 u32 hotplug_data[5]; 330 u32 ier_hdr; 331 u32 ier_data[5]; 332 u32 threshold_hdr; 333 u32 threshold_data[5]; 334 u32 power_mgmt_hdr; 335 u32 power_mgmt_data[5]; 336 u32 tlp_throttling_hdr; 337 u32 tlp_throttling_data[5]; 338 u32 force_speed_hdr; 339 u32 force_speed_data[5]; 340 u32 credit_timeout_hdr; 341 u32 credit_timeout_data[5]; 342 u32 link_state_hdr; 343 u32 link_state_data[5]; 344 u32 reserved4[174]; 345 } __packed; 346 347 struct switchtec_ntb; 348 349 struct switchtec_dev { 350 struct pci_dev *pdev; 351 struct device dev; 352 struct cdev cdev; 353 354 int partition; 355 int partition_count; 356 int pff_csr_count; 357 char pff_local[SWITCHTEC_MAX_PFF_CSR]; 358 359 void __iomem *mmio; 360 struct mrpc_regs __iomem *mmio_mrpc; 361 struct sw_event_regs __iomem *mmio_sw_event; 362 struct sys_info_regs __iomem *mmio_sys_info; 363 struct flash_info_regs __iomem *mmio_flash_info; 364 struct ntb_info_regs __iomem *mmio_ntb; 365 struct part_cfg_regs __iomem *mmio_part_cfg; 366 struct part_cfg_regs __iomem *mmio_part_cfg_all; 367 struct pff_csr_regs __iomem *mmio_pff_csr; 368 369 /* 370 * The mrpc mutex must be held when accessing the other 371 * mrpc_ fields, alive flag and stuser->state field 372 */ 373 struct mutex mrpc_mutex; 374 struct list_head mrpc_queue; 375 int mrpc_busy; 376 struct work_struct mrpc_work; 377 struct delayed_work mrpc_timeout; 378 bool alive; 379 380 wait_queue_head_t event_wq; 381 atomic_t event_cnt; 382 383 struct work_struct link_event_work; 384 void (*link_notifier)(struct switchtec_dev *stdev); 385 u8 link_event_count[SWITCHTEC_MAX_PFF_CSR]; 386 387 struct switchtec_ntb *sndev; 388 }; 389 390 static inline struct switchtec_dev *to_stdev(struct device *dev) 391 { 392 return container_of(dev, struct switchtec_dev, dev); 393 } 394 395 extern struct class *switchtec_class; 396 397 #endif 398