1 /* 2 * Microsemi Switchtec PCIe Driver 3 * Copyright (c) 2017, Microsemi Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 */ 15 16 #ifndef _SWITCHTEC_H 17 #define _SWITCHTEC_H 18 19 #include <linux/pci.h> 20 #include <linux/cdev.h> 21 22 #define MICROSEMI_VENDOR_ID 0x11f8 23 #define MICROSEMI_NTB_CLASSCODE 0x068000 24 #define MICROSEMI_MGMT_CLASSCODE 0x058000 25 26 #define SWITCHTEC_MRPC_PAYLOAD_SIZE 1024 27 #define SWITCHTEC_MAX_PFF_CSR 48 28 29 #define SWITCHTEC_EVENT_OCCURRED BIT(0) 30 #define SWITCHTEC_EVENT_CLEAR BIT(0) 31 #define SWITCHTEC_EVENT_EN_LOG BIT(1) 32 #define SWITCHTEC_EVENT_EN_CLI BIT(2) 33 #define SWITCHTEC_EVENT_EN_IRQ BIT(3) 34 #define SWITCHTEC_EVENT_FATAL BIT(4) 35 36 enum { 37 SWITCHTEC_GAS_MRPC_OFFSET = 0x0000, 38 SWITCHTEC_GAS_TOP_CFG_OFFSET = 0x1000, 39 SWITCHTEC_GAS_SW_EVENT_OFFSET = 0x1800, 40 SWITCHTEC_GAS_SYS_INFO_OFFSET = 0x2000, 41 SWITCHTEC_GAS_FLASH_INFO_OFFSET = 0x2200, 42 SWITCHTEC_GAS_PART_CFG_OFFSET = 0x4000, 43 SWITCHTEC_GAS_NTB_OFFSET = 0x10000, 44 SWITCHTEC_GAS_PFF_CSR_OFFSET = 0x134000, 45 }; 46 47 struct mrpc_regs { 48 u8 input_data[SWITCHTEC_MRPC_PAYLOAD_SIZE]; 49 u8 output_data[SWITCHTEC_MRPC_PAYLOAD_SIZE]; 50 u32 cmd; 51 u32 status; 52 u32 ret_value; 53 } __packed; 54 55 enum mrpc_status { 56 SWITCHTEC_MRPC_STATUS_INPROGRESS = 1, 57 SWITCHTEC_MRPC_STATUS_DONE = 2, 58 SWITCHTEC_MRPC_STATUS_ERROR = 0xFF, 59 SWITCHTEC_MRPC_STATUS_INTERRUPTED = 0x100, 60 }; 61 62 struct sw_event_regs { 63 u64 event_report_ctrl; 64 u64 reserved1; 65 u64 part_event_bitmap; 66 u64 reserved2; 67 u32 global_summary; 68 u32 reserved3[3]; 69 u32 stack_error_event_hdr; 70 u32 stack_error_event_data; 71 u32 reserved4[4]; 72 u32 ppu_error_event_hdr; 73 u32 ppu_error_event_data; 74 u32 reserved5[4]; 75 u32 isp_error_event_hdr; 76 u32 isp_error_event_data; 77 u32 reserved6[4]; 78 u32 sys_reset_event_hdr; 79 u32 reserved7[5]; 80 u32 fw_exception_hdr; 81 u32 reserved8[5]; 82 u32 fw_nmi_hdr; 83 u32 reserved9[5]; 84 u32 fw_non_fatal_hdr; 85 u32 reserved10[5]; 86 u32 fw_fatal_hdr; 87 u32 reserved11[5]; 88 u32 twi_mrpc_comp_hdr; 89 u32 twi_mrpc_comp_data; 90 u32 reserved12[4]; 91 u32 twi_mrpc_comp_async_hdr; 92 u32 twi_mrpc_comp_async_data; 93 u32 reserved13[4]; 94 u32 cli_mrpc_comp_hdr; 95 u32 cli_mrpc_comp_data; 96 u32 reserved14[4]; 97 u32 cli_mrpc_comp_async_hdr; 98 u32 cli_mrpc_comp_async_data; 99 u32 reserved15[4]; 100 u32 gpio_interrupt_hdr; 101 u32 gpio_interrupt_data; 102 u32 reserved16[4]; 103 } __packed; 104 105 enum { 106 SWITCHTEC_CFG0_RUNNING = 0x04, 107 SWITCHTEC_CFG1_RUNNING = 0x05, 108 SWITCHTEC_IMG0_RUNNING = 0x03, 109 SWITCHTEC_IMG1_RUNNING = 0x07, 110 }; 111 112 struct sys_info_regs { 113 u32 device_id; 114 u32 device_version; 115 u32 firmware_version; 116 u32 reserved1; 117 u32 vendor_table_revision; 118 u32 table_format_version; 119 u32 partition_id; 120 u32 cfg_file_fmt_version; 121 u16 cfg_running; 122 u16 img_running; 123 u32 reserved2[57]; 124 char vendor_id[8]; 125 char product_id[16]; 126 char product_revision[4]; 127 char component_vendor[8]; 128 u16 component_id; 129 u8 component_revision; 130 } __packed; 131 132 struct flash_info_regs { 133 u32 flash_part_map_upd_idx; 134 135 struct active_partition_info { 136 u32 address; 137 u32 build_version; 138 u32 build_string; 139 } active_img; 140 141 struct active_partition_info active_cfg; 142 struct active_partition_info inactive_img; 143 struct active_partition_info inactive_cfg; 144 145 u32 flash_length; 146 147 struct partition_info { 148 u32 address; 149 u32 length; 150 } cfg0; 151 152 struct partition_info cfg1; 153 struct partition_info img0; 154 struct partition_info img1; 155 struct partition_info nvlog; 156 struct partition_info vendor[8]; 157 }; 158 159 struct ntb_info_regs { 160 u8 partition_count; 161 u8 partition_id; 162 u16 reserved1; 163 u64 ep_map; 164 u16 requester_id; 165 } __packed; 166 167 struct part_cfg_regs { 168 u32 status; 169 u32 state; 170 u32 port_cnt; 171 u32 usp_port_mode; 172 u32 usp_pff_inst_id; 173 u32 vep_pff_inst_id; 174 u32 dsp_pff_inst_id[47]; 175 u32 reserved1[11]; 176 u16 vep_vector_number; 177 u16 usp_vector_number; 178 u32 port_event_bitmap; 179 u32 reserved2[3]; 180 u32 part_event_summary; 181 u32 reserved3[3]; 182 u32 part_reset_hdr; 183 u32 part_reset_data[5]; 184 u32 mrpc_comp_hdr; 185 u32 mrpc_comp_data[5]; 186 u32 mrpc_comp_async_hdr; 187 u32 mrpc_comp_async_data[5]; 188 u32 dyn_binding_hdr; 189 u32 dyn_binding_data[5]; 190 u32 reserved4[159]; 191 } __packed; 192 193 enum { 194 SWITCHTEC_PART_CFG_EVENT_RESET = 1 << 0, 195 SWITCHTEC_PART_CFG_EVENT_MRPC_CMP = 1 << 1, 196 SWITCHTEC_PART_CFG_EVENT_MRPC_ASYNC_CMP = 1 << 2, 197 SWITCHTEC_PART_CFG_EVENT_DYN_PART_CMP = 1 << 3, 198 }; 199 200 struct pff_csr_regs { 201 u16 vendor_id; 202 u16 device_id; 203 u32 pci_cfg_header[15]; 204 u32 pci_cap_region[48]; 205 u32 pcie_cap_region[448]; 206 u32 indirect_gas_window[128]; 207 u32 indirect_gas_window_off; 208 u32 reserved[127]; 209 u32 pff_event_summary; 210 u32 reserved2[3]; 211 u32 aer_in_p2p_hdr; 212 u32 aer_in_p2p_data[5]; 213 u32 aer_in_vep_hdr; 214 u32 aer_in_vep_data[5]; 215 u32 dpc_hdr; 216 u32 dpc_data[5]; 217 u32 cts_hdr; 218 u32 cts_data[5]; 219 u32 reserved3[6]; 220 u32 hotplug_hdr; 221 u32 hotplug_data[5]; 222 u32 ier_hdr; 223 u32 ier_data[5]; 224 u32 threshold_hdr; 225 u32 threshold_data[5]; 226 u32 power_mgmt_hdr; 227 u32 power_mgmt_data[5]; 228 u32 tlp_throttling_hdr; 229 u32 tlp_throttling_data[5]; 230 u32 force_speed_hdr; 231 u32 force_speed_data[5]; 232 u32 credit_timeout_hdr; 233 u32 credit_timeout_data[5]; 234 u32 link_state_hdr; 235 u32 link_state_data[5]; 236 u32 reserved4[174]; 237 } __packed; 238 239 struct switchtec_dev { 240 struct pci_dev *pdev; 241 struct device dev; 242 struct cdev cdev; 243 244 int partition; 245 int partition_count; 246 int pff_csr_count; 247 char pff_local[SWITCHTEC_MAX_PFF_CSR]; 248 249 void __iomem *mmio; 250 struct mrpc_regs __iomem *mmio_mrpc; 251 struct sw_event_regs __iomem *mmio_sw_event; 252 struct sys_info_regs __iomem *mmio_sys_info; 253 struct flash_info_regs __iomem *mmio_flash_info; 254 struct ntb_info_regs __iomem *mmio_ntb; 255 struct part_cfg_regs __iomem *mmio_part_cfg; 256 struct part_cfg_regs __iomem *mmio_part_cfg_all; 257 struct pff_csr_regs __iomem *mmio_pff_csr; 258 259 /* 260 * The mrpc mutex must be held when accessing the other 261 * mrpc_ fields, alive flag and stuser->state field 262 */ 263 struct mutex mrpc_mutex; 264 struct list_head mrpc_queue; 265 int mrpc_busy; 266 struct work_struct mrpc_work; 267 struct delayed_work mrpc_timeout; 268 bool alive; 269 270 wait_queue_head_t event_wq; 271 atomic_t event_cnt; 272 }; 273 274 static inline struct switchtec_dev *to_stdev(struct device *dev) 275 { 276 return container_of(dev, struct switchtec_dev, dev); 277 } 278 279 extern struct class *switchtec_class; 280 281 #endif 282