1 /* SPDX-License-Identifier: GPL-2.0-or-later 2 * 3 * Copyright (C) 2005 David Brownell 4 */ 5 6 #ifndef __LINUX_SPI_H 7 #define __LINUX_SPI_H 8 9 #include <linux/bits.h> 10 #include <linux/device.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/slab.h> 13 #include <linux/kthread.h> 14 #include <linux/completion.h> 15 #include <linux/scatterlist.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/ptp_clock_kernel.h> 18 19 #include <uapi/linux/spi/spi.h> 20 21 struct dma_chan; 22 struct software_node; 23 struct spi_controller; 24 struct spi_transfer; 25 struct spi_controller_mem_ops; 26 27 /* 28 * INTERFACES between SPI master-side drivers and SPI slave protocol handlers, 29 * and SPI infrastructure. 30 */ 31 extern struct bus_type spi_bus_type; 32 33 /** 34 * struct spi_statistics - statistics for spi transfers 35 * @lock: lock protecting this structure 36 * 37 * @messages: number of spi-messages handled 38 * @transfers: number of spi_transfers handled 39 * @errors: number of errors during spi_transfer 40 * @timedout: number of timeouts during spi_transfer 41 * 42 * @spi_sync: number of times spi_sync is used 43 * @spi_sync_immediate: 44 * number of times spi_sync is executed immediately 45 * in calling context without queuing and scheduling 46 * @spi_async: number of times spi_async is used 47 * 48 * @bytes: number of bytes transferred to/from device 49 * @bytes_tx: number of bytes sent to device 50 * @bytes_rx: number of bytes received from device 51 * 52 * @transfer_bytes_histo: 53 * transfer bytes histogramm 54 * 55 * @transfers_split_maxsize: 56 * number of transfers that have been split because of 57 * maxsize limit 58 */ 59 struct spi_statistics { 60 spinlock_t lock; /* lock for the whole structure */ 61 62 unsigned long messages; 63 unsigned long transfers; 64 unsigned long errors; 65 unsigned long timedout; 66 67 unsigned long spi_sync; 68 unsigned long spi_sync_immediate; 69 unsigned long spi_async; 70 71 unsigned long long bytes; 72 unsigned long long bytes_rx; 73 unsigned long long bytes_tx; 74 75 #define SPI_STATISTICS_HISTO_SIZE 17 76 unsigned long transfer_bytes_histo[SPI_STATISTICS_HISTO_SIZE]; 77 78 unsigned long transfers_split_maxsize; 79 }; 80 81 void spi_statistics_add_transfer_stats(struct spi_statistics *stats, 82 struct spi_transfer *xfer, 83 struct spi_controller *ctlr); 84 85 #define SPI_STATISTICS_ADD_TO_FIELD(stats, field, count) \ 86 do { \ 87 unsigned long flags; \ 88 spin_lock_irqsave(&(stats)->lock, flags); \ 89 (stats)->field += count; \ 90 spin_unlock_irqrestore(&(stats)->lock, flags); \ 91 } while (0) 92 93 #define SPI_STATISTICS_INCREMENT_FIELD(stats, field) \ 94 SPI_STATISTICS_ADD_TO_FIELD(stats, field, 1) 95 96 /** 97 * struct spi_delay - SPI delay information 98 * @value: Value for the delay 99 * @unit: Unit for the delay 100 */ 101 struct spi_delay { 102 #define SPI_DELAY_UNIT_USECS 0 103 #define SPI_DELAY_UNIT_NSECS 1 104 #define SPI_DELAY_UNIT_SCK 2 105 u16 value; 106 u8 unit; 107 }; 108 109 extern int spi_delay_to_ns(struct spi_delay *_delay, struct spi_transfer *xfer); 110 extern int spi_delay_exec(struct spi_delay *_delay, struct spi_transfer *xfer); 111 112 /** 113 * struct spi_device - Controller side proxy for an SPI slave device 114 * @dev: Driver model representation of the device. 115 * @controller: SPI controller used with the device. 116 * @master: Copy of controller, for backwards compatibility. 117 * @max_speed_hz: Maximum clock rate to be used with this chip 118 * (on this board); may be changed by the device's driver. 119 * The spi_transfer.speed_hz can override this for each transfer. 120 * @chip_select: Chipselect, distinguishing chips handled by @controller. 121 * @mode: The spi mode defines how data is clocked out and in. 122 * This may be changed by the device's driver. 123 * The "active low" default for chipselect mode can be overridden 124 * (by specifying SPI_CS_HIGH) as can the "MSB first" default for 125 * each word in a transfer (by specifying SPI_LSB_FIRST). 126 * @bits_per_word: Data transfers involve one or more words; word sizes 127 * like eight or 12 bits are common. In-memory wordsizes are 128 * powers of two bytes (e.g. 20 bit samples use 32 bits). 129 * This may be changed by the device's driver, or left at the 130 * default (0) indicating protocol words are eight bit bytes. 131 * The spi_transfer.bits_per_word can override this for each transfer. 132 * @rt: Make the pump thread real time priority. 133 * @irq: Negative, or the number passed to request_irq() to receive 134 * interrupts from this device. 135 * @controller_state: Controller's runtime state 136 * @controller_data: Board-specific definitions for controller, such as 137 * FIFO initialization parameters; from board_info.controller_data 138 * @modalias: Name of the driver to use with this device, or an alias 139 * for that name. This appears in the sysfs "modalias" attribute 140 * for driver coldplugging, and in uevents used for hotplugging 141 * @driver_override: If the name of a driver is written to this attribute, then 142 * the device will bind to the named driver and only the named driver. 143 * @cs_gpio: LEGACY: gpio number of the chipselect line (optional, -ENOENT when 144 * not using a GPIO line) use cs_gpiod in new drivers by opting in on 145 * the spi_master. 146 * @cs_gpiod: gpio descriptor of the chipselect line (optional, NULL when 147 * not using a GPIO line) 148 * @word_delay: delay to be inserted between consecutive 149 * words of a transfer 150 * @cs_setup: delay to be introduced by the controller after CS is asserted 151 * @cs_hold: delay to be introduced by the controller before CS is deasserted 152 * @cs_inactive: delay to be introduced by the controller after CS is 153 * deasserted. If @cs_change_delay is used from @spi_transfer, then the 154 * two delays will be added up. 155 * @statistics: statistics for the spi_device 156 * 157 * A @spi_device is used to interchange data between an SPI slave 158 * (usually a discrete chip) and CPU memory. 159 * 160 * In @dev, the platform_data is used to hold information about this 161 * device that's meaningful to the device's protocol driver, but not 162 * to its controller. One example might be an identifier for a chip 163 * variant with slightly different functionality; another might be 164 * information about how this particular board wires the chip's pins. 165 */ 166 struct spi_device { 167 struct device dev; 168 struct spi_controller *controller; 169 struct spi_controller *master; /* compatibility layer */ 170 u32 max_speed_hz; 171 u8 chip_select; 172 u8 bits_per_word; 173 bool rt; 174 #define SPI_NO_TX BIT(31) /* no transmit wire */ 175 #define SPI_NO_RX BIT(30) /* no receive wire */ 176 /* 177 * All bits defined above should be covered by SPI_MODE_KERNEL_MASK. 178 * The SPI_MODE_KERNEL_MASK has the SPI_MODE_USER_MASK counterpart, 179 * which is defined in 'include/uapi/linux/spi/spi.h'. 180 * The bits defined here are from bit 31 downwards, while in 181 * SPI_MODE_USER_MASK are from 0 upwards. 182 * These bits must not overlap. A static assert check should make sure of that. 183 * If adding extra bits, make sure to decrease the bit index below as well. 184 */ 185 #define SPI_MODE_KERNEL_MASK (~(BIT(30) - 1)) 186 u32 mode; 187 int irq; 188 void *controller_state; 189 void *controller_data; 190 char modalias[SPI_NAME_SIZE]; 191 const char *driver_override; 192 int cs_gpio; /* LEGACY: chip select gpio */ 193 struct gpio_desc *cs_gpiod; /* chip select gpio desc */ 194 struct spi_delay word_delay; /* inter-word delay */ 195 /* CS delays */ 196 struct spi_delay cs_setup; 197 struct spi_delay cs_hold; 198 struct spi_delay cs_inactive; 199 200 /* the statistics */ 201 struct spi_statistics statistics; 202 203 /* 204 * likely need more hooks for more protocol options affecting how 205 * the controller talks to each chip, like: 206 * - memory packing (12 bit samples into low bits, others zeroed) 207 * - priority 208 * - chipselect delays 209 * - ... 210 */ 211 }; 212 213 /* Make sure that SPI_MODE_KERNEL_MASK & SPI_MODE_USER_MASK don't overlap */ 214 static_assert((SPI_MODE_KERNEL_MASK & SPI_MODE_USER_MASK) == 0, 215 "SPI_MODE_USER_MASK & SPI_MODE_KERNEL_MASK must not overlap"); 216 217 static inline struct spi_device *to_spi_device(struct device *dev) 218 { 219 return dev ? container_of(dev, struct spi_device, dev) : NULL; 220 } 221 222 /* most drivers won't need to care about device refcounting */ 223 static inline struct spi_device *spi_dev_get(struct spi_device *spi) 224 { 225 return (spi && get_device(&spi->dev)) ? spi : NULL; 226 } 227 228 static inline void spi_dev_put(struct spi_device *spi) 229 { 230 if (spi) 231 put_device(&spi->dev); 232 } 233 234 /* ctldata is for the bus_controller driver's runtime state */ 235 static inline void *spi_get_ctldata(struct spi_device *spi) 236 { 237 return spi->controller_state; 238 } 239 240 static inline void spi_set_ctldata(struct spi_device *spi, void *state) 241 { 242 spi->controller_state = state; 243 } 244 245 /* device driver data */ 246 247 static inline void spi_set_drvdata(struct spi_device *spi, void *data) 248 { 249 dev_set_drvdata(&spi->dev, data); 250 } 251 252 static inline void *spi_get_drvdata(struct spi_device *spi) 253 { 254 return dev_get_drvdata(&spi->dev); 255 } 256 257 struct spi_message; 258 259 /** 260 * struct spi_driver - Host side "protocol" driver 261 * @id_table: List of SPI devices supported by this driver 262 * @probe: Binds this driver to the spi device. Drivers can verify 263 * that the device is actually present, and may need to configure 264 * characteristics (such as bits_per_word) which weren't needed for 265 * the initial configuration done during system setup. 266 * @remove: Unbinds this driver from the spi device 267 * @shutdown: Standard shutdown callback used during system state 268 * transitions such as powerdown/halt and kexec 269 * @driver: SPI device drivers should initialize the name and owner 270 * field of this structure. 271 * 272 * This represents the kind of device driver that uses SPI messages to 273 * interact with the hardware at the other end of a SPI link. It's called 274 * a "protocol" driver because it works through messages rather than talking 275 * directly to SPI hardware (which is what the underlying SPI controller 276 * driver does to pass those messages). These protocols are defined in the 277 * specification for the device(s) supported by the driver. 278 * 279 * As a rule, those device protocols represent the lowest level interface 280 * supported by a driver, and it will support upper level interfaces too. 281 * Examples of such upper levels include frameworks like MTD, networking, 282 * MMC, RTC, filesystem character device nodes, and hardware monitoring. 283 */ 284 struct spi_driver { 285 const struct spi_device_id *id_table; 286 int (*probe)(struct spi_device *spi); 287 int (*remove)(struct spi_device *spi); 288 void (*shutdown)(struct spi_device *spi); 289 struct device_driver driver; 290 }; 291 292 static inline struct spi_driver *to_spi_driver(struct device_driver *drv) 293 { 294 return drv ? container_of(drv, struct spi_driver, driver) : NULL; 295 } 296 297 extern int __spi_register_driver(struct module *owner, struct spi_driver *sdrv); 298 299 /** 300 * spi_unregister_driver - reverse effect of spi_register_driver 301 * @sdrv: the driver to unregister 302 * Context: can sleep 303 */ 304 static inline void spi_unregister_driver(struct spi_driver *sdrv) 305 { 306 if (sdrv) 307 driver_unregister(&sdrv->driver); 308 } 309 310 extern struct spi_device *spi_new_ancillary_device(struct spi_device *spi, u8 chip_select); 311 312 /* use a define to avoid include chaining to get THIS_MODULE */ 313 #define spi_register_driver(driver) \ 314 __spi_register_driver(THIS_MODULE, driver) 315 316 /** 317 * module_spi_driver() - Helper macro for registering a SPI driver 318 * @__spi_driver: spi_driver struct 319 * 320 * Helper macro for SPI drivers which do not do anything special in module 321 * init/exit. This eliminates a lot of boilerplate. Each module may only 322 * use this macro once, and calling it replaces module_init() and module_exit() 323 */ 324 #define module_spi_driver(__spi_driver) \ 325 module_driver(__spi_driver, spi_register_driver, \ 326 spi_unregister_driver) 327 328 /** 329 * struct spi_controller - interface to SPI master or slave controller 330 * @dev: device interface to this driver 331 * @list: link with the global spi_controller list 332 * @bus_num: board-specific (and often SOC-specific) identifier for a 333 * given SPI controller. 334 * @num_chipselect: chipselects are used to distinguish individual 335 * SPI slaves, and are numbered from zero to num_chipselects. 336 * each slave has a chipselect signal, but it's common that not 337 * every chipselect is connected to a slave. 338 * @dma_alignment: SPI controller constraint on DMA buffers alignment. 339 * @mode_bits: flags understood by this controller driver 340 * @buswidth_override_bits: flags to override for this controller driver 341 * @bits_per_word_mask: A mask indicating which values of bits_per_word are 342 * supported by the driver. Bit n indicates that a bits_per_word n+1 is 343 * supported. If set, the SPI core will reject any transfer with an 344 * unsupported bits_per_word. If not set, this value is simply ignored, 345 * and it's up to the individual driver to perform any validation. 346 * @min_speed_hz: Lowest supported transfer speed 347 * @max_speed_hz: Highest supported transfer speed 348 * @flags: other constraints relevant to this driver 349 * @slave: indicates that this is an SPI slave controller 350 * @devm_allocated: whether the allocation of this struct is devres-managed 351 * @max_transfer_size: function that returns the max transfer size for 352 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used. 353 * @max_message_size: function that returns the max message size for 354 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used. 355 * @io_mutex: mutex for physical bus access 356 * @bus_lock_spinlock: spinlock for SPI bus locking 357 * @bus_lock_mutex: mutex for exclusion of multiple callers 358 * @bus_lock_flag: indicates that the SPI bus is locked for exclusive use 359 * @setup: updates the device mode and clocking records used by a 360 * device's SPI controller; protocol code may call this. This 361 * must fail if an unrecognized or unsupported mode is requested. 362 * It's always safe to call this unless transfers are pending on 363 * the device whose settings are being modified. 364 * @set_cs_timing: optional hook for SPI devices to request SPI master 365 * controller for configuring specific CS setup time, hold time and inactive 366 * delay interms of clock counts 367 * @transfer: adds a message to the controller's transfer queue. 368 * @cleanup: frees controller-specific state 369 * @can_dma: determine whether this controller supports DMA 370 * @queued: whether this controller is providing an internal message queue 371 * @kworker: pointer to thread struct for message pump 372 * @pump_messages: work struct for scheduling work to the message pump 373 * @queue_lock: spinlock to syncronise access to message queue 374 * @queue: message queue 375 * @idling: the device is entering idle state 376 * @cur_msg: the currently in-flight message 377 * @cur_msg_prepared: spi_prepare_message was called for the currently 378 * in-flight message 379 * @cur_msg_mapped: message has been mapped for DMA 380 * @last_cs_enable: was enable true on the last call to set_cs. 381 * @last_cs_mode_high: was (mode & SPI_CS_HIGH) true on the last call to set_cs. 382 * @xfer_completion: used by core transfer_one_message() 383 * @busy: message pump is busy 384 * @running: message pump is running 385 * @rt: whether this queue is set to run as a realtime task 386 * @auto_runtime_pm: the core should ensure a runtime PM reference is held 387 * while the hardware is prepared, using the parent 388 * device for the spidev 389 * @max_dma_len: Maximum length of a DMA transfer for the device. 390 * @prepare_transfer_hardware: a message will soon arrive from the queue 391 * so the subsystem requests the driver to prepare the transfer hardware 392 * by issuing this call 393 * @transfer_one_message: the subsystem calls the driver to transfer a single 394 * message while queuing transfers that arrive in the meantime. When the 395 * driver is finished with this message, it must call 396 * spi_finalize_current_message() so the subsystem can issue the next 397 * message 398 * @unprepare_transfer_hardware: there are currently no more messages on the 399 * queue so the subsystem notifies the driver that it may relax the 400 * hardware by issuing this call 401 * 402 * @set_cs: set the logic level of the chip select line. May be called 403 * from interrupt context. 404 * @prepare_message: set up the controller to transfer a single message, 405 * for example doing DMA mapping. Called from threaded 406 * context. 407 * @transfer_one: transfer a single spi_transfer. 408 * 409 * - return 0 if the transfer is finished, 410 * - return 1 if the transfer is still in progress. When 411 * the driver is finished with this transfer it must 412 * call spi_finalize_current_transfer() so the subsystem 413 * can issue the next transfer. Note: transfer_one and 414 * transfer_one_message are mutually exclusive; when both 415 * are set, the generic subsystem does not call your 416 * transfer_one callback. 417 * @handle_err: the subsystem calls the driver to handle an error that occurs 418 * in the generic implementation of transfer_one_message(). 419 * @mem_ops: optimized/dedicated operations for interactions with SPI memory. 420 * This field is optional and should only be implemented if the 421 * controller has native support for memory like operations. 422 * @unprepare_message: undo any work done by prepare_message(). 423 * @slave_abort: abort the ongoing transfer request on an SPI slave controller 424 * @cs_gpios: LEGACY: array of GPIO descs to use as chip select lines; one per 425 * CS number. Any individual value may be -ENOENT for CS lines that 426 * are not GPIOs (driven by the SPI controller itself). Use the cs_gpiods 427 * in new drivers. 428 * @cs_gpiods: Array of GPIO descs to use as chip select lines; one per CS 429 * number. Any individual value may be NULL for CS lines that 430 * are not GPIOs (driven by the SPI controller itself). 431 * @use_gpio_descriptors: Turns on the code in the SPI core to parse and grab 432 * GPIO descriptors rather than using global GPIO numbers grabbed by the 433 * driver. This will fill in @cs_gpiods and @cs_gpios should not be used, 434 * and SPI devices will have the cs_gpiod assigned rather than cs_gpio. 435 * @unused_native_cs: When cs_gpiods is used, spi_register_controller() will 436 * fill in this field with the first unused native CS, to be used by SPI 437 * controller drivers that need to drive a native CS when using GPIO CS. 438 * @max_native_cs: When cs_gpiods is used, and this field is filled in, 439 * spi_register_controller() will validate all native CS (including the 440 * unused native CS) against this value. 441 * @statistics: statistics for the spi_controller 442 * @dma_tx: DMA transmit channel 443 * @dma_rx: DMA receive channel 444 * @dummy_rx: dummy receive buffer for full-duplex devices 445 * @dummy_tx: dummy transmit buffer for full-duplex devices 446 * @fw_translate_cs: If the boot firmware uses different numbering scheme 447 * what Linux expects, this optional hook can be used to translate 448 * between the two. 449 * @ptp_sts_supported: If the driver sets this to true, it must provide a 450 * time snapshot in @spi_transfer->ptp_sts as close as possible to the 451 * moment in time when @spi_transfer->ptp_sts_word_pre and 452 * @spi_transfer->ptp_sts_word_post were transmitted. 453 * If the driver does not set this, the SPI core takes the snapshot as 454 * close to the driver hand-over as possible. 455 * @irq_flags: Interrupt enable state during PTP system timestamping 456 * @fallback: fallback to pio if dma transfer return failure with 457 * SPI_TRANS_FAIL_NO_START. 458 * 459 * Each SPI controller can communicate with one or more @spi_device 460 * children. These make a small bus, sharing MOSI, MISO and SCK signals 461 * but not chip select signals. Each device may be configured to use a 462 * different clock rate, since those shared signals are ignored unless 463 * the chip is selected. 464 * 465 * The driver for an SPI controller manages access to those devices through 466 * a queue of spi_message transactions, copying data between CPU memory and 467 * an SPI slave device. For each such message it queues, it calls the 468 * message's completion function when the transaction completes. 469 */ 470 struct spi_controller { 471 struct device dev; 472 473 struct list_head list; 474 475 /* other than negative (== assign one dynamically), bus_num is fully 476 * board-specific. usually that simplifies to being SOC-specific. 477 * example: one SOC has three SPI controllers, numbered 0..2, 478 * and one board's schematics might show it using SPI-2. software 479 * would normally use bus_num=2 for that controller. 480 */ 481 s16 bus_num; 482 483 /* chipselects will be integral to many controllers; some others 484 * might use board-specific GPIOs. 485 */ 486 u16 num_chipselect; 487 488 /* some SPI controllers pose alignment requirements on DMAable 489 * buffers; let protocol drivers know about these requirements. 490 */ 491 u16 dma_alignment; 492 493 /* spi_device.mode flags understood by this controller driver */ 494 u32 mode_bits; 495 496 /* spi_device.mode flags override flags for this controller */ 497 u32 buswidth_override_bits; 498 499 /* bitmask of supported bits_per_word for transfers */ 500 u32 bits_per_word_mask; 501 #define SPI_BPW_MASK(bits) BIT((bits) - 1) 502 #define SPI_BPW_RANGE_MASK(min, max) GENMASK((max) - 1, (min) - 1) 503 504 /* limits on transfer speed */ 505 u32 min_speed_hz; 506 u32 max_speed_hz; 507 508 /* other constraints relevant to this driver */ 509 u16 flags; 510 #define SPI_CONTROLLER_HALF_DUPLEX BIT(0) /* can't do full duplex */ 511 #define SPI_CONTROLLER_NO_RX BIT(1) /* can't do buffer read */ 512 #define SPI_CONTROLLER_NO_TX BIT(2) /* can't do buffer write */ 513 #define SPI_CONTROLLER_MUST_RX BIT(3) /* requires rx */ 514 #define SPI_CONTROLLER_MUST_TX BIT(4) /* requires tx */ 515 516 #define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS must select slave */ 517 518 /* flag indicating if the allocation of this struct is devres-managed */ 519 bool devm_allocated; 520 521 /* flag indicating this is an SPI slave controller */ 522 bool slave; 523 524 /* 525 * on some hardware transfer / message size may be constrained 526 * the limit may depend on device transfer settings 527 */ 528 size_t (*max_transfer_size)(struct spi_device *spi); 529 size_t (*max_message_size)(struct spi_device *spi); 530 531 /* I/O mutex */ 532 struct mutex io_mutex; 533 534 /* lock and mutex for SPI bus locking */ 535 spinlock_t bus_lock_spinlock; 536 struct mutex bus_lock_mutex; 537 538 /* flag indicating that the SPI bus is locked for exclusive use */ 539 bool bus_lock_flag; 540 541 /* Setup mode and clock, etc (spi driver may call many times). 542 * 543 * IMPORTANT: this may be called when transfers to another 544 * device are active. DO NOT UPDATE SHARED REGISTERS in ways 545 * which could break those transfers. 546 */ 547 int (*setup)(struct spi_device *spi); 548 549 /* 550 * set_cs_timing() method is for SPI controllers that supports 551 * configuring CS timing. 552 * 553 * This hook allows SPI client drivers to request SPI controllers 554 * to configure specific CS timing through spi_set_cs_timing() after 555 * spi_setup(). 556 */ 557 int (*set_cs_timing)(struct spi_device *spi); 558 559 /* bidirectional bulk transfers 560 * 561 * + The transfer() method may not sleep; its main role is 562 * just to add the message to the queue. 563 * + For now there's no remove-from-queue operation, or 564 * any other request management 565 * + To a given spi_device, message queueing is pure fifo 566 * 567 * + The controller's main job is to process its message queue, 568 * selecting a chip (for masters), then transferring data 569 * + If there are multiple spi_device children, the i/o queue 570 * arbitration algorithm is unspecified (round robin, fifo, 571 * priority, reservations, preemption, etc) 572 * 573 * + Chipselect stays active during the entire message 574 * (unless modified by spi_transfer.cs_change != 0). 575 * + The message transfers use clock and SPI mode parameters 576 * previously established by setup() for this device 577 */ 578 int (*transfer)(struct spi_device *spi, 579 struct spi_message *mesg); 580 581 /* called on release() to free memory provided by spi_controller */ 582 void (*cleanup)(struct spi_device *spi); 583 584 /* 585 * Used to enable core support for DMA handling, if can_dma() 586 * exists and returns true then the transfer will be mapped 587 * prior to transfer_one() being called. The driver should 588 * not modify or store xfer and dma_tx and dma_rx must be set 589 * while the device is prepared. 590 */ 591 bool (*can_dma)(struct spi_controller *ctlr, 592 struct spi_device *spi, 593 struct spi_transfer *xfer); 594 struct device *dma_map_dev; 595 596 /* 597 * These hooks are for drivers that want to use the generic 598 * controller transfer queueing mechanism. If these are used, the 599 * transfer() function above must NOT be specified by the driver. 600 * Over time we expect SPI drivers to be phased over to this API. 601 */ 602 bool queued; 603 struct kthread_worker *kworker; 604 struct kthread_work pump_messages; 605 spinlock_t queue_lock; 606 struct list_head queue; 607 struct spi_message *cur_msg; 608 bool idling; 609 bool busy; 610 bool running; 611 bool rt; 612 bool auto_runtime_pm; 613 bool cur_msg_prepared; 614 bool cur_msg_mapped; 615 bool last_cs_enable; 616 bool last_cs_mode_high; 617 bool fallback; 618 struct completion xfer_completion; 619 size_t max_dma_len; 620 621 int (*prepare_transfer_hardware)(struct spi_controller *ctlr); 622 int (*transfer_one_message)(struct spi_controller *ctlr, 623 struct spi_message *mesg); 624 int (*unprepare_transfer_hardware)(struct spi_controller *ctlr); 625 int (*prepare_message)(struct spi_controller *ctlr, 626 struct spi_message *message); 627 int (*unprepare_message)(struct spi_controller *ctlr, 628 struct spi_message *message); 629 int (*slave_abort)(struct spi_controller *ctlr); 630 631 /* 632 * These hooks are for drivers that use a generic implementation 633 * of transfer_one_message() provided by the core. 634 */ 635 void (*set_cs)(struct spi_device *spi, bool enable); 636 int (*transfer_one)(struct spi_controller *ctlr, struct spi_device *spi, 637 struct spi_transfer *transfer); 638 void (*handle_err)(struct spi_controller *ctlr, 639 struct spi_message *message); 640 641 /* Optimized handlers for SPI memory-like operations. */ 642 const struct spi_controller_mem_ops *mem_ops; 643 644 /* gpio chip select */ 645 int *cs_gpios; 646 struct gpio_desc **cs_gpiods; 647 bool use_gpio_descriptors; 648 s8 unused_native_cs; 649 s8 max_native_cs; 650 651 /* statistics */ 652 struct spi_statistics statistics; 653 654 /* DMA channels for use with core dmaengine helpers */ 655 struct dma_chan *dma_tx; 656 struct dma_chan *dma_rx; 657 658 /* dummy data for full duplex devices */ 659 void *dummy_rx; 660 void *dummy_tx; 661 662 int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs); 663 664 /* 665 * Driver sets this field to indicate it is able to snapshot SPI 666 * transfers (needed e.g. for reading the time of POSIX clocks) 667 */ 668 bool ptp_sts_supported; 669 670 /* Interrupt enable state during PTP system timestamping */ 671 unsigned long irq_flags; 672 }; 673 674 static inline void *spi_controller_get_devdata(struct spi_controller *ctlr) 675 { 676 return dev_get_drvdata(&ctlr->dev); 677 } 678 679 static inline void spi_controller_set_devdata(struct spi_controller *ctlr, 680 void *data) 681 { 682 dev_set_drvdata(&ctlr->dev, data); 683 } 684 685 static inline struct spi_controller *spi_controller_get(struct spi_controller *ctlr) 686 { 687 if (!ctlr || !get_device(&ctlr->dev)) 688 return NULL; 689 return ctlr; 690 } 691 692 static inline void spi_controller_put(struct spi_controller *ctlr) 693 { 694 if (ctlr) 695 put_device(&ctlr->dev); 696 } 697 698 static inline bool spi_controller_is_slave(struct spi_controller *ctlr) 699 { 700 return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->slave; 701 } 702 703 /* PM calls that need to be issued by the driver */ 704 extern int spi_controller_suspend(struct spi_controller *ctlr); 705 extern int spi_controller_resume(struct spi_controller *ctlr); 706 707 /* Calls the driver make to interact with the message queue */ 708 extern struct spi_message *spi_get_next_queued_message(struct spi_controller *ctlr); 709 extern void spi_finalize_current_message(struct spi_controller *ctlr); 710 extern void spi_finalize_current_transfer(struct spi_controller *ctlr); 711 712 /* Helper calls for driver to timestamp transfer */ 713 void spi_take_timestamp_pre(struct spi_controller *ctlr, 714 struct spi_transfer *xfer, 715 size_t progress, bool irqs_off); 716 void spi_take_timestamp_post(struct spi_controller *ctlr, 717 struct spi_transfer *xfer, 718 size_t progress, bool irqs_off); 719 720 /* the spi driver core manages memory for the spi_controller classdev */ 721 extern struct spi_controller *__spi_alloc_controller(struct device *host, 722 unsigned int size, bool slave); 723 724 static inline struct spi_controller *spi_alloc_master(struct device *host, 725 unsigned int size) 726 { 727 return __spi_alloc_controller(host, size, false); 728 } 729 730 static inline struct spi_controller *spi_alloc_slave(struct device *host, 731 unsigned int size) 732 { 733 if (!IS_ENABLED(CONFIG_SPI_SLAVE)) 734 return NULL; 735 736 return __spi_alloc_controller(host, size, true); 737 } 738 739 struct spi_controller *__devm_spi_alloc_controller(struct device *dev, 740 unsigned int size, 741 bool slave); 742 743 static inline struct spi_controller *devm_spi_alloc_master(struct device *dev, 744 unsigned int size) 745 { 746 return __devm_spi_alloc_controller(dev, size, false); 747 } 748 749 static inline struct spi_controller *devm_spi_alloc_slave(struct device *dev, 750 unsigned int size) 751 { 752 if (!IS_ENABLED(CONFIG_SPI_SLAVE)) 753 return NULL; 754 755 return __devm_spi_alloc_controller(dev, size, true); 756 } 757 758 extern int spi_register_controller(struct spi_controller *ctlr); 759 extern int devm_spi_register_controller(struct device *dev, 760 struct spi_controller *ctlr); 761 extern void spi_unregister_controller(struct spi_controller *ctlr); 762 763 extern struct spi_controller *spi_busnum_to_master(u16 busnum); 764 765 /* 766 * SPI resource management while processing a SPI message 767 */ 768 769 typedef void (*spi_res_release_t)(struct spi_controller *ctlr, 770 struct spi_message *msg, 771 void *res); 772 773 /** 774 * struct spi_res - spi resource management structure 775 * @entry: list entry 776 * @release: release code called prior to freeing this resource 777 * @data: extra data allocated for the specific use-case 778 * 779 * this is based on ideas from devres, but focused on life-cycle 780 * management during spi_message processing 781 */ 782 struct spi_res { 783 struct list_head entry; 784 spi_res_release_t release; 785 unsigned long long data[]; /* guarantee ull alignment */ 786 }; 787 788 extern void *spi_res_alloc(struct spi_device *spi, 789 spi_res_release_t release, 790 size_t size, gfp_t gfp); 791 extern void spi_res_add(struct spi_message *message, void *res); 792 extern void spi_res_free(void *res); 793 794 extern void spi_res_release(struct spi_controller *ctlr, 795 struct spi_message *message); 796 797 /*---------------------------------------------------------------------------*/ 798 799 /* 800 * I/O INTERFACE between SPI controller and protocol drivers 801 * 802 * Protocol drivers use a queue of spi_messages, each transferring data 803 * between the controller and memory buffers. 804 * 805 * The spi_messages themselves consist of a series of read+write transfer 806 * segments. Those segments always read the same number of bits as they 807 * write; but one or the other is easily ignored by passing a null buffer 808 * pointer. (This is unlike most types of I/O API, because SPI hardware 809 * is full duplex.) 810 * 811 * NOTE: Allocation of spi_transfer and spi_message memory is entirely 812 * up to the protocol driver, which guarantees the integrity of both (as 813 * well as the data buffers) for as long as the message is queued. 814 */ 815 816 /** 817 * struct spi_transfer - a read/write buffer pair 818 * @tx_buf: data to be written (dma-safe memory), or NULL 819 * @rx_buf: data to be read (dma-safe memory), or NULL 820 * @tx_dma: DMA address of tx_buf, if @spi_message.is_dma_mapped 821 * @rx_dma: DMA address of rx_buf, if @spi_message.is_dma_mapped 822 * @tx_nbits: number of bits used for writing. If 0 the default 823 * (SPI_NBITS_SINGLE) is used. 824 * @rx_nbits: number of bits used for reading. If 0 the default 825 * (SPI_NBITS_SINGLE) is used. 826 * @len: size of rx and tx buffers (in bytes) 827 * @speed_hz: Select a speed other than the device default for this 828 * transfer. If 0 the default (from @spi_device) is used. 829 * @bits_per_word: select a bits_per_word other than the device default 830 * for this transfer. If 0 the default (from @spi_device) is used. 831 * @dummy_data: indicates transfer is dummy bytes transfer. 832 * @cs_change: affects chipselect after this transfer completes 833 * @cs_change_delay: delay between cs deassert and assert when 834 * @cs_change is set and @spi_transfer is not the last in @spi_message 835 * @delay: delay to be introduced after this transfer before 836 * (optionally) changing the chipselect status, then starting 837 * the next transfer or completing this @spi_message. 838 * @word_delay: inter word delay to be introduced after each word size 839 * (set by bits_per_word) transmission. 840 * @effective_speed_hz: the effective SCK-speed that was used to 841 * transfer this transfer. Set to 0 if the spi bus driver does 842 * not support it. 843 * @transfer_list: transfers are sequenced through @spi_message.transfers 844 * @tx_sg: Scatterlist for transmit, currently not for client use 845 * @rx_sg: Scatterlist for receive, currently not for client use 846 * @ptp_sts_word_pre: The word (subject to bits_per_word semantics) offset 847 * within @tx_buf for which the SPI device is requesting that the time 848 * snapshot for this transfer begins. Upon completing the SPI transfer, 849 * this value may have changed compared to what was requested, depending 850 * on the available snapshotting resolution (DMA transfer, 851 * @ptp_sts_supported is false, etc). 852 * @ptp_sts_word_post: See @ptp_sts_word_post. The two can be equal (meaning 853 * that a single byte should be snapshotted). 854 * If the core takes care of the timestamp (if @ptp_sts_supported is false 855 * for this controller), it will set @ptp_sts_word_pre to 0, and 856 * @ptp_sts_word_post to the length of the transfer. This is done 857 * purposefully (instead of setting to spi_transfer->len - 1) to denote 858 * that a transfer-level snapshot taken from within the driver may still 859 * be of higher quality. 860 * @ptp_sts: Pointer to a memory location held by the SPI slave device where a 861 * PTP system timestamp structure may lie. If drivers use PIO or their 862 * hardware has some sort of assist for retrieving exact transfer timing, 863 * they can (and should) assert @ptp_sts_supported and populate this 864 * structure using the ptp_read_system_*ts helper functions. 865 * The timestamp must represent the time at which the SPI slave device has 866 * processed the word, i.e. the "pre" timestamp should be taken before 867 * transmitting the "pre" word, and the "post" timestamp after receiving 868 * transmit confirmation from the controller for the "post" word. 869 * @timestamped: true if the transfer has been timestamped 870 * @error: Error status logged by spi controller driver. 871 * 872 * SPI transfers always write the same number of bytes as they read. 873 * Protocol drivers should always provide @rx_buf and/or @tx_buf. 874 * In some cases, they may also want to provide DMA addresses for 875 * the data being transferred; that may reduce overhead, when the 876 * underlying driver uses dma. 877 * 878 * If the transmit buffer is null, zeroes will be shifted out 879 * while filling @rx_buf. If the receive buffer is null, the data 880 * shifted in will be discarded. Only "len" bytes shift out (or in). 881 * It's an error to try to shift out a partial word. (For example, by 882 * shifting out three bytes with word size of sixteen or twenty bits; 883 * the former uses two bytes per word, the latter uses four bytes.) 884 * 885 * In-memory data values are always in native CPU byte order, translated 886 * from the wire byte order (big-endian except with SPI_LSB_FIRST). So 887 * for example when bits_per_word is sixteen, buffers are 2N bytes long 888 * (@len = 2N) and hold N sixteen bit words in CPU byte order. 889 * 890 * When the word size of the SPI transfer is not a power-of-two multiple 891 * of eight bits, those in-memory words include extra bits. In-memory 892 * words are always seen by protocol drivers as right-justified, so the 893 * undefined (rx) or unused (tx) bits are always the most significant bits. 894 * 895 * All SPI transfers start with the relevant chipselect active. Normally 896 * it stays selected until after the last transfer in a message. Drivers 897 * can affect the chipselect signal using cs_change. 898 * 899 * (i) If the transfer isn't the last one in the message, this flag is 900 * used to make the chipselect briefly go inactive in the middle of the 901 * message. Toggling chipselect in this way may be needed to terminate 902 * a chip command, letting a single spi_message perform all of group of 903 * chip transactions together. 904 * 905 * (ii) When the transfer is the last one in the message, the chip may 906 * stay selected until the next transfer. On multi-device SPI busses 907 * with nothing blocking messages going to other devices, this is just 908 * a performance hint; starting a message to another device deselects 909 * this one. But in other cases, this can be used to ensure correctness. 910 * Some devices need protocol transactions to be built from a series of 911 * spi_message submissions, where the content of one message is determined 912 * by the results of previous messages and where the whole transaction 913 * ends when the chipselect goes intactive. 914 * 915 * When SPI can transfer in 1x,2x or 4x. It can get this transfer information 916 * from device through @tx_nbits and @rx_nbits. In Bi-direction, these 917 * two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x) 918 * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer. 919 * 920 * The code that submits an spi_message (and its spi_transfers) 921 * to the lower layers is responsible for managing its memory. 922 * Zero-initialize every field you don't set up explicitly, to 923 * insulate against future API updates. After you submit a message 924 * and its transfers, ignore them until its completion callback. 925 */ 926 struct spi_transfer { 927 /* it's ok if tx_buf == rx_buf (right?) 928 * for MicroWire, one buffer must be null 929 * buffers must work with dma_*map_single() calls, unless 930 * spi_message.is_dma_mapped reports a pre-existing mapping 931 */ 932 const void *tx_buf; 933 void *rx_buf; 934 unsigned len; 935 936 dma_addr_t tx_dma; 937 dma_addr_t rx_dma; 938 struct sg_table tx_sg; 939 struct sg_table rx_sg; 940 941 unsigned dummy_data:1; 942 unsigned cs_change:1; 943 unsigned tx_nbits:3; 944 unsigned rx_nbits:3; 945 #define SPI_NBITS_SINGLE 0x01 /* 1bit transfer */ 946 #define SPI_NBITS_DUAL 0x02 /* 2bits transfer */ 947 #define SPI_NBITS_QUAD 0x04 /* 4bits transfer */ 948 u8 bits_per_word; 949 struct spi_delay delay; 950 struct spi_delay cs_change_delay; 951 struct spi_delay word_delay; 952 u32 speed_hz; 953 954 u32 effective_speed_hz; 955 956 unsigned int ptp_sts_word_pre; 957 unsigned int ptp_sts_word_post; 958 959 struct ptp_system_timestamp *ptp_sts; 960 961 bool timestamped; 962 963 struct list_head transfer_list; 964 965 #define SPI_TRANS_FAIL_NO_START BIT(0) 966 u16 error; 967 }; 968 969 /** 970 * struct spi_message - one multi-segment SPI transaction 971 * @transfers: list of transfer segments in this transaction 972 * @spi: SPI device to which the transaction is queued 973 * @is_dma_mapped: if true, the caller provided both dma and cpu virtual 974 * addresses for each transfer buffer 975 * @complete: called to report transaction completions 976 * @context: the argument to complete() when it's called 977 * @frame_length: the total number of bytes in the message 978 * @actual_length: the total number of bytes that were transferred in all 979 * successful segments 980 * @status: zero for success, else negative errno 981 * @queue: for use by whichever driver currently owns the message 982 * @state: for use by whichever driver currently owns the message 983 * @resources: for resource management when the spi message is processed 984 * 985 * A @spi_message is used to execute an atomic sequence of data transfers, 986 * each represented by a struct spi_transfer. The sequence is "atomic" 987 * in the sense that no other spi_message may use that SPI bus until that 988 * sequence completes. On some systems, many such sequences can execute as 989 * a single programmed DMA transfer. On all systems, these messages are 990 * queued, and might complete after transactions to other devices. Messages 991 * sent to a given spi_device are always executed in FIFO order. 992 * 993 * The code that submits an spi_message (and its spi_transfers) 994 * to the lower layers is responsible for managing its memory. 995 * Zero-initialize every field you don't set up explicitly, to 996 * insulate against future API updates. After you submit a message 997 * and its transfers, ignore them until its completion callback. 998 */ 999 struct spi_message { 1000 struct list_head transfers; 1001 1002 struct spi_device *spi; 1003 1004 unsigned is_dma_mapped:1; 1005 1006 /* REVISIT: we might want a flag affecting the behavior of the 1007 * last transfer ... allowing things like "read 16 bit length L" 1008 * immediately followed by "read L bytes". Basically imposing 1009 * a specific message scheduling algorithm. 1010 * 1011 * Some controller drivers (message-at-a-time queue processing) 1012 * could provide that as their default scheduling algorithm. But 1013 * others (with multi-message pipelines) could need a flag to 1014 * tell them about such special cases. 1015 */ 1016 1017 /* completion is reported through a callback */ 1018 void (*complete)(void *context); 1019 void *context; 1020 unsigned frame_length; 1021 unsigned actual_length; 1022 int status; 1023 1024 /* for optional use by whatever driver currently owns the 1025 * spi_message ... between calls to spi_async and then later 1026 * complete(), that's the spi_controller controller driver. 1027 */ 1028 struct list_head queue; 1029 void *state; 1030 1031 /* list of spi_res reources when the spi message is processed */ 1032 struct list_head resources; 1033 }; 1034 1035 static inline void spi_message_init_no_memset(struct spi_message *m) 1036 { 1037 INIT_LIST_HEAD(&m->transfers); 1038 INIT_LIST_HEAD(&m->resources); 1039 } 1040 1041 static inline void spi_message_init(struct spi_message *m) 1042 { 1043 memset(m, 0, sizeof *m); 1044 spi_message_init_no_memset(m); 1045 } 1046 1047 static inline void 1048 spi_message_add_tail(struct spi_transfer *t, struct spi_message *m) 1049 { 1050 list_add_tail(&t->transfer_list, &m->transfers); 1051 } 1052 1053 static inline void 1054 spi_transfer_del(struct spi_transfer *t) 1055 { 1056 list_del(&t->transfer_list); 1057 } 1058 1059 static inline int 1060 spi_transfer_delay_exec(struct spi_transfer *t) 1061 { 1062 return spi_delay_exec(&t->delay, t); 1063 } 1064 1065 /** 1066 * spi_message_init_with_transfers - Initialize spi_message and append transfers 1067 * @m: spi_message to be initialized 1068 * @xfers: An array of spi transfers 1069 * @num_xfers: Number of items in the xfer array 1070 * 1071 * This function initializes the given spi_message and adds each spi_transfer in 1072 * the given array to the message. 1073 */ 1074 static inline void 1075 spi_message_init_with_transfers(struct spi_message *m, 1076 struct spi_transfer *xfers, unsigned int num_xfers) 1077 { 1078 unsigned int i; 1079 1080 spi_message_init(m); 1081 for (i = 0; i < num_xfers; ++i) 1082 spi_message_add_tail(&xfers[i], m); 1083 } 1084 1085 /* It's fine to embed message and transaction structures in other data 1086 * structures so long as you don't free them while they're in use. 1087 */ 1088 1089 static inline struct spi_message *spi_message_alloc(unsigned ntrans, gfp_t flags) 1090 { 1091 struct spi_message *m; 1092 1093 m = kzalloc(sizeof(struct spi_message) 1094 + ntrans * sizeof(struct spi_transfer), 1095 flags); 1096 if (m) { 1097 unsigned i; 1098 struct spi_transfer *t = (struct spi_transfer *)(m + 1); 1099 1100 spi_message_init_no_memset(m); 1101 for (i = 0; i < ntrans; i++, t++) 1102 spi_message_add_tail(t, m); 1103 } 1104 return m; 1105 } 1106 1107 static inline void spi_message_free(struct spi_message *m) 1108 { 1109 kfree(m); 1110 } 1111 1112 extern int spi_setup(struct spi_device *spi); 1113 extern int spi_async(struct spi_device *spi, struct spi_message *message); 1114 extern int spi_async_locked(struct spi_device *spi, 1115 struct spi_message *message); 1116 extern int spi_slave_abort(struct spi_device *spi); 1117 1118 static inline size_t 1119 spi_max_message_size(struct spi_device *spi) 1120 { 1121 struct spi_controller *ctlr = spi->controller; 1122 1123 if (!ctlr->max_message_size) 1124 return SIZE_MAX; 1125 return ctlr->max_message_size(spi); 1126 } 1127 1128 static inline size_t 1129 spi_max_transfer_size(struct spi_device *spi) 1130 { 1131 struct spi_controller *ctlr = spi->controller; 1132 size_t tr_max = SIZE_MAX; 1133 size_t msg_max = spi_max_message_size(spi); 1134 1135 if (ctlr->max_transfer_size) 1136 tr_max = ctlr->max_transfer_size(spi); 1137 1138 /* transfer size limit must not be greater than messsage size limit */ 1139 return min(tr_max, msg_max); 1140 } 1141 1142 /** 1143 * spi_is_bpw_supported - Check if bits per word is supported 1144 * @spi: SPI device 1145 * @bpw: Bits per word 1146 * 1147 * This function checks to see if the SPI controller supports @bpw. 1148 * 1149 * Returns: 1150 * True if @bpw is supported, false otherwise. 1151 */ 1152 static inline bool spi_is_bpw_supported(struct spi_device *spi, u32 bpw) 1153 { 1154 u32 bpw_mask = spi->master->bits_per_word_mask; 1155 1156 if (bpw == 8 || (bpw <= 32 && bpw_mask & SPI_BPW_MASK(bpw))) 1157 return true; 1158 1159 return false; 1160 } 1161 1162 /*---------------------------------------------------------------------------*/ 1163 1164 /* SPI transfer replacement methods which make use of spi_res */ 1165 1166 struct spi_replaced_transfers; 1167 typedef void (*spi_replaced_release_t)(struct spi_controller *ctlr, 1168 struct spi_message *msg, 1169 struct spi_replaced_transfers *res); 1170 /** 1171 * struct spi_replaced_transfers - structure describing the spi_transfer 1172 * replacements that have occurred 1173 * so that they can get reverted 1174 * @release: some extra release code to get executed prior to 1175 * relasing this structure 1176 * @extradata: pointer to some extra data if requested or NULL 1177 * @replaced_transfers: transfers that have been replaced and which need 1178 * to get restored 1179 * @replaced_after: the transfer after which the @replaced_transfers 1180 * are to get re-inserted 1181 * @inserted: number of transfers inserted 1182 * @inserted_transfers: array of spi_transfers of array-size @inserted, 1183 * that have been replacing replaced_transfers 1184 * 1185 * note: that @extradata will point to @inserted_transfers[@inserted] 1186 * if some extra allocation is requested, so alignment will be the same 1187 * as for spi_transfers 1188 */ 1189 struct spi_replaced_transfers { 1190 spi_replaced_release_t release; 1191 void *extradata; 1192 struct list_head replaced_transfers; 1193 struct list_head *replaced_after; 1194 size_t inserted; 1195 struct spi_transfer inserted_transfers[]; 1196 }; 1197 1198 extern struct spi_replaced_transfers *spi_replace_transfers( 1199 struct spi_message *msg, 1200 struct spi_transfer *xfer_first, 1201 size_t remove, 1202 size_t insert, 1203 spi_replaced_release_t release, 1204 size_t extradatasize, 1205 gfp_t gfp); 1206 1207 /*---------------------------------------------------------------------------*/ 1208 1209 /* SPI transfer transformation methods */ 1210 1211 extern int spi_split_transfers_maxsize(struct spi_controller *ctlr, 1212 struct spi_message *msg, 1213 size_t maxsize, 1214 gfp_t gfp); 1215 1216 /*---------------------------------------------------------------------------*/ 1217 1218 /* All these synchronous SPI transfer routines are utilities layered 1219 * over the core async transfer primitive. Here, "synchronous" means 1220 * they will sleep uninterruptibly until the async transfer completes. 1221 */ 1222 1223 extern int spi_sync(struct spi_device *spi, struct spi_message *message); 1224 extern int spi_sync_locked(struct spi_device *spi, struct spi_message *message); 1225 extern int spi_bus_lock(struct spi_controller *ctlr); 1226 extern int spi_bus_unlock(struct spi_controller *ctlr); 1227 1228 /** 1229 * spi_sync_transfer - synchronous SPI data transfer 1230 * @spi: device with which data will be exchanged 1231 * @xfers: An array of spi_transfers 1232 * @num_xfers: Number of items in the xfer array 1233 * Context: can sleep 1234 * 1235 * Does a synchronous SPI data transfer of the given spi_transfer array. 1236 * 1237 * For more specific semantics see spi_sync(). 1238 * 1239 * Return: zero on success, else a negative error code. 1240 */ 1241 static inline int 1242 spi_sync_transfer(struct spi_device *spi, struct spi_transfer *xfers, 1243 unsigned int num_xfers) 1244 { 1245 struct spi_message msg; 1246 1247 spi_message_init_with_transfers(&msg, xfers, num_xfers); 1248 1249 return spi_sync(spi, &msg); 1250 } 1251 1252 /** 1253 * spi_write - SPI synchronous write 1254 * @spi: device to which data will be written 1255 * @buf: data buffer 1256 * @len: data buffer size 1257 * Context: can sleep 1258 * 1259 * This function writes the buffer @buf. 1260 * Callable only from contexts that can sleep. 1261 * 1262 * Return: zero on success, else a negative error code. 1263 */ 1264 static inline int 1265 spi_write(struct spi_device *spi, const void *buf, size_t len) 1266 { 1267 struct spi_transfer t = { 1268 .tx_buf = buf, 1269 .len = len, 1270 }; 1271 1272 return spi_sync_transfer(spi, &t, 1); 1273 } 1274 1275 /** 1276 * spi_read - SPI synchronous read 1277 * @spi: device from which data will be read 1278 * @buf: data buffer 1279 * @len: data buffer size 1280 * Context: can sleep 1281 * 1282 * This function reads the buffer @buf. 1283 * Callable only from contexts that can sleep. 1284 * 1285 * Return: zero on success, else a negative error code. 1286 */ 1287 static inline int 1288 spi_read(struct spi_device *spi, void *buf, size_t len) 1289 { 1290 struct spi_transfer t = { 1291 .rx_buf = buf, 1292 .len = len, 1293 }; 1294 1295 return spi_sync_transfer(spi, &t, 1); 1296 } 1297 1298 /* this copies txbuf and rxbuf data; for small transfers only! */ 1299 extern int spi_write_then_read(struct spi_device *spi, 1300 const void *txbuf, unsigned n_tx, 1301 void *rxbuf, unsigned n_rx); 1302 1303 /** 1304 * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read 1305 * @spi: device with which data will be exchanged 1306 * @cmd: command to be written before data is read back 1307 * Context: can sleep 1308 * 1309 * Callable only from contexts that can sleep. 1310 * 1311 * Return: the (unsigned) eight bit number returned by the 1312 * device, or else a negative error code. 1313 */ 1314 static inline ssize_t spi_w8r8(struct spi_device *spi, u8 cmd) 1315 { 1316 ssize_t status; 1317 u8 result; 1318 1319 status = spi_write_then_read(spi, &cmd, 1, &result, 1); 1320 1321 /* return negative errno or unsigned value */ 1322 return (status < 0) ? status : result; 1323 } 1324 1325 /** 1326 * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read 1327 * @spi: device with which data will be exchanged 1328 * @cmd: command to be written before data is read back 1329 * Context: can sleep 1330 * 1331 * The number is returned in wire-order, which is at least sometimes 1332 * big-endian. 1333 * 1334 * Callable only from contexts that can sleep. 1335 * 1336 * Return: the (unsigned) sixteen bit number returned by the 1337 * device, or else a negative error code. 1338 */ 1339 static inline ssize_t spi_w8r16(struct spi_device *spi, u8 cmd) 1340 { 1341 ssize_t status; 1342 u16 result; 1343 1344 status = spi_write_then_read(spi, &cmd, 1, &result, 2); 1345 1346 /* return negative errno or unsigned value */ 1347 return (status < 0) ? status : result; 1348 } 1349 1350 /** 1351 * spi_w8r16be - SPI synchronous 8 bit write followed by 16 bit big-endian read 1352 * @spi: device with which data will be exchanged 1353 * @cmd: command to be written before data is read back 1354 * Context: can sleep 1355 * 1356 * This function is similar to spi_w8r16, with the exception that it will 1357 * convert the read 16 bit data word from big-endian to native endianness. 1358 * 1359 * Callable only from contexts that can sleep. 1360 * 1361 * Return: the (unsigned) sixteen bit number returned by the device in cpu 1362 * endianness, or else a negative error code. 1363 */ 1364 static inline ssize_t spi_w8r16be(struct spi_device *spi, u8 cmd) 1365 1366 { 1367 ssize_t status; 1368 __be16 result; 1369 1370 status = spi_write_then_read(spi, &cmd, 1, &result, 2); 1371 if (status < 0) 1372 return status; 1373 1374 return be16_to_cpu(result); 1375 } 1376 1377 /*---------------------------------------------------------------------------*/ 1378 1379 /* 1380 * INTERFACE between board init code and SPI infrastructure. 1381 * 1382 * No SPI driver ever sees these SPI device table segments, but 1383 * it's how the SPI core (or adapters that get hotplugged) grows 1384 * the driver model tree. 1385 * 1386 * As a rule, SPI devices can't be probed. Instead, board init code 1387 * provides a table listing the devices which are present, with enough 1388 * information to bind and set up the device's driver. There's basic 1389 * support for nonstatic configurations too; enough to handle adding 1390 * parport adapters, or microcontrollers acting as USB-to-SPI bridges. 1391 */ 1392 1393 /** 1394 * struct spi_board_info - board-specific template for a SPI device 1395 * @modalias: Initializes spi_device.modalias; identifies the driver. 1396 * @platform_data: Initializes spi_device.platform_data; the particular 1397 * data stored there is driver-specific. 1398 * @swnode: Software node for the device. 1399 * @controller_data: Initializes spi_device.controller_data; some 1400 * controllers need hints about hardware setup, e.g. for DMA. 1401 * @irq: Initializes spi_device.irq; depends on how the board is wired. 1402 * @max_speed_hz: Initializes spi_device.max_speed_hz; based on limits 1403 * from the chip datasheet and board-specific signal quality issues. 1404 * @bus_num: Identifies which spi_controller parents the spi_device; unused 1405 * by spi_new_device(), and otherwise depends on board wiring. 1406 * @chip_select: Initializes spi_device.chip_select; depends on how 1407 * the board is wired. 1408 * @mode: Initializes spi_device.mode; based on the chip datasheet, board 1409 * wiring (some devices support both 3WIRE and standard modes), and 1410 * possibly presence of an inverter in the chipselect path. 1411 * 1412 * When adding new SPI devices to the device tree, these structures serve 1413 * as a partial device template. They hold information which can't always 1414 * be determined by drivers. Information that probe() can establish (such 1415 * as the default transfer wordsize) is not included here. 1416 * 1417 * These structures are used in two places. Their primary role is to 1418 * be stored in tables of board-specific device descriptors, which are 1419 * declared early in board initialization and then used (much later) to 1420 * populate a controller's device tree after the that controller's driver 1421 * initializes. A secondary (and atypical) role is as a parameter to 1422 * spi_new_device() call, which happens after those controller drivers 1423 * are active in some dynamic board configuration models. 1424 */ 1425 struct spi_board_info { 1426 /* the device name and module name are coupled, like platform_bus; 1427 * "modalias" is normally the driver name. 1428 * 1429 * platform_data goes to spi_device.dev.platform_data, 1430 * controller_data goes to spi_device.controller_data, 1431 * irq is copied too 1432 */ 1433 char modalias[SPI_NAME_SIZE]; 1434 const void *platform_data; 1435 const struct software_node *swnode; 1436 void *controller_data; 1437 int irq; 1438 1439 /* slower signaling on noisy or low voltage boards */ 1440 u32 max_speed_hz; 1441 1442 1443 /* bus_num is board specific and matches the bus_num of some 1444 * spi_controller that will probably be registered later. 1445 * 1446 * chip_select reflects how this chip is wired to that master; 1447 * it's less than num_chipselect. 1448 */ 1449 u16 bus_num; 1450 u16 chip_select; 1451 1452 /* mode becomes spi_device.mode, and is essential for chips 1453 * where the default of SPI_CS_HIGH = 0 is wrong. 1454 */ 1455 u32 mode; 1456 1457 /* ... may need additional spi_device chip config data here. 1458 * avoid stuff protocol drivers can set; but include stuff 1459 * needed to behave without being bound to a driver: 1460 * - quirks like clock rate mattering when not selected 1461 */ 1462 }; 1463 1464 #ifdef CONFIG_SPI 1465 extern int 1466 spi_register_board_info(struct spi_board_info const *info, unsigned n); 1467 #else 1468 /* board init code may ignore whether SPI is configured or not */ 1469 static inline int 1470 spi_register_board_info(struct spi_board_info const *info, unsigned n) 1471 { return 0; } 1472 #endif 1473 1474 /* If you're hotplugging an adapter with devices (parport, usb, etc) 1475 * use spi_new_device() to describe each device. You can also call 1476 * spi_unregister_device() to start making that device vanish, but 1477 * normally that would be handled by spi_unregister_controller(). 1478 * 1479 * You can also use spi_alloc_device() and spi_add_device() to use a two 1480 * stage registration sequence for each spi_device. This gives the caller 1481 * some more control over the spi_device structure before it is registered, 1482 * but requires that caller to initialize fields that would otherwise 1483 * be defined using the board info. 1484 */ 1485 extern struct spi_device * 1486 spi_alloc_device(struct spi_controller *ctlr); 1487 1488 extern int 1489 spi_add_device(struct spi_device *spi); 1490 1491 extern struct spi_device * 1492 spi_new_device(struct spi_controller *, struct spi_board_info *); 1493 1494 extern void spi_unregister_device(struct spi_device *spi); 1495 1496 extern const struct spi_device_id * 1497 spi_get_device_id(const struct spi_device *sdev); 1498 1499 static inline bool 1500 spi_transfer_is_last(struct spi_controller *ctlr, struct spi_transfer *xfer) 1501 { 1502 return list_is_last(&xfer->transfer_list, &ctlr->cur_msg->transfers); 1503 } 1504 1505 /* OF support code */ 1506 #if IS_ENABLED(CONFIG_OF) 1507 1508 /* must call put_device() when done with returned spi_device device */ 1509 extern struct spi_device * 1510 of_find_spi_device_by_node(struct device_node *node); 1511 1512 #else 1513 1514 static inline struct spi_device * 1515 of_find_spi_device_by_node(struct device_node *node) 1516 { 1517 return NULL; 1518 } 1519 1520 #endif /* IS_ENABLED(CONFIG_OF) */ 1521 1522 /* Compatibility layer */ 1523 #define spi_master spi_controller 1524 1525 #define SPI_MASTER_HALF_DUPLEX SPI_CONTROLLER_HALF_DUPLEX 1526 #define SPI_MASTER_NO_RX SPI_CONTROLLER_NO_RX 1527 #define SPI_MASTER_NO_TX SPI_CONTROLLER_NO_TX 1528 #define SPI_MASTER_MUST_RX SPI_CONTROLLER_MUST_RX 1529 #define SPI_MASTER_MUST_TX SPI_CONTROLLER_MUST_TX 1530 1531 #define spi_master_get_devdata(_ctlr) spi_controller_get_devdata(_ctlr) 1532 #define spi_master_set_devdata(_ctlr, _data) \ 1533 spi_controller_set_devdata(_ctlr, _data) 1534 #define spi_master_get(_ctlr) spi_controller_get(_ctlr) 1535 #define spi_master_put(_ctlr) spi_controller_put(_ctlr) 1536 #define spi_master_suspend(_ctlr) spi_controller_suspend(_ctlr) 1537 #define spi_master_resume(_ctlr) spi_controller_resume(_ctlr) 1538 1539 #define spi_register_master(_ctlr) spi_register_controller(_ctlr) 1540 #define devm_spi_register_master(_dev, _ctlr) \ 1541 devm_spi_register_controller(_dev, _ctlr) 1542 #define spi_unregister_master(_ctlr) spi_unregister_controller(_ctlr) 1543 1544 #endif /* __LINUX_SPI_H */ 1545