1 /* SPDX-License-Identifier: GPL-2.0-or-later 2 * 3 * Copyright (C) 2005 David Brownell 4 */ 5 6 #ifndef __LINUX_SPI_H 7 #define __LINUX_SPI_H 8 9 #include <linux/bits.h> 10 #include <linux/device.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/slab.h> 13 #include <linux/kthread.h> 14 #include <linux/completion.h> 15 #include <linux/scatterlist.h> 16 #include <linux/gpio/consumer.h> 17 18 #include <uapi/linux/spi/spi.h> 19 #include <linux/acpi.h> 20 #include <linux/u64_stats_sync.h> 21 22 struct dma_chan; 23 struct software_node; 24 struct ptp_system_timestamp; 25 struct spi_controller; 26 struct spi_transfer; 27 struct spi_controller_mem_ops; 28 struct spi_controller_mem_caps; 29 30 /* 31 * INTERFACES between SPI master-side drivers and SPI slave protocol handlers, 32 * and SPI infrastructure. 33 */ 34 extern struct bus_type spi_bus_type; 35 36 /** 37 * struct spi_statistics - statistics for spi transfers 38 * @syncp: seqcount to protect members in this struct for per-cpu udate 39 * on 32-bit systems 40 * 41 * @messages: number of spi-messages handled 42 * @transfers: number of spi_transfers handled 43 * @errors: number of errors during spi_transfer 44 * @timedout: number of timeouts during spi_transfer 45 * 46 * @spi_sync: number of times spi_sync is used 47 * @spi_sync_immediate: 48 * number of times spi_sync is executed immediately 49 * in calling context without queuing and scheduling 50 * @spi_async: number of times spi_async is used 51 * 52 * @bytes: number of bytes transferred to/from device 53 * @bytes_tx: number of bytes sent to device 54 * @bytes_rx: number of bytes received from device 55 * 56 * @transfer_bytes_histo: 57 * transfer bytes histogramm 58 * 59 * @transfers_split_maxsize: 60 * number of transfers that have been split because of 61 * maxsize limit 62 */ 63 struct spi_statistics { 64 struct u64_stats_sync syncp; 65 66 u64_stats_t messages; 67 u64_stats_t transfers; 68 u64_stats_t errors; 69 u64_stats_t timedout; 70 71 u64_stats_t spi_sync; 72 u64_stats_t spi_sync_immediate; 73 u64_stats_t spi_async; 74 75 u64_stats_t bytes; 76 u64_stats_t bytes_rx; 77 u64_stats_t bytes_tx; 78 79 #define SPI_STATISTICS_HISTO_SIZE 17 80 u64_stats_t transfer_bytes_histo[SPI_STATISTICS_HISTO_SIZE]; 81 82 u64_stats_t transfers_split_maxsize; 83 }; 84 85 #define SPI_STATISTICS_ADD_TO_FIELD(pcpu_stats, field, count) \ 86 do { \ 87 struct spi_statistics *__lstats; \ 88 get_cpu(); \ 89 __lstats = this_cpu_ptr(pcpu_stats); \ 90 u64_stats_update_begin(&__lstats->syncp); \ 91 u64_stats_add(&__lstats->field, count); \ 92 u64_stats_update_end(&__lstats->syncp); \ 93 put_cpu(); \ 94 } while (0) 95 96 #define SPI_STATISTICS_INCREMENT_FIELD(pcpu_stats, field) \ 97 do { \ 98 struct spi_statistics *__lstats; \ 99 get_cpu(); \ 100 __lstats = this_cpu_ptr(pcpu_stats); \ 101 u64_stats_update_begin(&__lstats->syncp); \ 102 u64_stats_inc(&__lstats->field); \ 103 u64_stats_update_end(&__lstats->syncp); \ 104 put_cpu(); \ 105 } while (0) 106 107 /** 108 * struct spi_delay - SPI delay information 109 * @value: Value for the delay 110 * @unit: Unit for the delay 111 */ 112 struct spi_delay { 113 #define SPI_DELAY_UNIT_USECS 0 114 #define SPI_DELAY_UNIT_NSECS 1 115 #define SPI_DELAY_UNIT_SCK 2 116 u16 value; 117 u8 unit; 118 }; 119 120 extern int spi_delay_to_ns(struct spi_delay *_delay, struct spi_transfer *xfer); 121 extern int spi_delay_exec(struct spi_delay *_delay, struct spi_transfer *xfer); 122 123 /** 124 * struct spi_device - Controller side proxy for an SPI slave device 125 * @dev: Driver model representation of the device. 126 * @controller: SPI controller used with the device. 127 * @master: Copy of controller, for backwards compatibility. 128 * @max_speed_hz: Maximum clock rate to be used with this chip 129 * (on this board); may be changed by the device's driver. 130 * The spi_transfer.speed_hz can override this for each transfer. 131 * @chip_select: Chipselect, distinguishing chips handled by @controller. 132 * @mode: The spi mode defines how data is clocked out and in. 133 * This may be changed by the device's driver. 134 * The "active low" default for chipselect mode can be overridden 135 * (by specifying SPI_CS_HIGH) as can the "MSB first" default for 136 * each word in a transfer (by specifying SPI_LSB_FIRST). 137 * @bits_per_word: Data transfers involve one or more words; word sizes 138 * like eight or 12 bits are common. In-memory wordsizes are 139 * powers of two bytes (e.g. 20 bit samples use 32 bits). 140 * This may be changed by the device's driver, or left at the 141 * default (0) indicating protocol words are eight bit bytes. 142 * The spi_transfer.bits_per_word can override this for each transfer. 143 * @rt: Make the pump thread real time priority. 144 * @irq: Negative, or the number passed to request_irq() to receive 145 * interrupts from this device. 146 * @controller_state: Controller's runtime state 147 * @controller_data: Board-specific definitions for controller, such as 148 * FIFO initialization parameters; from board_info.controller_data 149 * @modalias: Name of the driver to use with this device, or an alias 150 * for that name. This appears in the sysfs "modalias" attribute 151 * for driver coldplugging, and in uevents used for hotplugging 152 * @driver_override: If the name of a driver is written to this attribute, then 153 * the device will bind to the named driver and only the named driver. 154 * Do not set directly, because core frees it; use driver_set_override() to 155 * set or clear it. 156 * @cs_gpiod: gpio descriptor of the chipselect line (optional, NULL when 157 * not using a GPIO line) 158 * @word_delay: delay to be inserted between consecutive 159 * words of a transfer 160 * @cs_setup: delay to be introduced by the controller after CS is asserted 161 * @cs_hold: delay to be introduced by the controller before CS is deasserted 162 * @cs_inactive: delay to be introduced by the controller after CS is 163 * deasserted. If @cs_change_delay is used from @spi_transfer, then the 164 * two delays will be added up. 165 * @pcpu_statistics: statistics for the spi_device 166 * 167 * A @spi_device is used to interchange data between an SPI slave 168 * (usually a discrete chip) and CPU memory. 169 * 170 * In @dev, the platform_data is used to hold information about this 171 * device that's meaningful to the device's protocol driver, but not 172 * to its controller. One example might be an identifier for a chip 173 * variant with slightly different functionality; another might be 174 * information about how this particular board wires the chip's pins. 175 */ 176 struct spi_device { 177 struct device dev; 178 struct spi_controller *controller; 179 struct spi_controller *master; /* Compatibility layer */ 180 u32 max_speed_hz; 181 u8 chip_select; 182 u8 bits_per_word; 183 bool rt; 184 #define SPI_NO_TX BIT(31) /* No transmit wire */ 185 #define SPI_NO_RX BIT(30) /* No receive wire */ 186 /* 187 * All bits defined above should be covered by SPI_MODE_KERNEL_MASK. 188 * The SPI_MODE_KERNEL_MASK has the SPI_MODE_USER_MASK counterpart, 189 * which is defined in 'include/uapi/linux/spi/spi.h'. 190 * The bits defined here are from bit 31 downwards, while in 191 * SPI_MODE_USER_MASK are from 0 upwards. 192 * These bits must not overlap. A static assert check should make sure of that. 193 * If adding extra bits, make sure to decrease the bit index below as well. 194 */ 195 #define SPI_MODE_KERNEL_MASK (~(BIT(30) - 1)) 196 u32 mode; 197 int irq; 198 void *controller_state; 199 void *controller_data; 200 char modalias[SPI_NAME_SIZE]; 201 const char *driver_override; 202 struct gpio_desc *cs_gpiod; /* Chip select gpio desc */ 203 struct spi_delay word_delay; /* Inter-word delay */ 204 /* CS delays */ 205 struct spi_delay cs_setup; 206 struct spi_delay cs_hold; 207 struct spi_delay cs_inactive; 208 209 /* The statistics */ 210 struct spi_statistics __percpu *pcpu_statistics; 211 212 /* 213 * likely need more hooks for more protocol options affecting how 214 * the controller talks to each chip, like: 215 * - memory packing (12 bit samples into low bits, others zeroed) 216 * - priority 217 * - chipselect delays 218 * - ... 219 */ 220 }; 221 222 /* Make sure that SPI_MODE_KERNEL_MASK & SPI_MODE_USER_MASK don't overlap */ 223 static_assert((SPI_MODE_KERNEL_MASK & SPI_MODE_USER_MASK) == 0, 224 "SPI_MODE_USER_MASK & SPI_MODE_KERNEL_MASK must not overlap"); 225 226 static inline struct spi_device *to_spi_device(struct device *dev) 227 { 228 return dev ? container_of(dev, struct spi_device, dev) : NULL; 229 } 230 231 /* Most drivers won't need to care about device refcounting */ 232 static inline struct spi_device *spi_dev_get(struct spi_device *spi) 233 { 234 return (spi && get_device(&spi->dev)) ? spi : NULL; 235 } 236 237 static inline void spi_dev_put(struct spi_device *spi) 238 { 239 if (spi) 240 put_device(&spi->dev); 241 } 242 243 /* ctldata is for the bus_controller driver's runtime state */ 244 static inline void *spi_get_ctldata(struct spi_device *spi) 245 { 246 return spi->controller_state; 247 } 248 249 static inline void spi_set_ctldata(struct spi_device *spi, void *state) 250 { 251 spi->controller_state = state; 252 } 253 254 /* Device driver data */ 255 256 static inline void spi_set_drvdata(struct spi_device *spi, void *data) 257 { 258 dev_set_drvdata(&spi->dev, data); 259 } 260 261 static inline void *spi_get_drvdata(struct spi_device *spi) 262 { 263 return dev_get_drvdata(&spi->dev); 264 } 265 266 struct spi_message; 267 268 /** 269 * struct spi_driver - Host side "protocol" driver 270 * @id_table: List of SPI devices supported by this driver 271 * @probe: Binds this driver to the spi device. Drivers can verify 272 * that the device is actually present, and may need to configure 273 * characteristics (such as bits_per_word) which weren't needed for 274 * the initial configuration done during system setup. 275 * @remove: Unbinds this driver from the spi device 276 * @shutdown: Standard shutdown callback used during system state 277 * transitions such as powerdown/halt and kexec 278 * @driver: SPI device drivers should initialize the name and owner 279 * field of this structure. 280 * 281 * This represents the kind of device driver that uses SPI messages to 282 * interact with the hardware at the other end of a SPI link. It's called 283 * a "protocol" driver because it works through messages rather than talking 284 * directly to SPI hardware (which is what the underlying SPI controller 285 * driver does to pass those messages). These protocols are defined in the 286 * specification for the device(s) supported by the driver. 287 * 288 * As a rule, those device protocols represent the lowest level interface 289 * supported by a driver, and it will support upper level interfaces too. 290 * Examples of such upper levels include frameworks like MTD, networking, 291 * MMC, RTC, filesystem character device nodes, and hardware monitoring. 292 */ 293 struct spi_driver { 294 const struct spi_device_id *id_table; 295 int (*probe)(struct spi_device *spi); 296 void (*remove)(struct spi_device *spi); 297 void (*shutdown)(struct spi_device *spi); 298 struct device_driver driver; 299 }; 300 301 static inline struct spi_driver *to_spi_driver(struct device_driver *drv) 302 { 303 return drv ? container_of(drv, struct spi_driver, driver) : NULL; 304 } 305 306 extern int __spi_register_driver(struct module *owner, struct spi_driver *sdrv); 307 308 /** 309 * spi_unregister_driver - reverse effect of spi_register_driver 310 * @sdrv: the driver to unregister 311 * Context: can sleep 312 */ 313 static inline void spi_unregister_driver(struct spi_driver *sdrv) 314 { 315 if (sdrv) 316 driver_unregister(&sdrv->driver); 317 } 318 319 extern struct spi_device *spi_new_ancillary_device(struct spi_device *spi, u8 chip_select); 320 321 /* Use a define to avoid include chaining to get THIS_MODULE */ 322 #define spi_register_driver(driver) \ 323 __spi_register_driver(THIS_MODULE, driver) 324 325 /** 326 * module_spi_driver() - Helper macro for registering a SPI driver 327 * @__spi_driver: spi_driver struct 328 * 329 * Helper macro for SPI drivers which do not do anything special in module 330 * init/exit. This eliminates a lot of boilerplate. Each module may only 331 * use this macro once, and calling it replaces module_init() and module_exit() 332 */ 333 #define module_spi_driver(__spi_driver) \ 334 module_driver(__spi_driver, spi_register_driver, \ 335 spi_unregister_driver) 336 337 /** 338 * struct spi_controller - interface to SPI master or slave controller 339 * @dev: device interface to this driver 340 * @list: link with the global spi_controller list 341 * @bus_num: board-specific (and often SOC-specific) identifier for a 342 * given SPI controller. 343 * @num_chipselect: chipselects are used to distinguish individual 344 * SPI slaves, and are numbered from zero to num_chipselects. 345 * each slave has a chipselect signal, but it's common that not 346 * every chipselect is connected to a slave. 347 * @dma_alignment: SPI controller constraint on DMA buffers alignment. 348 * @mode_bits: flags understood by this controller driver 349 * @buswidth_override_bits: flags to override for this controller driver 350 * @bits_per_word_mask: A mask indicating which values of bits_per_word are 351 * supported by the driver. Bit n indicates that a bits_per_word n+1 is 352 * supported. If set, the SPI core will reject any transfer with an 353 * unsupported bits_per_word. If not set, this value is simply ignored, 354 * and it's up to the individual driver to perform any validation. 355 * @min_speed_hz: Lowest supported transfer speed 356 * @max_speed_hz: Highest supported transfer speed 357 * @flags: other constraints relevant to this driver 358 * @slave: indicates that this is an SPI slave controller 359 * @devm_allocated: whether the allocation of this struct is devres-managed 360 * @max_transfer_size: function that returns the max transfer size for 361 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used. 362 * @max_message_size: function that returns the max message size for 363 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used. 364 * @io_mutex: mutex for physical bus access 365 * @add_lock: mutex to avoid adding devices to the same chipselect 366 * @bus_lock_spinlock: spinlock for SPI bus locking 367 * @bus_lock_mutex: mutex for exclusion of multiple callers 368 * @bus_lock_flag: indicates that the SPI bus is locked for exclusive use 369 * @setup: updates the device mode and clocking records used by a 370 * device's SPI controller; protocol code may call this. This 371 * must fail if an unrecognized or unsupported mode is requested. 372 * It's always safe to call this unless transfers are pending on 373 * the device whose settings are being modified. 374 * @set_cs_timing: optional hook for SPI devices to request SPI master 375 * controller for configuring specific CS setup time, hold time and inactive 376 * delay interms of clock counts 377 * @transfer: adds a message to the controller's transfer queue. 378 * @cleanup: frees controller-specific state 379 * @can_dma: determine whether this controller supports DMA 380 * @dma_map_dev: device which can be used for DMA mapping 381 * @queued: whether this controller is providing an internal message queue 382 * @kworker: pointer to thread struct for message pump 383 * @pump_messages: work struct for scheduling work to the message pump 384 * @queue_lock: spinlock to syncronise access to message queue 385 * @queue: message queue 386 * @cur_msg: the currently in-flight message 387 * @cur_msg_completion: a completion for the current in-flight message 388 * @cur_msg_incomplete: Flag used internally to opportunistically skip 389 * the @cur_msg_completion. This flag is used to check if the driver has 390 * already called spi_finalize_current_message(). 391 * @cur_msg_need_completion: Flag used internally to opportunistically skip 392 * the @cur_msg_completion. This flag is used to signal the context that 393 * is running spi_finalize_current_message() that it needs to complete() 394 * @cur_msg_mapped: message has been mapped for DMA 395 * @last_cs: the last chip_select that is recorded by set_cs, -1 on non chip 396 * selected 397 * @last_cs_mode_high: was (mode & SPI_CS_HIGH) true on the last call to set_cs. 398 * @xfer_completion: used by core transfer_one_message() 399 * @busy: message pump is busy 400 * @running: message pump is running 401 * @rt: whether this queue is set to run as a realtime task 402 * @auto_runtime_pm: the core should ensure a runtime PM reference is held 403 * while the hardware is prepared, using the parent 404 * device for the spidev 405 * @max_dma_len: Maximum length of a DMA transfer for the device. 406 * @prepare_transfer_hardware: a message will soon arrive from the queue 407 * so the subsystem requests the driver to prepare the transfer hardware 408 * by issuing this call 409 * @transfer_one_message: the subsystem calls the driver to transfer a single 410 * message while queuing transfers that arrive in the meantime. When the 411 * driver is finished with this message, it must call 412 * spi_finalize_current_message() so the subsystem can issue the next 413 * message 414 * @unprepare_transfer_hardware: there are currently no more messages on the 415 * queue so the subsystem notifies the driver that it may relax the 416 * hardware by issuing this call 417 * 418 * @set_cs: set the logic level of the chip select line. May be called 419 * from interrupt context. 420 * @prepare_message: set up the controller to transfer a single message, 421 * for example doing DMA mapping. Called from threaded 422 * context. 423 * @transfer_one: transfer a single spi_transfer. 424 * 425 * - return 0 if the transfer is finished, 426 * - return 1 if the transfer is still in progress. When 427 * the driver is finished with this transfer it must 428 * call spi_finalize_current_transfer() so the subsystem 429 * can issue the next transfer. Note: transfer_one and 430 * transfer_one_message are mutually exclusive; when both 431 * are set, the generic subsystem does not call your 432 * transfer_one callback. 433 * @handle_err: the subsystem calls the driver to handle an error that occurs 434 * in the generic implementation of transfer_one_message(). 435 * @mem_ops: optimized/dedicated operations for interactions with SPI memory. 436 * This field is optional and should only be implemented if the 437 * controller has native support for memory like operations. 438 * @mem_caps: controller capabilities for the handling of memory operations. 439 * @unprepare_message: undo any work done by prepare_message(). 440 * @slave_abort: abort the ongoing transfer request on an SPI slave controller 441 * @cs_gpiods: Array of GPIO descs to use as chip select lines; one per CS 442 * number. Any individual value may be NULL for CS lines that 443 * are not GPIOs (driven by the SPI controller itself). 444 * @use_gpio_descriptors: Turns on the code in the SPI core to parse and grab 445 * GPIO descriptors. This will fill in @cs_gpiods and SPI devices will have 446 * the cs_gpiod assigned if a GPIO line is found for the chipselect. 447 * @unused_native_cs: When cs_gpiods is used, spi_register_controller() will 448 * fill in this field with the first unused native CS, to be used by SPI 449 * controller drivers that need to drive a native CS when using GPIO CS. 450 * @max_native_cs: When cs_gpiods is used, and this field is filled in, 451 * spi_register_controller() will validate all native CS (including the 452 * unused native CS) against this value. 453 * @pcpu_statistics: statistics for the spi_controller 454 * @dma_tx: DMA transmit channel 455 * @dma_rx: DMA receive channel 456 * @dummy_rx: dummy receive buffer for full-duplex devices 457 * @dummy_tx: dummy transmit buffer for full-duplex devices 458 * @fw_translate_cs: If the boot firmware uses different numbering scheme 459 * what Linux expects, this optional hook can be used to translate 460 * between the two. 461 * @ptp_sts_supported: If the driver sets this to true, it must provide a 462 * time snapshot in @spi_transfer->ptp_sts as close as possible to the 463 * moment in time when @spi_transfer->ptp_sts_word_pre and 464 * @spi_transfer->ptp_sts_word_post were transmitted. 465 * If the driver does not set this, the SPI core takes the snapshot as 466 * close to the driver hand-over as possible. 467 * @irq_flags: Interrupt enable state during PTP system timestamping 468 * @fallback: fallback to pio if dma transfer return failure with 469 * SPI_TRANS_FAIL_NO_START. 470 * @queue_empty: signal green light for opportunistically skipping the queue 471 * for spi_sync transfers. 472 * 473 * Each SPI controller can communicate with one or more @spi_device 474 * children. These make a small bus, sharing MOSI, MISO and SCK signals 475 * but not chip select signals. Each device may be configured to use a 476 * different clock rate, since those shared signals are ignored unless 477 * the chip is selected. 478 * 479 * The driver for an SPI controller manages access to those devices through 480 * a queue of spi_message transactions, copying data between CPU memory and 481 * an SPI slave device. For each such message it queues, it calls the 482 * message's completion function when the transaction completes. 483 */ 484 struct spi_controller { 485 struct device dev; 486 487 struct list_head list; 488 489 /* Other than negative (== assign one dynamically), bus_num is fully 490 * board-specific. usually that simplifies to being SOC-specific. 491 * example: one SOC has three SPI controllers, numbered 0..2, 492 * and one board's schematics might show it using SPI-2. software 493 * would normally use bus_num=2 for that controller. 494 */ 495 s16 bus_num; 496 497 /* chipselects will be integral to many controllers; some others 498 * might use board-specific GPIOs. 499 */ 500 u16 num_chipselect; 501 502 /* Some SPI controllers pose alignment requirements on DMAable 503 * buffers; let protocol drivers know about these requirements. 504 */ 505 u16 dma_alignment; 506 507 /* spi_device.mode flags understood by this controller driver */ 508 u32 mode_bits; 509 510 /* spi_device.mode flags override flags for this controller */ 511 u32 buswidth_override_bits; 512 513 /* Bitmask of supported bits_per_word for transfers */ 514 u32 bits_per_word_mask; 515 #define SPI_BPW_MASK(bits) BIT((bits) - 1) 516 #define SPI_BPW_RANGE_MASK(min, max) GENMASK((max) - 1, (min) - 1) 517 518 /* Limits on transfer speed */ 519 u32 min_speed_hz; 520 u32 max_speed_hz; 521 522 /* Other constraints relevant to this driver */ 523 u16 flags; 524 #define SPI_CONTROLLER_HALF_DUPLEX BIT(0) /* Can't do full duplex */ 525 #define SPI_CONTROLLER_NO_RX BIT(1) /* Can't do buffer read */ 526 #define SPI_CONTROLLER_NO_TX BIT(2) /* Can't do buffer write */ 527 #define SPI_CONTROLLER_MUST_RX BIT(3) /* Requires rx */ 528 #define SPI_CONTROLLER_MUST_TX BIT(4) /* Requires tx */ 529 530 #define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS must select slave */ 531 532 /* Flag indicating if the allocation of this struct is devres-managed */ 533 bool devm_allocated; 534 535 /* Flag indicating this is an SPI slave controller */ 536 bool slave; 537 538 /* 539 * on some hardware transfer / message size may be constrained 540 * the limit may depend on device transfer settings 541 */ 542 size_t (*max_transfer_size)(struct spi_device *spi); 543 size_t (*max_message_size)(struct spi_device *spi); 544 545 /* I/O mutex */ 546 struct mutex io_mutex; 547 548 /* Used to avoid adding the same CS twice */ 549 struct mutex add_lock; 550 551 /* Lock and mutex for SPI bus locking */ 552 spinlock_t bus_lock_spinlock; 553 struct mutex bus_lock_mutex; 554 555 /* Flag indicating that the SPI bus is locked for exclusive use */ 556 bool bus_lock_flag; 557 558 /* Setup mode and clock, etc (spi driver may call many times). 559 * 560 * IMPORTANT: this may be called when transfers to another 561 * device are active. DO NOT UPDATE SHARED REGISTERS in ways 562 * which could break those transfers. 563 */ 564 int (*setup)(struct spi_device *spi); 565 566 /* 567 * set_cs_timing() method is for SPI controllers that supports 568 * configuring CS timing. 569 * 570 * This hook allows SPI client drivers to request SPI controllers 571 * to configure specific CS timing through spi_set_cs_timing() after 572 * spi_setup(). 573 */ 574 int (*set_cs_timing)(struct spi_device *spi); 575 576 /* Bidirectional bulk transfers 577 * 578 * + The transfer() method may not sleep; its main role is 579 * just to add the message to the queue. 580 * + For now there's no remove-from-queue operation, or 581 * any other request management 582 * + To a given spi_device, message queueing is pure fifo 583 * 584 * + The controller's main job is to process its message queue, 585 * selecting a chip (for masters), then transferring data 586 * + If there are multiple spi_device children, the i/o queue 587 * arbitration algorithm is unspecified (round robin, fifo, 588 * priority, reservations, preemption, etc) 589 * 590 * + Chipselect stays active during the entire message 591 * (unless modified by spi_transfer.cs_change != 0). 592 * + The message transfers use clock and SPI mode parameters 593 * previously established by setup() for this device 594 */ 595 int (*transfer)(struct spi_device *spi, 596 struct spi_message *mesg); 597 598 /* Called on release() to free memory provided by spi_controller */ 599 void (*cleanup)(struct spi_device *spi); 600 601 /* 602 * Used to enable core support for DMA handling, if can_dma() 603 * exists and returns true then the transfer will be mapped 604 * prior to transfer_one() being called. The driver should 605 * not modify or store xfer and dma_tx and dma_rx must be set 606 * while the device is prepared. 607 */ 608 bool (*can_dma)(struct spi_controller *ctlr, 609 struct spi_device *spi, 610 struct spi_transfer *xfer); 611 struct device *dma_map_dev; 612 613 /* 614 * These hooks are for drivers that want to use the generic 615 * controller transfer queueing mechanism. If these are used, the 616 * transfer() function above must NOT be specified by the driver. 617 * Over time we expect SPI drivers to be phased over to this API. 618 */ 619 bool queued; 620 struct kthread_worker *kworker; 621 struct kthread_work pump_messages; 622 spinlock_t queue_lock; 623 struct list_head queue; 624 struct spi_message *cur_msg; 625 struct completion cur_msg_completion; 626 bool cur_msg_incomplete; 627 bool cur_msg_need_completion; 628 bool busy; 629 bool running; 630 bool rt; 631 bool auto_runtime_pm; 632 bool cur_msg_mapped; 633 char last_cs; 634 bool last_cs_mode_high; 635 bool fallback; 636 struct completion xfer_completion; 637 size_t max_dma_len; 638 639 int (*prepare_transfer_hardware)(struct spi_controller *ctlr); 640 int (*transfer_one_message)(struct spi_controller *ctlr, 641 struct spi_message *mesg); 642 int (*unprepare_transfer_hardware)(struct spi_controller *ctlr); 643 int (*prepare_message)(struct spi_controller *ctlr, 644 struct spi_message *message); 645 int (*unprepare_message)(struct spi_controller *ctlr, 646 struct spi_message *message); 647 int (*slave_abort)(struct spi_controller *ctlr); 648 649 /* 650 * These hooks are for drivers that use a generic implementation 651 * of transfer_one_message() provided by the core. 652 */ 653 void (*set_cs)(struct spi_device *spi, bool enable); 654 int (*transfer_one)(struct spi_controller *ctlr, struct spi_device *spi, 655 struct spi_transfer *transfer); 656 void (*handle_err)(struct spi_controller *ctlr, 657 struct spi_message *message); 658 659 /* Optimized handlers for SPI memory-like operations. */ 660 const struct spi_controller_mem_ops *mem_ops; 661 const struct spi_controller_mem_caps *mem_caps; 662 663 /* gpio chip select */ 664 struct gpio_desc **cs_gpiods; 665 bool use_gpio_descriptors; 666 s8 unused_native_cs; 667 s8 max_native_cs; 668 669 /* Statistics */ 670 struct spi_statistics __percpu *pcpu_statistics; 671 672 /* DMA channels for use with core dmaengine helpers */ 673 struct dma_chan *dma_tx; 674 struct dma_chan *dma_rx; 675 676 /* Dummy data for full duplex devices */ 677 void *dummy_rx; 678 void *dummy_tx; 679 680 int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs); 681 682 /* 683 * Driver sets this field to indicate it is able to snapshot SPI 684 * transfers (needed e.g. for reading the time of POSIX clocks) 685 */ 686 bool ptp_sts_supported; 687 688 /* Interrupt enable state during PTP system timestamping */ 689 unsigned long irq_flags; 690 691 /* Flag for enabling opportunistic skipping of the queue in spi_sync */ 692 bool queue_empty; 693 }; 694 695 static inline void *spi_controller_get_devdata(struct spi_controller *ctlr) 696 { 697 return dev_get_drvdata(&ctlr->dev); 698 } 699 700 static inline void spi_controller_set_devdata(struct spi_controller *ctlr, 701 void *data) 702 { 703 dev_set_drvdata(&ctlr->dev, data); 704 } 705 706 static inline struct spi_controller *spi_controller_get(struct spi_controller *ctlr) 707 { 708 if (!ctlr || !get_device(&ctlr->dev)) 709 return NULL; 710 return ctlr; 711 } 712 713 static inline void spi_controller_put(struct spi_controller *ctlr) 714 { 715 if (ctlr) 716 put_device(&ctlr->dev); 717 } 718 719 static inline bool spi_controller_is_slave(struct spi_controller *ctlr) 720 { 721 return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->slave; 722 } 723 724 /* PM calls that need to be issued by the driver */ 725 extern int spi_controller_suspend(struct spi_controller *ctlr); 726 extern int spi_controller_resume(struct spi_controller *ctlr); 727 728 /* Calls the driver make to interact with the message queue */ 729 extern struct spi_message *spi_get_next_queued_message(struct spi_controller *ctlr); 730 extern void spi_finalize_current_message(struct spi_controller *ctlr); 731 extern void spi_finalize_current_transfer(struct spi_controller *ctlr); 732 733 /* Helper calls for driver to timestamp transfer */ 734 void spi_take_timestamp_pre(struct spi_controller *ctlr, 735 struct spi_transfer *xfer, 736 size_t progress, bool irqs_off); 737 void spi_take_timestamp_post(struct spi_controller *ctlr, 738 struct spi_transfer *xfer, 739 size_t progress, bool irqs_off); 740 741 /* The spi driver core manages memory for the spi_controller classdev */ 742 extern struct spi_controller *__spi_alloc_controller(struct device *host, 743 unsigned int size, bool slave); 744 745 static inline struct spi_controller *spi_alloc_master(struct device *host, 746 unsigned int size) 747 { 748 return __spi_alloc_controller(host, size, false); 749 } 750 751 static inline struct spi_controller *spi_alloc_slave(struct device *host, 752 unsigned int size) 753 { 754 if (!IS_ENABLED(CONFIG_SPI_SLAVE)) 755 return NULL; 756 757 return __spi_alloc_controller(host, size, true); 758 } 759 760 struct spi_controller *__devm_spi_alloc_controller(struct device *dev, 761 unsigned int size, 762 bool slave); 763 764 static inline struct spi_controller *devm_spi_alloc_master(struct device *dev, 765 unsigned int size) 766 { 767 return __devm_spi_alloc_controller(dev, size, false); 768 } 769 770 static inline struct spi_controller *devm_spi_alloc_slave(struct device *dev, 771 unsigned int size) 772 { 773 if (!IS_ENABLED(CONFIG_SPI_SLAVE)) 774 return NULL; 775 776 return __devm_spi_alloc_controller(dev, size, true); 777 } 778 779 extern int spi_register_controller(struct spi_controller *ctlr); 780 extern int devm_spi_register_controller(struct device *dev, 781 struct spi_controller *ctlr); 782 extern void spi_unregister_controller(struct spi_controller *ctlr); 783 784 #if IS_ENABLED(CONFIG_ACPI) 785 extern struct spi_device *acpi_spi_device_alloc(struct spi_controller *ctlr, 786 struct acpi_device *adev, 787 int index); 788 int acpi_spi_count_resources(struct acpi_device *adev); 789 #endif 790 791 /* 792 * SPI resource management while processing a SPI message 793 */ 794 795 typedef void (*spi_res_release_t)(struct spi_controller *ctlr, 796 struct spi_message *msg, 797 void *res); 798 799 /** 800 * struct spi_res - spi resource management structure 801 * @entry: list entry 802 * @release: release code called prior to freeing this resource 803 * @data: extra data allocated for the specific use-case 804 * 805 * this is based on ideas from devres, but focused on life-cycle 806 * management during spi_message processing 807 */ 808 struct spi_res { 809 struct list_head entry; 810 spi_res_release_t release; 811 unsigned long long data[]; /* Guarantee ull alignment */ 812 }; 813 814 /*---------------------------------------------------------------------------*/ 815 816 /* 817 * I/O INTERFACE between SPI controller and protocol drivers 818 * 819 * Protocol drivers use a queue of spi_messages, each transferring data 820 * between the controller and memory buffers. 821 * 822 * The spi_messages themselves consist of a series of read+write transfer 823 * segments. Those segments always read the same number of bits as they 824 * write; but one or the other is easily ignored by passing a null buffer 825 * pointer. (This is unlike most types of I/O API, because SPI hardware 826 * is full duplex.) 827 * 828 * NOTE: Allocation of spi_transfer and spi_message memory is entirely 829 * up to the protocol driver, which guarantees the integrity of both (as 830 * well as the data buffers) for as long as the message is queued. 831 */ 832 833 /** 834 * struct spi_transfer - a read/write buffer pair 835 * @tx_buf: data to be written (dma-safe memory), or NULL 836 * @rx_buf: data to be read (dma-safe memory), or NULL 837 * @tx_dma: DMA address of tx_buf, if @spi_message.is_dma_mapped 838 * @rx_dma: DMA address of rx_buf, if @spi_message.is_dma_mapped 839 * @tx_nbits: number of bits used for writing. If 0 the default 840 * (SPI_NBITS_SINGLE) is used. 841 * @rx_nbits: number of bits used for reading. If 0 the default 842 * (SPI_NBITS_SINGLE) is used. 843 * @len: size of rx and tx buffers (in bytes) 844 * @speed_hz: Select a speed other than the device default for this 845 * transfer. If 0 the default (from @spi_device) is used. 846 * @bits_per_word: select a bits_per_word other than the device default 847 * for this transfer. If 0 the default (from @spi_device) is used. 848 * @dummy_data: indicates transfer is dummy bytes transfer. 849 * @cs_change: affects chipselect after this transfer completes 850 * @cs_change_delay: delay between cs deassert and assert when 851 * @cs_change is set and @spi_transfer is not the last in @spi_message 852 * @delay: delay to be introduced after this transfer before 853 * (optionally) changing the chipselect status, then starting 854 * the next transfer or completing this @spi_message. 855 * @word_delay: inter word delay to be introduced after each word size 856 * (set by bits_per_word) transmission. 857 * @effective_speed_hz: the effective SCK-speed that was used to 858 * transfer this transfer. Set to 0 if the spi bus driver does 859 * not support it. 860 * @transfer_list: transfers are sequenced through @spi_message.transfers 861 * @tx_sg: Scatterlist for transmit, currently not for client use 862 * @rx_sg: Scatterlist for receive, currently not for client use 863 * @ptp_sts_word_pre: The word (subject to bits_per_word semantics) offset 864 * within @tx_buf for which the SPI device is requesting that the time 865 * snapshot for this transfer begins. Upon completing the SPI transfer, 866 * this value may have changed compared to what was requested, depending 867 * on the available snapshotting resolution (DMA transfer, 868 * @ptp_sts_supported is false, etc). 869 * @ptp_sts_word_post: See @ptp_sts_word_post. The two can be equal (meaning 870 * that a single byte should be snapshotted). 871 * If the core takes care of the timestamp (if @ptp_sts_supported is false 872 * for this controller), it will set @ptp_sts_word_pre to 0, and 873 * @ptp_sts_word_post to the length of the transfer. This is done 874 * purposefully (instead of setting to spi_transfer->len - 1) to denote 875 * that a transfer-level snapshot taken from within the driver may still 876 * be of higher quality. 877 * @ptp_sts: Pointer to a memory location held by the SPI slave device where a 878 * PTP system timestamp structure may lie. If drivers use PIO or their 879 * hardware has some sort of assist for retrieving exact transfer timing, 880 * they can (and should) assert @ptp_sts_supported and populate this 881 * structure using the ptp_read_system_*ts helper functions. 882 * The timestamp must represent the time at which the SPI slave device has 883 * processed the word, i.e. the "pre" timestamp should be taken before 884 * transmitting the "pre" word, and the "post" timestamp after receiving 885 * transmit confirmation from the controller for the "post" word. 886 * @timestamped: true if the transfer has been timestamped 887 * @error: Error status logged by spi controller driver. 888 * 889 * SPI transfers always write the same number of bytes as they read. 890 * Protocol drivers should always provide @rx_buf and/or @tx_buf. 891 * In some cases, they may also want to provide DMA addresses for 892 * the data being transferred; that may reduce overhead, when the 893 * underlying driver uses dma. 894 * 895 * If the transmit buffer is null, zeroes will be shifted out 896 * while filling @rx_buf. If the receive buffer is null, the data 897 * shifted in will be discarded. Only "len" bytes shift out (or in). 898 * It's an error to try to shift out a partial word. (For example, by 899 * shifting out three bytes with word size of sixteen or twenty bits; 900 * the former uses two bytes per word, the latter uses four bytes.) 901 * 902 * In-memory data values are always in native CPU byte order, translated 903 * from the wire byte order (big-endian except with SPI_LSB_FIRST). So 904 * for example when bits_per_word is sixteen, buffers are 2N bytes long 905 * (@len = 2N) and hold N sixteen bit words in CPU byte order. 906 * 907 * When the word size of the SPI transfer is not a power-of-two multiple 908 * of eight bits, those in-memory words include extra bits. In-memory 909 * words are always seen by protocol drivers as right-justified, so the 910 * undefined (rx) or unused (tx) bits are always the most significant bits. 911 * 912 * All SPI transfers start with the relevant chipselect active. Normally 913 * it stays selected until after the last transfer in a message. Drivers 914 * can affect the chipselect signal using cs_change. 915 * 916 * (i) If the transfer isn't the last one in the message, this flag is 917 * used to make the chipselect briefly go inactive in the middle of the 918 * message. Toggling chipselect in this way may be needed to terminate 919 * a chip command, letting a single spi_message perform all of group of 920 * chip transactions together. 921 * 922 * (ii) When the transfer is the last one in the message, the chip may 923 * stay selected until the next transfer. On multi-device SPI busses 924 * with nothing blocking messages going to other devices, this is just 925 * a performance hint; starting a message to another device deselects 926 * this one. But in other cases, this can be used to ensure correctness. 927 * Some devices need protocol transactions to be built from a series of 928 * spi_message submissions, where the content of one message is determined 929 * by the results of previous messages and where the whole transaction 930 * ends when the chipselect goes intactive. 931 * 932 * When SPI can transfer in 1x,2x or 4x. It can get this transfer information 933 * from device through @tx_nbits and @rx_nbits. In Bi-direction, these 934 * two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x) 935 * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer. 936 * 937 * The code that submits an spi_message (and its spi_transfers) 938 * to the lower layers is responsible for managing its memory. 939 * Zero-initialize every field you don't set up explicitly, to 940 * insulate against future API updates. After you submit a message 941 * and its transfers, ignore them until its completion callback. 942 */ 943 struct spi_transfer { 944 /* It's ok if tx_buf == rx_buf (right?) 945 * for MicroWire, one buffer must be null 946 * buffers must work with dma_*map_single() calls, unless 947 * spi_message.is_dma_mapped reports a pre-existing mapping 948 */ 949 const void *tx_buf; 950 void *rx_buf; 951 unsigned len; 952 953 dma_addr_t tx_dma; 954 dma_addr_t rx_dma; 955 struct sg_table tx_sg; 956 struct sg_table rx_sg; 957 958 unsigned dummy_data:1; 959 unsigned cs_change:1; 960 unsigned tx_nbits:3; 961 unsigned rx_nbits:3; 962 #define SPI_NBITS_SINGLE 0x01 /* 1bit transfer */ 963 #define SPI_NBITS_DUAL 0x02 /* 2bits transfer */ 964 #define SPI_NBITS_QUAD 0x04 /* 4bits transfer */ 965 u8 bits_per_word; 966 struct spi_delay delay; 967 struct spi_delay cs_change_delay; 968 struct spi_delay word_delay; 969 u32 speed_hz; 970 971 u32 effective_speed_hz; 972 973 unsigned int ptp_sts_word_pre; 974 unsigned int ptp_sts_word_post; 975 976 struct ptp_system_timestamp *ptp_sts; 977 978 bool timestamped; 979 980 struct list_head transfer_list; 981 982 #define SPI_TRANS_FAIL_NO_START BIT(0) 983 u16 error; 984 }; 985 986 /** 987 * struct spi_message - one multi-segment SPI transaction 988 * @transfers: list of transfer segments in this transaction 989 * @spi: SPI device to which the transaction is queued 990 * @is_dma_mapped: if true, the caller provided both dma and cpu virtual 991 * addresses for each transfer buffer 992 * @complete: called to report transaction completions 993 * @context: the argument to complete() when it's called 994 * @frame_length: the total number of bytes in the message 995 * @actual_length: the total number of bytes that were transferred in all 996 * successful segments 997 * @status: zero for success, else negative errno 998 * @queue: for use by whichever driver currently owns the message 999 * @state: for use by whichever driver currently owns the message 1000 * @resources: for resource management when the spi message is processed 1001 * @prepared: spi_prepare_message was called for the this message 1002 * 1003 * A @spi_message is used to execute an atomic sequence of data transfers, 1004 * each represented by a struct spi_transfer. The sequence is "atomic" 1005 * in the sense that no other spi_message may use that SPI bus until that 1006 * sequence completes. On some systems, many such sequences can execute as 1007 * a single programmed DMA transfer. On all systems, these messages are 1008 * queued, and might complete after transactions to other devices. Messages 1009 * sent to a given spi_device are always executed in FIFO order. 1010 * 1011 * The code that submits an spi_message (and its spi_transfers) 1012 * to the lower layers is responsible for managing its memory. 1013 * Zero-initialize every field you don't set up explicitly, to 1014 * insulate against future API updates. After you submit a message 1015 * and its transfers, ignore them until its completion callback. 1016 */ 1017 struct spi_message { 1018 struct list_head transfers; 1019 1020 struct spi_device *spi; 1021 1022 unsigned is_dma_mapped:1; 1023 1024 /* REVISIT: we might want a flag affecting the behavior of the 1025 * last transfer ... allowing things like "read 16 bit length L" 1026 * immediately followed by "read L bytes". Basically imposing 1027 * a specific message scheduling algorithm. 1028 * 1029 * Some controller drivers (message-at-a-time queue processing) 1030 * could provide that as their default scheduling algorithm. But 1031 * others (with multi-message pipelines) could need a flag to 1032 * tell them about such special cases. 1033 */ 1034 1035 /* Completion is reported through a callback */ 1036 void (*complete)(void *context); 1037 void *context; 1038 unsigned frame_length; 1039 unsigned actual_length; 1040 int status; 1041 1042 /* For optional use by whatever driver currently owns the 1043 * spi_message ... between calls to spi_async and then later 1044 * complete(), that's the spi_controller controller driver. 1045 */ 1046 struct list_head queue; 1047 void *state; 1048 1049 /* List of spi_res reources when the spi message is processed */ 1050 struct list_head resources; 1051 1052 /* spi_prepare_message() was called for this message */ 1053 bool prepared; 1054 }; 1055 1056 static inline void spi_message_init_no_memset(struct spi_message *m) 1057 { 1058 INIT_LIST_HEAD(&m->transfers); 1059 INIT_LIST_HEAD(&m->resources); 1060 } 1061 1062 static inline void spi_message_init(struct spi_message *m) 1063 { 1064 memset(m, 0, sizeof *m); 1065 spi_message_init_no_memset(m); 1066 } 1067 1068 static inline void 1069 spi_message_add_tail(struct spi_transfer *t, struct spi_message *m) 1070 { 1071 list_add_tail(&t->transfer_list, &m->transfers); 1072 } 1073 1074 static inline void 1075 spi_transfer_del(struct spi_transfer *t) 1076 { 1077 list_del(&t->transfer_list); 1078 } 1079 1080 static inline int 1081 spi_transfer_delay_exec(struct spi_transfer *t) 1082 { 1083 return spi_delay_exec(&t->delay, t); 1084 } 1085 1086 /** 1087 * spi_message_init_with_transfers - Initialize spi_message and append transfers 1088 * @m: spi_message to be initialized 1089 * @xfers: An array of spi transfers 1090 * @num_xfers: Number of items in the xfer array 1091 * 1092 * This function initializes the given spi_message and adds each spi_transfer in 1093 * the given array to the message. 1094 */ 1095 static inline void 1096 spi_message_init_with_transfers(struct spi_message *m, 1097 struct spi_transfer *xfers, unsigned int num_xfers) 1098 { 1099 unsigned int i; 1100 1101 spi_message_init(m); 1102 for (i = 0; i < num_xfers; ++i) 1103 spi_message_add_tail(&xfers[i], m); 1104 } 1105 1106 /* It's fine to embed message and transaction structures in other data 1107 * structures so long as you don't free them while they're in use. 1108 */ 1109 1110 static inline struct spi_message *spi_message_alloc(unsigned ntrans, gfp_t flags) 1111 { 1112 struct spi_message *m; 1113 1114 m = kzalloc(sizeof(struct spi_message) 1115 + ntrans * sizeof(struct spi_transfer), 1116 flags); 1117 if (m) { 1118 unsigned i; 1119 struct spi_transfer *t = (struct spi_transfer *)(m + 1); 1120 1121 spi_message_init_no_memset(m); 1122 for (i = 0; i < ntrans; i++, t++) 1123 spi_message_add_tail(t, m); 1124 } 1125 return m; 1126 } 1127 1128 static inline void spi_message_free(struct spi_message *m) 1129 { 1130 kfree(m); 1131 } 1132 1133 extern int spi_setup(struct spi_device *spi); 1134 extern int spi_async(struct spi_device *spi, struct spi_message *message); 1135 extern int spi_slave_abort(struct spi_device *spi); 1136 1137 static inline size_t 1138 spi_max_message_size(struct spi_device *spi) 1139 { 1140 struct spi_controller *ctlr = spi->controller; 1141 1142 if (!ctlr->max_message_size) 1143 return SIZE_MAX; 1144 return ctlr->max_message_size(spi); 1145 } 1146 1147 static inline size_t 1148 spi_max_transfer_size(struct spi_device *spi) 1149 { 1150 struct spi_controller *ctlr = spi->controller; 1151 size_t tr_max = SIZE_MAX; 1152 size_t msg_max = spi_max_message_size(spi); 1153 1154 if (ctlr->max_transfer_size) 1155 tr_max = ctlr->max_transfer_size(spi); 1156 1157 /* Transfer size limit must not be greater than message size limit */ 1158 return min(tr_max, msg_max); 1159 } 1160 1161 /** 1162 * spi_is_bpw_supported - Check if bits per word is supported 1163 * @spi: SPI device 1164 * @bpw: Bits per word 1165 * 1166 * This function checks to see if the SPI controller supports @bpw. 1167 * 1168 * Returns: 1169 * True if @bpw is supported, false otherwise. 1170 */ 1171 static inline bool spi_is_bpw_supported(struct spi_device *spi, u32 bpw) 1172 { 1173 u32 bpw_mask = spi->master->bits_per_word_mask; 1174 1175 if (bpw == 8 || (bpw <= 32 && bpw_mask & SPI_BPW_MASK(bpw))) 1176 return true; 1177 1178 return false; 1179 } 1180 1181 /*---------------------------------------------------------------------------*/ 1182 1183 /* SPI transfer replacement methods which make use of spi_res */ 1184 1185 struct spi_replaced_transfers; 1186 typedef void (*spi_replaced_release_t)(struct spi_controller *ctlr, 1187 struct spi_message *msg, 1188 struct spi_replaced_transfers *res); 1189 /** 1190 * struct spi_replaced_transfers - structure describing the spi_transfer 1191 * replacements that have occurred 1192 * so that they can get reverted 1193 * @release: some extra release code to get executed prior to 1194 * relasing this structure 1195 * @extradata: pointer to some extra data if requested or NULL 1196 * @replaced_transfers: transfers that have been replaced and which need 1197 * to get restored 1198 * @replaced_after: the transfer after which the @replaced_transfers 1199 * are to get re-inserted 1200 * @inserted: number of transfers inserted 1201 * @inserted_transfers: array of spi_transfers of array-size @inserted, 1202 * that have been replacing replaced_transfers 1203 * 1204 * note: that @extradata will point to @inserted_transfers[@inserted] 1205 * if some extra allocation is requested, so alignment will be the same 1206 * as for spi_transfers 1207 */ 1208 struct spi_replaced_transfers { 1209 spi_replaced_release_t release; 1210 void *extradata; 1211 struct list_head replaced_transfers; 1212 struct list_head *replaced_after; 1213 size_t inserted; 1214 struct spi_transfer inserted_transfers[]; 1215 }; 1216 1217 /*---------------------------------------------------------------------------*/ 1218 1219 /* SPI transfer transformation methods */ 1220 1221 extern int spi_split_transfers_maxsize(struct spi_controller *ctlr, 1222 struct spi_message *msg, 1223 size_t maxsize, 1224 gfp_t gfp); 1225 1226 /*---------------------------------------------------------------------------*/ 1227 1228 /* All these synchronous SPI transfer routines are utilities layered 1229 * over the core async transfer primitive. Here, "synchronous" means 1230 * they will sleep uninterruptibly until the async transfer completes. 1231 */ 1232 1233 extern int spi_sync(struct spi_device *spi, struct spi_message *message); 1234 extern int spi_sync_locked(struct spi_device *spi, struct spi_message *message); 1235 extern int spi_bus_lock(struct spi_controller *ctlr); 1236 extern int spi_bus_unlock(struct spi_controller *ctlr); 1237 1238 /** 1239 * spi_sync_transfer - synchronous SPI data transfer 1240 * @spi: device with which data will be exchanged 1241 * @xfers: An array of spi_transfers 1242 * @num_xfers: Number of items in the xfer array 1243 * Context: can sleep 1244 * 1245 * Does a synchronous SPI data transfer of the given spi_transfer array. 1246 * 1247 * For more specific semantics see spi_sync(). 1248 * 1249 * Return: zero on success, else a negative error code. 1250 */ 1251 static inline int 1252 spi_sync_transfer(struct spi_device *spi, struct spi_transfer *xfers, 1253 unsigned int num_xfers) 1254 { 1255 struct spi_message msg; 1256 1257 spi_message_init_with_transfers(&msg, xfers, num_xfers); 1258 1259 return spi_sync(spi, &msg); 1260 } 1261 1262 /** 1263 * spi_write - SPI synchronous write 1264 * @spi: device to which data will be written 1265 * @buf: data buffer 1266 * @len: data buffer size 1267 * Context: can sleep 1268 * 1269 * This function writes the buffer @buf. 1270 * Callable only from contexts that can sleep. 1271 * 1272 * Return: zero on success, else a negative error code. 1273 */ 1274 static inline int 1275 spi_write(struct spi_device *spi, const void *buf, size_t len) 1276 { 1277 struct spi_transfer t = { 1278 .tx_buf = buf, 1279 .len = len, 1280 }; 1281 1282 return spi_sync_transfer(spi, &t, 1); 1283 } 1284 1285 /** 1286 * spi_read - SPI synchronous read 1287 * @spi: device from which data will be read 1288 * @buf: data buffer 1289 * @len: data buffer size 1290 * Context: can sleep 1291 * 1292 * This function reads the buffer @buf. 1293 * Callable only from contexts that can sleep. 1294 * 1295 * Return: zero on success, else a negative error code. 1296 */ 1297 static inline int 1298 spi_read(struct spi_device *spi, void *buf, size_t len) 1299 { 1300 struct spi_transfer t = { 1301 .rx_buf = buf, 1302 .len = len, 1303 }; 1304 1305 return spi_sync_transfer(spi, &t, 1); 1306 } 1307 1308 /* This copies txbuf and rxbuf data; for small transfers only! */ 1309 extern int spi_write_then_read(struct spi_device *spi, 1310 const void *txbuf, unsigned n_tx, 1311 void *rxbuf, unsigned n_rx); 1312 1313 /** 1314 * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read 1315 * @spi: device with which data will be exchanged 1316 * @cmd: command to be written before data is read back 1317 * Context: can sleep 1318 * 1319 * Callable only from contexts that can sleep. 1320 * 1321 * Return: the (unsigned) eight bit number returned by the 1322 * device, or else a negative error code. 1323 */ 1324 static inline ssize_t spi_w8r8(struct spi_device *spi, u8 cmd) 1325 { 1326 ssize_t status; 1327 u8 result; 1328 1329 status = spi_write_then_read(spi, &cmd, 1, &result, 1); 1330 1331 /* Return negative errno or unsigned value */ 1332 return (status < 0) ? status : result; 1333 } 1334 1335 /** 1336 * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read 1337 * @spi: device with which data will be exchanged 1338 * @cmd: command to be written before data is read back 1339 * Context: can sleep 1340 * 1341 * The number is returned in wire-order, which is at least sometimes 1342 * big-endian. 1343 * 1344 * Callable only from contexts that can sleep. 1345 * 1346 * Return: the (unsigned) sixteen bit number returned by the 1347 * device, or else a negative error code. 1348 */ 1349 static inline ssize_t spi_w8r16(struct spi_device *spi, u8 cmd) 1350 { 1351 ssize_t status; 1352 u16 result; 1353 1354 status = spi_write_then_read(spi, &cmd, 1, &result, 2); 1355 1356 /* Return negative errno or unsigned value */ 1357 return (status < 0) ? status : result; 1358 } 1359 1360 /** 1361 * spi_w8r16be - SPI synchronous 8 bit write followed by 16 bit big-endian read 1362 * @spi: device with which data will be exchanged 1363 * @cmd: command to be written before data is read back 1364 * Context: can sleep 1365 * 1366 * This function is similar to spi_w8r16, with the exception that it will 1367 * convert the read 16 bit data word from big-endian to native endianness. 1368 * 1369 * Callable only from contexts that can sleep. 1370 * 1371 * Return: the (unsigned) sixteen bit number returned by the device in cpu 1372 * endianness, or else a negative error code. 1373 */ 1374 static inline ssize_t spi_w8r16be(struct spi_device *spi, u8 cmd) 1375 1376 { 1377 ssize_t status; 1378 __be16 result; 1379 1380 status = spi_write_then_read(spi, &cmd, 1, &result, 2); 1381 if (status < 0) 1382 return status; 1383 1384 return be16_to_cpu(result); 1385 } 1386 1387 /*---------------------------------------------------------------------------*/ 1388 1389 /* 1390 * INTERFACE between board init code and SPI infrastructure. 1391 * 1392 * No SPI driver ever sees these SPI device table segments, but 1393 * it's how the SPI core (or adapters that get hotplugged) grows 1394 * the driver model tree. 1395 * 1396 * As a rule, SPI devices can't be probed. Instead, board init code 1397 * provides a table listing the devices which are present, with enough 1398 * information to bind and set up the device's driver. There's basic 1399 * support for nonstatic configurations too; enough to handle adding 1400 * parport adapters, or microcontrollers acting as USB-to-SPI bridges. 1401 */ 1402 1403 /** 1404 * struct spi_board_info - board-specific template for a SPI device 1405 * @modalias: Initializes spi_device.modalias; identifies the driver. 1406 * @platform_data: Initializes spi_device.platform_data; the particular 1407 * data stored there is driver-specific. 1408 * @swnode: Software node for the device. 1409 * @controller_data: Initializes spi_device.controller_data; some 1410 * controllers need hints about hardware setup, e.g. for DMA. 1411 * @irq: Initializes spi_device.irq; depends on how the board is wired. 1412 * @max_speed_hz: Initializes spi_device.max_speed_hz; based on limits 1413 * from the chip datasheet and board-specific signal quality issues. 1414 * @bus_num: Identifies which spi_controller parents the spi_device; unused 1415 * by spi_new_device(), and otherwise depends on board wiring. 1416 * @chip_select: Initializes spi_device.chip_select; depends on how 1417 * the board is wired. 1418 * @mode: Initializes spi_device.mode; based on the chip datasheet, board 1419 * wiring (some devices support both 3WIRE and standard modes), and 1420 * possibly presence of an inverter in the chipselect path. 1421 * 1422 * When adding new SPI devices to the device tree, these structures serve 1423 * as a partial device template. They hold information which can't always 1424 * be determined by drivers. Information that probe() can establish (such 1425 * as the default transfer wordsize) is not included here. 1426 * 1427 * These structures are used in two places. Their primary role is to 1428 * be stored in tables of board-specific device descriptors, which are 1429 * declared early in board initialization and then used (much later) to 1430 * populate a controller's device tree after the that controller's driver 1431 * initializes. A secondary (and atypical) role is as a parameter to 1432 * spi_new_device() call, which happens after those controller drivers 1433 * are active in some dynamic board configuration models. 1434 */ 1435 struct spi_board_info { 1436 /* The device name and module name are coupled, like platform_bus; 1437 * "modalias" is normally the driver name. 1438 * 1439 * platform_data goes to spi_device.dev.platform_data, 1440 * controller_data goes to spi_device.controller_data, 1441 * irq is copied too 1442 */ 1443 char modalias[SPI_NAME_SIZE]; 1444 const void *platform_data; 1445 const struct software_node *swnode; 1446 void *controller_data; 1447 int irq; 1448 1449 /* Slower signaling on noisy or low voltage boards */ 1450 u32 max_speed_hz; 1451 1452 1453 /* bus_num is board specific and matches the bus_num of some 1454 * spi_controller that will probably be registered later. 1455 * 1456 * chip_select reflects how this chip is wired to that master; 1457 * it's less than num_chipselect. 1458 */ 1459 u16 bus_num; 1460 u16 chip_select; 1461 1462 /* mode becomes spi_device.mode, and is essential for chips 1463 * where the default of SPI_CS_HIGH = 0 is wrong. 1464 */ 1465 u32 mode; 1466 1467 /* ... may need additional spi_device chip config data here. 1468 * avoid stuff protocol drivers can set; but include stuff 1469 * needed to behave without being bound to a driver: 1470 * - quirks like clock rate mattering when not selected 1471 */ 1472 }; 1473 1474 #ifdef CONFIG_SPI 1475 extern int 1476 spi_register_board_info(struct spi_board_info const *info, unsigned n); 1477 #else 1478 /* Board init code may ignore whether SPI is configured or not */ 1479 static inline int 1480 spi_register_board_info(struct spi_board_info const *info, unsigned n) 1481 { return 0; } 1482 #endif 1483 1484 /* If you're hotplugging an adapter with devices (parport, usb, etc) 1485 * use spi_new_device() to describe each device. You can also call 1486 * spi_unregister_device() to start making that device vanish, but 1487 * normally that would be handled by spi_unregister_controller(). 1488 * 1489 * You can also use spi_alloc_device() and spi_add_device() to use a two 1490 * stage registration sequence for each spi_device. This gives the caller 1491 * some more control over the spi_device structure before it is registered, 1492 * but requires that caller to initialize fields that would otherwise 1493 * be defined using the board info. 1494 */ 1495 extern struct spi_device * 1496 spi_alloc_device(struct spi_controller *ctlr); 1497 1498 extern int 1499 spi_add_device(struct spi_device *spi); 1500 1501 extern struct spi_device * 1502 spi_new_device(struct spi_controller *, struct spi_board_info *); 1503 1504 extern void spi_unregister_device(struct spi_device *spi); 1505 1506 extern const struct spi_device_id * 1507 spi_get_device_id(const struct spi_device *sdev); 1508 1509 static inline bool 1510 spi_transfer_is_last(struct spi_controller *ctlr, struct spi_transfer *xfer) 1511 { 1512 return list_is_last(&xfer->transfer_list, &ctlr->cur_msg->transfers); 1513 } 1514 1515 /* Compatibility layer */ 1516 #define spi_master spi_controller 1517 1518 #define SPI_MASTER_HALF_DUPLEX SPI_CONTROLLER_HALF_DUPLEX 1519 #define SPI_MASTER_NO_RX SPI_CONTROLLER_NO_RX 1520 #define SPI_MASTER_NO_TX SPI_CONTROLLER_NO_TX 1521 #define SPI_MASTER_MUST_RX SPI_CONTROLLER_MUST_RX 1522 #define SPI_MASTER_MUST_TX SPI_CONTROLLER_MUST_TX 1523 1524 #define spi_master_get_devdata(_ctlr) spi_controller_get_devdata(_ctlr) 1525 #define spi_master_set_devdata(_ctlr, _data) \ 1526 spi_controller_set_devdata(_ctlr, _data) 1527 #define spi_master_get(_ctlr) spi_controller_get(_ctlr) 1528 #define spi_master_put(_ctlr) spi_controller_put(_ctlr) 1529 #define spi_master_suspend(_ctlr) spi_controller_suspend(_ctlr) 1530 #define spi_master_resume(_ctlr) spi_controller_resume(_ctlr) 1531 1532 #define spi_register_master(_ctlr) spi_register_controller(_ctlr) 1533 #define devm_spi_register_master(_dev, _ctlr) \ 1534 devm_spi_register_controller(_dev, _ctlr) 1535 #define spi_unregister_master(_ctlr) spi_unregister_controller(_ctlr) 1536 1537 #endif /* __LINUX_SPI_H */ 1538