1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2 /* Copyright(c) 2015-17 Intel Corporation. */ 3 4 #ifndef __SOUNDWIRE_H 5 #define __SOUNDWIRE_H 6 7 struct sdw_bus; 8 struct sdw_slave; 9 10 /* SDW spec defines and enums, as defined by MIPI 1.1. Spec */ 11 12 /* SDW Broadcast Device Number */ 13 #define SDW_BROADCAST_DEV_NUM 15 14 15 /* SDW Enumeration Device Number */ 16 #define SDW_ENUM_DEV_NUM 0 17 18 /* SDW Group Device Numbers */ 19 #define SDW_GROUP12_DEV_NUM 12 20 #define SDW_GROUP13_DEV_NUM 13 21 22 /* SDW Master Device Number, not supported yet */ 23 #define SDW_MASTER_DEV_NUM 14 24 25 #define SDW_NUM_DEV_ID_REGISTERS 6 26 /* frame shape defines */ 27 28 /* 29 * Note: The maximum row define in SoundWire spec 1.1 is 23. In order to 30 * fill hole with 0, one more dummy entry is added 31 */ 32 #define SDW_FRAME_ROWS 24 33 #define SDW_FRAME_COLS 8 34 #define SDW_FRAME_ROW_COLS (SDW_FRAME_ROWS * SDW_FRAME_COLS) 35 36 #define SDW_FRAME_CTRL_BITS 48 37 #define SDW_MAX_DEVICES 11 38 39 #define SDW_VALID_PORT_RANGE(n) ((n) <= 14 && (n) >= 1) 40 41 #define SDW_DAI_ID_RANGE_START 100 42 #define SDW_DAI_ID_RANGE_END 200 43 44 enum { 45 SDW_PORT_DIRN_SINK = 0, 46 SDW_PORT_DIRN_SOURCE, 47 SDW_PORT_DIRN_MAX, 48 }; 49 50 /* 51 * constants for flow control, ports and transport 52 * 53 * these are bit masks as devices can have multiple capabilities 54 */ 55 56 /* 57 * flow modes for SDW port. These can be isochronous, tx controlled, 58 * rx controlled or async 59 */ 60 #define SDW_PORT_FLOW_MODE_ISOCH 0 61 #define SDW_PORT_FLOW_MODE_TX_CNTRL BIT(0) 62 #define SDW_PORT_FLOW_MODE_RX_CNTRL BIT(1) 63 #define SDW_PORT_FLOW_MODE_ASYNC GENMASK(1, 0) 64 65 /* sample packaging for block. It can be per port or per channel */ 66 #define SDW_BLOCK_PACKG_PER_PORT BIT(0) 67 #define SDW_BLOCK_PACKG_PER_CH BIT(1) 68 69 /** 70 * enum sdw_slave_status - Slave status 71 * @SDW_SLAVE_UNATTACHED: Slave is not attached with the bus. 72 * @SDW_SLAVE_ATTACHED: Slave is attached with bus. 73 * @SDW_SLAVE_ALERT: Some alert condition on the Slave 74 * @SDW_SLAVE_RESERVED: Reserved for future use 75 */ 76 enum sdw_slave_status { 77 SDW_SLAVE_UNATTACHED = 0, 78 SDW_SLAVE_ATTACHED = 1, 79 SDW_SLAVE_ALERT = 2, 80 SDW_SLAVE_RESERVED = 3, 81 }; 82 83 /** 84 * enum sdw_command_response - Command response as defined by SDW spec 85 * @SDW_CMD_OK: cmd was successful 86 * @SDW_CMD_IGNORED: cmd was ignored 87 * @SDW_CMD_FAIL: cmd was NACKed 88 * @SDW_CMD_TIMEOUT: cmd timedout 89 * @SDW_CMD_FAIL_OTHER: cmd failed due to other reason than above 90 * 91 * NOTE: The enum is different than actual Spec as response in the Spec is 92 * combination of ACK/NAK bits 93 * 94 * SDW_CMD_TIMEOUT/FAIL_OTHER is defined for SW use, not in spec 95 */ 96 enum sdw_command_response { 97 SDW_CMD_OK = 0, 98 SDW_CMD_IGNORED = 1, 99 SDW_CMD_FAIL = 2, 100 SDW_CMD_TIMEOUT = 3, 101 SDW_CMD_FAIL_OTHER = 4, 102 }; 103 104 /* block group count enum */ 105 enum sdw_dpn_grouping { 106 SDW_BLK_GRP_CNT_1 = 0, 107 SDW_BLK_GRP_CNT_2 = 1, 108 SDW_BLK_GRP_CNT_3 = 2, 109 SDW_BLK_GRP_CNT_4 = 3, 110 }; 111 112 /** 113 * enum sdw_stream_type: data stream type 114 * 115 * @SDW_STREAM_PCM: PCM data stream 116 * @SDW_STREAM_PDM: PDM data stream 117 * 118 * spec doesn't define this, but is used in implementation 119 */ 120 enum sdw_stream_type { 121 SDW_STREAM_PCM = 0, 122 SDW_STREAM_PDM = 1, 123 }; 124 125 /** 126 * enum sdw_data_direction: Data direction 127 * 128 * @SDW_DATA_DIR_RX: Data into Port 129 * @SDW_DATA_DIR_TX: Data out of Port 130 */ 131 enum sdw_data_direction { 132 SDW_DATA_DIR_RX = 0, 133 SDW_DATA_DIR_TX = 1, 134 }; 135 136 /** 137 * enum sdw_port_data_mode: Data Port mode 138 * 139 * @SDW_PORT_DATA_MODE_NORMAL: Normal data mode where audio data is received 140 * and transmitted. 141 * @SDW_PORT_DATA_MODE_STATIC_1: Simple test mode which uses static value of 142 * logic 1. The encoding will result in signal transitions at every bitslot 143 * owned by this Port 144 * @SDW_PORT_DATA_MODE_STATIC_0: Simple test mode which uses static value of 145 * logic 0. The encoding will result in no signal transitions 146 * @SDW_PORT_DATA_MODE_PRBS: Test mode which uses a PRBS generator to produce 147 * a pseudo random data pattern that is transferred 148 */ 149 enum sdw_port_data_mode { 150 SDW_PORT_DATA_MODE_NORMAL = 0, 151 SDW_PORT_DATA_MODE_STATIC_1 = 1, 152 SDW_PORT_DATA_MODE_STATIC_0 = 2, 153 SDW_PORT_DATA_MODE_PRBS = 3, 154 }; 155 156 /* 157 * SDW properties, defined in MIPI DisCo spec v1.0 158 */ 159 enum sdw_clk_stop_reset_behave { 160 SDW_CLK_STOP_KEEP_STATUS = 1, 161 }; 162 163 /** 164 * enum sdw_p15_behave - Slave Port 15 behaviour when the Master attempts a 165 * read 166 * @SDW_P15_READ_IGNORED: Read is ignored 167 * @SDW_P15_CMD_OK: Command is ok 168 */ 169 enum sdw_p15_behave { 170 SDW_P15_READ_IGNORED = 0, 171 SDW_P15_CMD_OK = 1, 172 }; 173 174 /** 175 * enum sdw_dpn_type - Data port types 176 * @SDW_DPN_FULL: Full Data Port is supported 177 * @SDW_DPN_SIMPLE: Simplified Data Port as defined in spec. 178 * DPN_SampleCtrl2, DPN_OffsetCtrl2, DPN_HCtrl and DPN_BlockCtrl3 179 * are not implemented. 180 * @SDW_DPN_REDUCED: Reduced Data Port as defined in spec. 181 * DPN_SampleCtrl2, DPN_HCtrl are not implemented. 182 */ 183 enum sdw_dpn_type { 184 SDW_DPN_FULL = 0, 185 SDW_DPN_SIMPLE = 1, 186 SDW_DPN_REDUCED = 2, 187 }; 188 189 /** 190 * enum sdw_clk_stop_mode - Clock Stop modes 191 * @SDW_CLK_STOP_MODE0: Slave can continue operation seamlessly on clock 192 * restart 193 * @SDW_CLK_STOP_MODE1: Slave may have entered a deeper power-saving mode, 194 * not capable of continuing operation seamlessly when the clock restarts 195 */ 196 enum sdw_clk_stop_mode { 197 SDW_CLK_STOP_MODE0 = 0, 198 SDW_CLK_STOP_MODE1 = 1, 199 }; 200 201 /** 202 * struct sdw_dp0_prop - DP0 properties 203 * @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64 204 * (inclusive) 205 * @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64 206 * (inclusive) 207 * @num_words: number of wordlengths supported 208 * @words: wordlengths supported 209 * @BRA_flow_controlled: Slave implementation results in an OK_NotReady 210 * response 211 * @simple_ch_prep_sm: If channel prepare sequence is required 212 * @imp_def_interrupts: If set, each bit corresponds to support for 213 * implementation-defined interrupts 214 * 215 * The wordlengths are specified by Spec as max, min AND number of 216 * discrete values, implementation can define based on the wordlengths they 217 * support 218 */ 219 struct sdw_dp0_prop { 220 u32 max_word; 221 u32 min_word; 222 u32 num_words; 223 u32 *words; 224 bool BRA_flow_controlled; 225 bool simple_ch_prep_sm; 226 bool imp_def_interrupts; 227 }; 228 229 /** 230 * struct sdw_dpn_audio_mode - Audio mode properties for DPn 231 * @bus_min_freq: Minimum bus frequency, in Hz 232 * @bus_max_freq: Maximum bus frequency, in Hz 233 * @bus_num_freq: Number of discrete frequencies supported 234 * @bus_freq: Discrete bus frequencies, in Hz 235 * @min_freq: Minimum sampling frequency, in Hz 236 * @max_freq: Maximum sampling bus frequency, in Hz 237 * @num_freq: Number of discrete sampling frequency supported 238 * @freq: Discrete sampling frequencies, in Hz 239 * @prep_ch_behave: Specifies the dependencies between Channel Prepare 240 * sequence and bus clock configuration 241 * If 0, Channel Prepare can happen at any Bus clock rate 242 * If 1, Channel Prepare sequence shall happen only after Bus clock is 243 * changed to a frequency supported by this mode or compatible modes 244 * described by the next field 245 * @glitchless: Bitmap describing possible glitchless transitions from this 246 * Audio Mode to other Audio Modes 247 */ 248 struct sdw_dpn_audio_mode { 249 u32 bus_min_freq; 250 u32 bus_max_freq; 251 u32 bus_num_freq; 252 u32 *bus_freq; 253 u32 max_freq; 254 u32 min_freq; 255 u32 num_freq; 256 u32 *freq; 257 u32 prep_ch_behave; 258 u32 glitchless; 259 }; 260 261 /** 262 * struct sdw_dpn_prop - Data Port DPn properties 263 * @num: port number 264 * @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64 265 * (inclusive) 266 * @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64 267 * (inclusive) 268 * @num_words: Number of discrete supported wordlengths 269 * @words: Discrete supported wordlength 270 * @type: Data port type. Full, Simplified or Reduced 271 * @max_grouping: Maximum number of samples that can be grouped together for 272 * a full data port 273 * @simple_ch_prep_sm: If the port supports simplified channel prepare state 274 * machine 275 * @ch_prep_timeout: Port-specific timeout value, in milliseconds 276 * @imp_def_interrupts: If set, each bit corresponds to support for 277 * implementation-defined interrupts 278 * @max_ch: Maximum channels supported 279 * @min_ch: Minimum channels supported 280 * @num_ch: Number of discrete channels supported 281 * @ch: Discrete channels supported 282 * @num_ch_combinations: Number of channel combinations supported 283 * @ch_combinations: Channel combinations supported 284 * @modes: SDW mode supported 285 * @max_async_buffer: Number of samples that this port can buffer in 286 * asynchronous modes 287 * @block_pack_mode: Type of block port mode supported 288 * @port_encoding: Payload Channel Sample encoding schemes supported 289 * @audio_modes: Audio modes supported 290 */ 291 struct sdw_dpn_prop { 292 u32 num; 293 u32 max_word; 294 u32 min_word; 295 u32 num_words; 296 u32 *words; 297 enum sdw_dpn_type type; 298 u32 max_grouping; 299 bool simple_ch_prep_sm; 300 u32 ch_prep_timeout; 301 u32 imp_def_interrupts; 302 u32 max_ch; 303 u32 min_ch; 304 u32 num_ch; 305 u32 *ch; 306 u32 num_ch_combinations; 307 u32 *ch_combinations; 308 u32 modes; 309 u32 max_async_buffer; 310 bool block_pack_mode; 311 u32 port_encoding; 312 struct sdw_dpn_audio_mode *audio_modes; 313 }; 314 315 /** 316 * struct sdw_slave_prop - SoundWire Slave properties 317 * @mipi_revision: Spec version of the implementation 318 * @wake_capable: Wake-up events are supported 319 * @test_mode_capable: If test mode is supported 320 * @clk_stop_mode1: Clock-Stop Mode 1 is supported 321 * @simple_clk_stop_capable: Simple clock mode is supported 322 * @clk_stop_timeout: Worst-case latency of the Clock Stop Prepare State 323 * Machine transitions, in milliseconds 324 * @ch_prep_timeout: Worst-case latency of the Channel Prepare State Machine 325 * transitions, in milliseconds 326 * @reset_behave: Slave keeps the status of the SlaveStopClockPrepare 327 * state machine (P=1 SCSP_SM) after exit from clock-stop mode1 328 * @high_PHY_capable: Slave is HighPHY capable 329 * @paging_support: Slave implements paging registers SCP_AddrPage1 and 330 * SCP_AddrPage2 331 * @bank_delay_support: Slave implements bank delay/bridge support registers 332 * SCP_BankDelay and SCP_NextFrame 333 * @p15_behave: Slave behavior when the Master attempts a read to the Port15 334 * alias 335 * @lane_control_support: Slave supports lane control 336 * @master_count: Number of Masters present on this Slave 337 * @source_ports: Bitmap identifying source ports 338 * @sink_ports: Bitmap identifying sink ports 339 * @dp0_prop: Data Port 0 properties 340 * @src_dpn_prop: Source Data Port N properties 341 * @sink_dpn_prop: Sink Data Port N properties 342 */ 343 struct sdw_slave_prop { 344 u32 mipi_revision; 345 bool wake_capable; 346 bool test_mode_capable; 347 bool clk_stop_mode1; 348 bool simple_clk_stop_capable; 349 u32 clk_stop_timeout; 350 u32 ch_prep_timeout; 351 enum sdw_clk_stop_reset_behave reset_behave; 352 bool high_PHY_capable; 353 bool paging_support; 354 bool bank_delay_support; 355 enum sdw_p15_behave p15_behave; 356 bool lane_control_support; 357 u32 master_count; 358 u32 source_ports; 359 u32 sink_ports; 360 struct sdw_dp0_prop *dp0_prop; 361 struct sdw_dpn_prop *src_dpn_prop; 362 struct sdw_dpn_prop *sink_dpn_prop; 363 }; 364 365 /** 366 * struct sdw_master_prop - Master properties 367 * @revision: MIPI spec version of the implementation 368 * @clk_stop_modes: Bitmap, bit N set when clock-stop-modeN supported 369 * @max_clk_freq: Maximum Bus clock frequency, in Hz 370 * @num_clk_gears: Number of clock gears supported 371 * @clk_gears: Clock gears supported 372 * @num_clk_freq: Number of clock frequencies supported, in Hz 373 * @clk_freq: Clock frequencies supported, in Hz 374 * @default_frame_rate: Controller default Frame rate, in Hz 375 * @default_row: Number of rows 376 * @default_col: Number of columns 377 * @dynamic_frame: Dynamic frame shape supported 378 * @err_threshold: Number of times that software may retry sending a single 379 * command 380 */ 381 struct sdw_master_prop { 382 u32 revision; 383 u32 clk_stop_modes; 384 u32 max_clk_freq; 385 u32 num_clk_gears; 386 u32 *clk_gears; 387 u32 num_clk_freq; 388 u32 *clk_freq; 389 u32 default_frame_rate; 390 u32 default_row; 391 u32 default_col; 392 bool dynamic_frame; 393 u32 err_threshold; 394 }; 395 396 int sdw_master_read_prop(struct sdw_bus *bus); 397 int sdw_slave_read_prop(struct sdw_slave *slave); 398 399 /* 400 * SDW Slave Structures and APIs 401 */ 402 403 /** 404 * struct sdw_slave_id - Slave ID 405 * @mfg_id: MIPI Manufacturer ID 406 * @part_id: Device Part ID 407 * @class_id: MIPI Class ID, unused now. 408 * Currently a placeholder in MIPI SoundWire Spec 409 * @unique_id: Device unique ID 410 * @sdw_version: SDW version implemented 411 * 412 * The order of the IDs here does not follow the DisCo spec definitions 413 */ 414 struct sdw_slave_id { 415 __u16 mfg_id; 416 __u16 part_id; 417 __u8 class_id; 418 __u8 unique_id:4; 419 __u8 sdw_version:4; 420 }; 421 422 /** 423 * struct sdw_slave_intr_status - Slave interrupt status 424 * @control_port: control port status 425 * @port: data port status 426 */ 427 struct sdw_slave_intr_status { 428 u8 control_port; 429 u8 port[15]; 430 }; 431 432 /** 433 * sdw_reg_bank - SoundWire register banks 434 * @SDW_BANK0: Soundwire register bank 0 435 * @SDW_BANK1: Soundwire register bank 1 436 */ 437 enum sdw_reg_bank { 438 SDW_BANK0, 439 SDW_BANK1, 440 }; 441 442 /** 443 * struct sdw_bus_conf: Bus configuration 444 * 445 * @clk_freq: Clock frequency, in Hz 446 * @num_rows: Number of rows in frame 447 * @num_cols: Number of columns in frame 448 * @bank: Next register bank 449 */ 450 struct sdw_bus_conf { 451 unsigned int clk_freq; 452 unsigned int num_rows; 453 unsigned int num_cols; 454 unsigned int bank; 455 }; 456 457 /** 458 * struct sdw_prepare_ch: Prepare/De-prepare Data Port channel 459 * 460 * @num: Port number 461 * @ch_mask: Active channel mask 462 * @prepare: Prepare (true) /de-prepare (false) channel 463 * @bank: Register bank, which bank Slave/Master driver should program for 464 * implementation defined registers. This is always updated to next_bank 465 * value read from bus params. 466 * 467 */ 468 struct sdw_prepare_ch { 469 unsigned int num; 470 unsigned int ch_mask; 471 bool prepare; 472 unsigned int bank; 473 }; 474 475 /** 476 * enum sdw_port_prep_ops: Prepare operations for Data Port 477 * 478 * @SDW_OPS_PORT_PRE_PREP: Pre prepare operation for the Port 479 * @SDW_OPS_PORT_PREP: Prepare operation for the Port 480 * @SDW_OPS_PORT_POST_PREP: Post prepare operation for the Port 481 */ 482 enum sdw_port_prep_ops { 483 SDW_OPS_PORT_PRE_PREP = 0, 484 SDW_OPS_PORT_PREP = 1, 485 SDW_OPS_PORT_POST_PREP = 2, 486 }; 487 488 /** 489 * struct sdw_bus_params: Structure holding bus configuration 490 * 491 * @curr_bank: Current bank in use (BANK0/BANK1) 492 * @next_bank: Next bank to use (BANK0/BANK1). next_bank will always be 493 * set to !curr_bank 494 * @max_dr_freq: Maximum double rate clock frequency supported, in Hz 495 * @curr_dr_freq: Current double rate clock frequency, in Hz 496 * @bandwidth: Current bandwidth 497 * @col: Active columns 498 * @row: Active rows 499 */ 500 struct sdw_bus_params { 501 enum sdw_reg_bank curr_bank; 502 enum sdw_reg_bank next_bank; 503 unsigned int max_dr_freq; 504 unsigned int curr_dr_freq; 505 unsigned int bandwidth; 506 unsigned int col; 507 unsigned int row; 508 }; 509 510 /** 511 * struct sdw_slave_ops: Slave driver callback ops 512 * 513 * @read_prop: Read Slave properties 514 * @interrupt_callback: Device interrupt notification (invoked in thread 515 * context) 516 * @update_status: Update Slave status 517 * @bus_config: Update the bus config for Slave 518 * @port_prep: Prepare the port with parameters 519 */ 520 struct sdw_slave_ops { 521 int (*read_prop)(struct sdw_slave *sdw); 522 int (*interrupt_callback)(struct sdw_slave *slave, 523 struct sdw_slave_intr_status *status); 524 int (*update_status)(struct sdw_slave *slave, 525 enum sdw_slave_status status); 526 int (*bus_config)(struct sdw_slave *slave, 527 struct sdw_bus_params *params); 528 int (*port_prep)(struct sdw_slave *slave, 529 struct sdw_prepare_ch *prepare_ch, 530 enum sdw_port_prep_ops pre_ops); 531 }; 532 533 /** 534 * struct sdw_slave - SoundWire Slave 535 * @id: MIPI device ID 536 * @dev: Linux device 537 * @status: Status reported by the Slave 538 * @bus: Bus handle 539 * @ops: Slave callback ops 540 * @prop: Slave properties 541 * @node: node for bus list 542 * @port_ready: Port ready completion flag for each Slave port 543 * @dev_num: Device Number assigned by Bus 544 */ 545 struct sdw_slave { 546 struct sdw_slave_id id; 547 struct device dev; 548 enum sdw_slave_status status; 549 struct sdw_bus *bus; 550 const struct sdw_slave_ops *ops; 551 struct sdw_slave_prop prop; 552 struct list_head node; 553 struct completion *port_ready; 554 u16 dev_num; 555 }; 556 557 #define dev_to_sdw_dev(_dev) container_of(_dev, struct sdw_slave, dev) 558 559 struct sdw_driver { 560 const char *name; 561 562 int (*probe)(struct sdw_slave *sdw, 563 const struct sdw_device_id *id); 564 int (*remove)(struct sdw_slave *sdw); 565 void (*shutdown)(struct sdw_slave *sdw); 566 567 const struct sdw_device_id *id_table; 568 const struct sdw_slave_ops *ops; 569 570 struct device_driver driver; 571 }; 572 573 #define SDW_SLAVE_ENTRY(_mfg_id, _part_id, _drv_data) \ 574 { .mfg_id = (_mfg_id), .part_id = (_part_id), \ 575 .driver_data = (unsigned long)(_drv_data) } 576 577 int sdw_handle_slave_status(struct sdw_bus *bus, 578 enum sdw_slave_status status[]); 579 580 /* 581 * SDW master structures and APIs 582 */ 583 584 /** 585 * struct sdw_port_params: Data Port parameters 586 * 587 * @num: Port number 588 * @bps: Word length of the Port 589 * @flow_mode: Port Data flow mode 590 * @data_mode: Test modes or normal mode 591 * 592 * This is used to program the Data Port based on Data Port stream 593 * parameters. 594 */ 595 struct sdw_port_params { 596 unsigned int num; 597 unsigned int bps; 598 unsigned int flow_mode; 599 unsigned int data_mode; 600 }; 601 602 /** 603 * struct sdw_transport_params: Data Port Transport Parameters 604 * 605 * @blk_grp_ctrl_valid: Port implements block group control 606 * @num: Port number 607 * @blk_grp_ctrl: Block group control value 608 * @sample_interval: Sample interval 609 * @offset1: Blockoffset of the payload data 610 * @offset2: Blockoffset of the payload data 611 * @hstart: Horizontal start of the payload data 612 * @hstop: Horizontal stop of the payload data 613 * @blk_pkg_mode: Block per channel or block per port 614 * @lane_ctrl: Data lane Port uses for Data transfer. Currently only single 615 * data lane is supported in bus 616 * 617 * This is used to program the Data Port based on Data Port transport 618 * parameters. All these parameters are banked and can be modified 619 * during a bank switch without any artifacts in audio stream. 620 */ 621 struct sdw_transport_params { 622 bool blk_grp_ctrl_valid; 623 unsigned int port_num; 624 unsigned int blk_grp_ctrl; 625 unsigned int sample_interval; 626 unsigned int offset1; 627 unsigned int offset2; 628 unsigned int hstart; 629 unsigned int hstop; 630 unsigned int blk_pkg_mode; 631 unsigned int lane_ctrl; 632 }; 633 634 /** 635 * struct sdw_enable_ch: Enable/disable Data Port channel 636 * 637 * @num: Port number 638 * @ch_mask: Active channel mask 639 * @enable: Enable (true) /disable (false) channel 640 */ 641 struct sdw_enable_ch { 642 unsigned int port_num; 643 unsigned int ch_mask; 644 bool enable; 645 }; 646 647 /** 648 * struct sdw_master_port_ops: Callback functions from bus to Master 649 * driver to set Master Data ports. 650 * 651 * @dpn_set_port_params: Set the Port parameters for the Master Port. 652 * Mandatory callback 653 * @dpn_set_port_transport_params: Set transport parameters for the Master 654 * Port. Mandatory callback 655 * @dpn_port_prep: Port prepare operations for the Master Data Port. 656 * @dpn_port_enable_ch: Enable the channels of Master Port. 657 */ 658 struct sdw_master_port_ops { 659 int (*dpn_set_port_params)(struct sdw_bus *bus, 660 struct sdw_port_params *port_params, 661 unsigned int bank); 662 int (*dpn_set_port_transport_params)(struct sdw_bus *bus, 663 struct sdw_transport_params *transport_params, 664 enum sdw_reg_bank bank); 665 int (*dpn_port_prep)(struct sdw_bus *bus, 666 struct sdw_prepare_ch *prepare_ch); 667 int (*dpn_port_enable_ch)(struct sdw_bus *bus, 668 struct sdw_enable_ch *enable_ch, unsigned int bank); 669 }; 670 671 struct sdw_msg; 672 673 /** 674 * struct sdw_defer - SDW deffered message 675 * @length: message length 676 * @complete: message completion 677 * @msg: SDW message 678 */ 679 struct sdw_defer { 680 int length; 681 struct completion complete; 682 struct sdw_msg *msg; 683 }; 684 685 /** 686 * struct sdw_master_ops - Master driver ops 687 * @read_prop: Read Master properties 688 * @xfer_msg: Transfer message callback 689 * @xfer_msg_defer: Defer version of transfer message callback 690 * @reset_page_addr: Reset the SCP page address registers 691 * @set_bus_conf: Set the bus configuration 692 * @pre_bank_switch: Callback for pre bank switch 693 * @post_bank_switch: Callback for post bank switch 694 */ 695 struct sdw_master_ops { 696 int (*read_prop)(struct sdw_bus *bus); 697 698 enum sdw_command_response (*xfer_msg) 699 (struct sdw_bus *bus, struct sdw_msg *msg); 700 enum sdw_command_response (*xfer_msg_defer) 701 (struct sdw_bus *bus, struct sdw_msg *msg, 702 struct sdw_defer *defer); 703 enum sdw_command_response (*reset_page_addr) 704 (struct sdw_bus *bus, unsigned int dev_num); 705 int (*set_bus_conf)(struct sdw_bus *bus, 706 struct sdw_bus_params *params); 707 int (*pre_bank_switch)(struct sdw_bus *bus); 708 int (*post_bank_switch)(struct sdw_bus *bus); 709 710 }; 711 712 /** 713 * struct sdw_bus - SoundWire bus 714 * @dev: Master linux device 715 * @link_id: Link id number, can be 0 to N, unique for each Master 716 * @slaves: list of Slaves on this bus 717 * @assigned: Bitmap for Slave device numbers. 718 * Bit set implies used number, bit clear implies unused number. 719 * @bus_lock: bus lock 720 * @msg_lock: message lock 721 * @ops: Master callback ops 722 * @port_ops: Master port callback ops 723 * @params: Current bus parameters 724 * @prop: Master properties 725 * @m_rt_list: List of Master instance of all stream(s) running on Bus. This 726 * is used to compute and program bus bandwidth, clock, frame shape, 727 * transport and port parameters 728 * @defer_msg: Defer message 729 * @clk_stop_timeout: Clock stop timeout computed 730 * @bank_switch_timeout: Bank switch timeout computed 731 * @multi_link: Store bus property that indicates if multi links 732 * are supported. This flag is populated by drivers after reading 733 * appropriate firmware (ACPI/DT). 734 */ 735 struct sdw_bus { 736 struct device *dev; 737 unsigned int link_id; 738 struct list_head slaves; 739 DECLARE_BITMAP(assigned, SDW_MAX_DEVICES); 740 struct mutex bus_lock; 741 struct mutex msg_lock; 742 const struct sdw_master_ops *ops; 743 const struct sdw_master_port_ops *port_ops; 744 struct sdw_bus_params params; 745 struct sdw_master_prop prop; 746 struct list_head m_rt_list; 747 struct sdw_defer defer_msg; 748 unsigned int clk_stop_timeout; 749 u32 bank_switch_timeout; 750 bool multi_link; 751 }; 752 753 int sdw_add_bus_master(struct sdw_bus *bus); 754 void sdw_delete_bus_master(struct sdw_bus *bus); 755 756 /** 757 * sdw_port_config: Master or Slave Port configuration 758 * 759 * @num: Port number 760 * @ch_mask: channels mask for port 761 */ 762 struct sdw_port_config { 763 unsigned int num; 764 unsigned int ch_mask; 765 }; 766 767 /** 768 * sdw_stream_config: Master or Slave stream configuration 769 * 770 * @frame_rate: Audio frame rate of the stream, in Hz 771 * @ch_count: Channel count of the stream 772 * @bps: Number of bits per audio sample 773 * @direction: Data direction 774 * @type: Stream type PCM or PDM 775 */ 776 struct sdw_stream_config { 777 unsigned int frame_rate; 778 unsigned int ch_count; 779 unsigned int bps; 780 enum sdw_data_direction direction; 781 enum sdw_stream_type type; 782 }; 783 784 /** 785 * sdw_stream_state: Stream states 786 * 787 * @SDW_STREAM_ALLOCATED: New stream allocated. 788 * @SDW_STREAM_CONFIGURED: Stream configured 789 * @SDW_STREAM_PREPARED: Stream prepared 790 * @SDW_STREAM_ENABLED: Stream enabled 791 * @SDW_STREAM_DISABLED: Stream disabled 792 * @SDW_STREAM_DEPREPARED: Stream de-prepared 793 * @SDW_STREAM_RELEASED: Stream released 794 */ 795 enum sdw_stream_state { 796 SDW_STREAM_ALLOCATED = 0, 797 SDW_STREAM_CONFIGURED = 1, 798 SDW_STREAM_PREPARED = 2, 799 SDW_STREAM_ENABLED = 3, 800 SDW_STREAM_DISABLED = 4, 801 SDW_STREAM_DEPREPARED = 5, 802 SDW_STREAM_RELEASED = 6, 803 }; 804 805 /** 806 * sdw_stream_params: Stream parameters 807 * 808 * @rate: Sampling frequency, in Hz 809 * @ch_count: Number of channels 810 * @bps: bits per channel sample 811 */ 812 struct sdw_stream_params { 813 unsigned int rate; 814 unsigned int ch_count; 815 unsigned int bps; 816 }; 817 818 /** 819 * sdw_stream_runtime: Runtime stream parameters 820 * 821 * @name: SoundWire stream name 822 * @params: Stream parameters 823 * @state: Current state of the stream 824 * @type: Stream type PCM or PDM 825 * @master_list: List of Master runtime(s) in this stream. 826 * master_list can contain only one m_rt per Master instance 827 * for a stream 828 * @m_rt_count: Count of Master runtime(s) in this stream 829 */ 830 struct sdw_stream_runtime { 831 char *name; 832 struct sdw_stream_params params; 833 enum sdw_stream_state state; 834 enum sdw_stream_type type; 835 struct list_head master_list; 836 int m_rt_count; 837 }; 838 839 struct sdw_stream_runtime *sdw_alloc_stream(char *stream_name); 840 void sdw_release_stream(struct sdw_stream_runtime *stream); 841 int sdw_stream_add_master(struct sdw_bus *bus, 842 struct sdw_stream_config *stream_config, 843 struct sdw_port_config *port_config, 844 unsigned int num_ports, 845 struct sdw_stream_runtime *stream); 846 int sdw_stream_add_slave(struct sdw_slave *slave, 847 struct sdw_stream_config *stream_config, 848 struct sdw_port_config *port_config, 849 unsigned int num_ports, 850 struct sdw_stream_runtime *stream); 851 int sdw_stream_remove_master(struct sdw_bus *bus, 852 struct sdw_stream_runtime *stream); 853 int sdw_stream_remove_slave(struct sdw_slave *slave, 854 struct sdw_stream_runtime *stream); 855 int sdw_prepare_stream(struct sdw_stream_runtime *stream); 856 int sdw_enable_stream(struct sdw_stream_runtime *stream); 857 int sdw_disable_stream(struct sdw_stream_runtime *stream); 858 int sdw_deprepare_stream(struct sdw_stream_runtime *stream); 859 860 /* messaging and data APIs */ 861 862 int sdw_read(struct sdw_slave *slave, u32 addr); 863 int sdw_write(struct sdw_slave *slave, u32 addr, u8 value); 864 int sdw_nread(struct sdw_slave *slave, u32 addr, size_t count, u8 *val); 865 int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, u8 *val); 866 867 #endif /* __SOUNDWIRE_H */ 868