1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Texas Instruments System Control Interface Protocol 4 * 5 * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ 6 * Nishanth Menon 7 */ 8 9 #ifndef __TISCI_PROTOCOL_H 10 #define __TISCI_PROTOCOL_H 11 12 /** 13 * struct ti_sci_version_info - version information structure 14 * @abi_major: Major ABI version. Change here implies risk of backward 15 * compatibility break. 16 * @abi_minor: Minor ABI version. Change here implies new feature addition, 17 * or compatible change in ABI. 18 * @firmware_revision: Firmware revision (not usually used). 19 * @firmware_description: Firmware description (not usually used). 20 */ 21 struct ti_sci_version_info { 22 u8 abi_major; 23 u8 abi_minor; 24 u16 firmware_revision; 25 char firmware_description[32]; 26 }; 27 28 struct ti_sci_handle; 29 30 /** 31 * struct ti_sci_core_ops - SoC Core Operations 32 * @reboot_device: Reboot the SoC 33 * Returns 0 for successful request(ideally should never return), 34 * else returns corresponding error value. 35 */ 36 struct ti_sci_core_ops { 37 int (*reboot_device)(const struct ti_sci_handle *handle); 38 }; 39 40 /** 41 * struct ti_sci_dev_ops - Device control operations 42 * @get_device: Command to request for device managed by TISCI 43 * Returns 0 for successful exclusive request, else returns 44 * corresponding error message. 45 * @idle_device: Command to idle a device managed by TISCI 46 * Returns 0 for successful exclusive request, else returns 47 * corresponding error message. 48 * @put_device: Command to release a device managed by TISCI 49 * Returns 0 for successful release, else returns corresponding 50 * error message. 51 * @is_valid: Check if the device ID is a valid ID. 52 * Returns 0 if the ID is valid, else returns corresponding error. 53 * @get_context_loss_count: Command to retrieve context loss counter - this 54 * increments every time the device looses context. Overflow 55 * is possible. 56 * - count: pointer to u32 which will retrieve counter 57 * Returns 0 for successful information request and count has 58 * proper data, else returns corresponding error message. 59 * @is_idle: Reports back about device idle state 60 * - req_state: Returns requested idle state 61 * Returns 0 for successful information request and req_state and 62 * current_state has proper data, else returns corresponding error 63 * message. 64 * @is_stop: Reports back about device stop state 65 * - req_state: Returns requested stop state 66 * - current_state: Returns current stop state 67 * Returns 0 for successful information request and req_state and 68 * current_state has proper data, else returns corresponding error 69 * message. 70 * @is_on: Reports back about device ON(or active) state 71 * - req_state: Returns requested ON state 72 * - current_state: Returns current ON state 73 * Returns 0 for successful information request and req_state and 74 * current_state has proper data, else returns corresponding error 75 * message. 76 * @is_transitioning: Reports back if the device is in the middle of transition 77 * of state. 78 * -current_state: Returns 'true' if currently transitioning. 79 * @set_device_resets: Command to configure resets for device managed by TISCI. 80 * -reset_state: Device specific reset bit field 81 * Returns 0 for successful request, else returns 82 * corresponding error message. 83 * @get_device_resets: Command to read state of resets for device managed 84 * by TISCI. 85 * -reset_state: pointer to u32 which will retrieve resets 86 * Returns 0 for successful request, else returns 87 * corresponding error message. 88 * 89 * NOTE: for all these functions, the following parameters are generic in 90 * nature: 91 * -handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle 92 * -id: Device Identifier 93 * 94 * Request for the device - NOTE: the client MUST maintain integrity of 95 * usage count by balancing get_device with put_device. No refcounting is 96 * managed by driver for that purpose. 97 */ 98 struct ti_sci_dev_ops { 99 int (*get_device)(const struct ti_sci_handle *handle, u32 id); 100 int (*idle_device)(const struct ti_sci_handle *handle, u32 id); 101 int (*put_device)(const struct ti_sci_handle *handle, u32 id); 102 int (*is_valid)(const struct ti_sci_handle *handle, u32 id); 103 int (*get_context_loss_count)(const struct ti_sci_handle *handle, 104 u32 id, u32 *count); 105 int (*is_idle)(const struct ti_sci_handle *handle, u32 id, 106 bool *requested_state); 107 int (*is_stop)(const struct ti_sci_handle *handle, u32 id, 108 bool *req_state, bool *current_state); 109 int (*is_on)(const struct ti_sci_handle *handle, u32 id, 110 bool *req_state, bool *current_state); 111 int (*is_transitioning)(const struct ti_sci_handle *handle, u32 id, 112 bool *current_state); 113 int (*set_device_resets)(const struct ti_sci_handle *handle, u32 id, 114 u32 reset_state); 115 int (*get_device_resets)(const struct ti_sci_handle *handle, u32 id, 116 u32 *reset_state); 117 }; 118 119 /** 120 * struct ti_sci_clk_ops - Clock control operations 121 * @get_clock: Request for activation of clock and manage by processor 122 * - needs_ssc: 'true' if Spread Spectrum clock is desired. 123 * - can_change_freq: 'true' if frequency change is desired. 124 * - enable_input_term: 'true' if input termination is desired. 125 * @idle_clock: Request for Idling a clock managed by processor 126 * @put_clock: Release the clock to be auto managed by TISCI 127 * @is_auto: Is the clock being auto managed 128 * - req_state: state indicating if the clock is auto managed 129 * @is_on: Is the clock ON 130 * - req_state: if the clock is requested to be forced ON 131 * - current_state: if the clock is currently ON 132 * @is_off: Is the clock OFF 133 * - req_state: if the clock is requested to be forced OFF 134 * - current_state: if the clock is currently Gated 135 * @set_parent: Set the clock source of a specific device clock 136 * - parent_id: Parent clock identifier to set. 137 * @get_parent: Get the current clock source of a specific device clock 138 * - parent_id: Parent clock identifier which is the parent. 139 * @get_num_parents: Get the number of parents of the current clock source 140 * - num_parents: returns the number of parent clocks. 141 * @get_best_match_freq: Find a best matching frequency for a frequency 142 * range. 143 * - match_freq: Best matching frequency in Hz. 144 * @set_freq: Set the Clock frequency 145 * @get_freq: Get the Clock frequency 146 * - current_freq: Frequency in Hz that the clock is at. 147 * 148 * NOTE: for all these functions, the following parameters are generic in 149 * nature: 150 * -handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle 151 * -did: Device identifier this request is for 152 * -cid: Clock identifier for the device for this request. 153 * Each device has it's own set of clock inputs. This indexes 154 * which clock input to modify. 155 * -min_freq: The minimum allowable frequency in Hz. This is the minimum 156 * allowable programmed frequency and does not account for clock 157 * tolerances and jitter. 158 * -target_freq: The target clock frequency in Hz. A frequency will be 159 * processed as close to this target frequency as possible. 160 * -max_freq: The maximum allowable frequency in Hz. This is the maximum 161 * allowable programmed frequency and does not account for clock 162 * tolerances and jitter. 163 * 164 * Request for the clock - NOTE: the client MUST maintain integrity of 165 * usage count by balancing get_clock with put_clock. No refcounting is 166 * managed by driver for that purpose. 167 */ 168 struct ti_sci_clk_ops { 169 int (*get_clock)(const struct ti_sci_handle *handle, u32 did, u32 cid, 170 bool needs_ssc, bool can_change_freq, 171 bool enable_input_term); 172 int (*idle_clock)(const struct ti_sci_handle *handle, u32 did, u32 cid); 173 int (*put_clock)(const struct ti_sci_handle *handle, u32 did, u32 cid); 174 int (*is_auto)(const struct ti_sci_handle *handle, u32 did, u32 cid, 175 bool *req_state); 176 int (*is_on)(const struct ti_sci_handle *handle, u32 did, u32 cid, 177 bool *req_state, bool *current_state); 178 int (*is_off)(const struct ti_sci_handle *handle, u32 did, u32 cid, 179 bool *req_state, bool *current_state); 180 int (*set_parent)(const struct ti_sci_handle *handle, u32 did, u32 cid, 181 u32 parent_id); 182 int (*get_parent)(const struct ti_sci_handle *handle, u32 did, u32 cid, 183 u32 *parent_id); 184 int (*get_num_parents)(const struct ti_sci_handle *handle, u32 did, 185 u32 cid, u32 *num_parents); 186 int (*get_best_match_freq)(const struct ti_sci_handle *handle, u32 did, 187 u32 cid, u64 min_freq, u64 target_freq, 188 u64 max_freq, u64 *match_freq); 189 int (*set_freq)(const struct ti_sci_handle *handle, u32 did, u32 cid, 190 u64 min_freq, u64 target_freq, u64 max_freq); 191 int (*get_freq)(const struct ti_sci_handle *handle, u32 did, u32 cid, 192 u64 *current_freq); 193 }; 194 195 /** 196 * struct ti_sci_rm_core_ops - Resource management core operations 197 * @get_range: Get a range of resources belonging to ti sci host. 198 * @get_rage_from_shost: Get a range of resources belonging to 199 * specified host id. 200 * - s_host: Host processing entity to which the 201 * resources are allocated 202 * 203 * NOTE: for these functions, all the parameters are consolidated and defined 204 * as below: 205 * - handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle 206 * - dev_id: TISCI device ID. 207 * - subtype: Resource assignment subtype that is being requested 208 * from the given device. 209 * - range_start: Start index of the resource range 210 * - range_end: Number of resources in the range 211 */ 212 struct ti_sci_rm_core_ops { 213 int (*get_range)(const struct ti_sci_handle *handle, u32 dev_id, 214 u8 subtype, u16 *range_start, u16 *range_num); 215 int (*get_range_from_shost)(const struct ti_sci_handle *handle, 216 u32 dev_id, u8 subtype, u8 s_host, 217 u16 *range_start, u16 *range_num); 218 }; 219 220 /** 221 * struct ti_sci_rm_irq_ops: IRQ management operations 222 * @set_irq: Set an IRQ route between the requested source 223 * and destination 224 * @set_event_map: Set an Event based peripheral irq to Interrupt 225 * Aggregator. 226 * @free_irq: Free an an IRQ route between the requested source 227 * destination. 228 * @free_event_map: Free an event based peripheral irq to Interrupt 229 * Aggregator. 230 */ 231 struct ti_sci_rm_irq_ops { 232 int (*set_irq)(const struct ti_sci_handle *handle, u16 src_id, 233 u16 src_index, u16 dst_id, u16 dst_host_irq); 234 int (*set_event_map)(const struct ti_sci_handle *handle, u16 src_id, 235 u16 src_index, u16 ia_id, u16 vint, 236 u16 global_event, u8 vint_status_bit); 237 int (*free_irq)(const struct ti_sci_handle *handle, u16 src_id, 238 u16 src_index, u16 dst_id, u16 dst_host_irq); 239 int (*free_event_map)(const struct ti_sci_handle *handle, u16 src_id, 240 u16 src_index, u16 ia_id, u16 vint, 241 u16 global_event, u8 vint_status_bit); 242 }; 243 244 /* RA config.addr_lo parameter is valid for RM ring configure TI_SCI message */ 245 #define TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID BIT(0) 246 /* RA config.addr_hi parameter is valid for RM ring configure TI_SCI message */ 247 #define TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID BIT(1) 248 /* RA config.count parameter is valid for RM ring configure TI_SCI message */ 249 #define TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID BIT(2) 250 /* RA config.mode parameter is valid for RM ring configure TI_SCI message */ 251 #define TI_SCI_MSG_VALUE_RM_RING_MODE_VALID BIT(3) 252 /* RA config.size parameter is valid for RM ring configure TI_SCI message */ 253 #define TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID BIT(4) 254 /* RA config.order_id parameter is valid for RM ring configure TISCI message */ 255 #define TI_SCI_MSG_VALUE_RM_RING_ORDER_ID_VALID BIT(5) 256 257 #define TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER \ 258 (TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID | \ 259 TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID | \ 260 TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID | \ 261 TI_SCI_MSG_VALUE_RM_RING_MODE_VALID | \ 262 TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID) 263 264 /** 265 * struct ti_sci_rm_ringacc_ops - Ring Accelerator Management operations 266 * @config: configure the SoC Navigator Subsystem Ring Accelerator ring 267 * @get_config: get the SoC Navigator Subsystem Ring Accelerator ring 268 * configuration 269 */ 270 struct ti_sci_rm_ringacc_ops { 271 int (*config)(const struct ti_sci_handle *handle, 272 u32 valid_params, u16 nav_id, u16 index, 273 u32 addr_lo, u32 addr_hi, u32 count, u8 mode, 274 u8 size, u8 order_id 275 ); 276 int (*get_config)(const struct ti_sci_handle *handle, 277 u32 nav_id, u32 index, u8 *mode, 278 u32 *addr_lo, u32 *addr_hi, u32 *count, 279 u8 *size, u8 *order_id); 280 }; 281 282 /** 283 * struct ti_sci_rm_psil_ops - PSI-L thread operations 284 * @pair: pair PSI-L source thread to a destination thread. 285 * If the src_thread is mapped to UDMA tchan, the corresponding channel's 286 * TCHAN_THRD_ID register is updated. 287 * If the dst_thread is mapped to UDMA rchan, the corresponding channel's 288 * RCHAN_THRD_ID register is updated. 289 * @unpair: unpair PSI-L source thread from a destination thread. 290 * If the src_thread is mapped to UDMA tchan, the corresponding channel's 291 * TCHAN_THRD_ID register is cleared. 292 * If the dst_thread is mapped to UDMA rchan, the corresponding channel's 293 * RCHAN_THRD_ID register is cleared. 294 */ 295 struct ti_sci_rm_psil_ops { 296 int (*pair)(const struct ti_sci_handle *handle, u32 nav_id, 297 u32 src_thread, u32 dst_thread); 298 int (*unpair)(const struct ti_sci_handle *handle, u32 nav_id, 299 u32 src_thread, u32 dst_thread); 300 }; 301 302 /* UDMAP channel types */ 303 #define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR 2 304 #define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR_SB 3 /* RX only */ 305 #define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBRR 10 306 #define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBVR 11 307 #define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR 12 308 #define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBVR 13 309 310 #define TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST 0 311 #define TI_SCI_RM_UDMAP_RX_FLOW_DESC_MONO 2 312 313 #define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES 1 314 #define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES 2 315 #define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES 3 316 317 /* UDMAP TX/RX channel valid_params common declarations */ 318 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID BIT(0) 319 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID BIT(1) 320 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID BIT(2) 321 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID BIT(3) 322 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID BIT(4) 323 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_VALID BIT(5) 324 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID BIT(6) 325 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID BIT(7) 326 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID BIT(8) 327 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID BIT(14) 328 329 /** 330 * Configures a Navigator Subsystem UDMAP transmit channel 331 * 332 * Configures a Navigator Subsystem UDMAP transmit channel registers. 333 * See @ti_sci_msg_rm_udmap_tx_ch_cfg_req 334 */ 335 struct ti_sci_msg_rm_udmap_tx_ch_cfg { 336 u32 valid_params; 337 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID BIT(9) 338 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID BIT(10) 339 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID BIT(11) 340 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID BIT(12) 341 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID BIT(13) 342 u16 nav_id; 343 u16 index; 344 u8 tx_pause_on_err; 345 u8 tx_filt_einfo; 346 u8 tx_filt_pswords; 347 u8 tx_atype; 348 u8 tx_chan_type; 349 u8 tx_supr_tdpkt; 350 u16 tx_fetch_size; 351 u8 tx_credit_count; 352 u16 txcq_qnum; 353 u8 tx_priority; 354 u8 tx_qos; 355 u8 tx_orderid; 356 u16 fdepth; 357 u8 tx_sched_priority; 358 u8 tx_burst_size; 359 }; 360 361 /** 362 * Configures a Navigator Subsystem UDMAP receive channel 363 * 364 * Configures a Navigator Subsystem UDMAP receive channel registers. 365 * See @ti_sci_msg_rm_udmap_rx_ch_cfg_req 366 */ 367 struct ti_sci_msg_rm_udmap_rx_ch_cfg { 368 u32 valid_params; 369 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID BIT(9) 370 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID BIT(10) 371 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID BIT(11) 372 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID BIT(12) 373 u16 nav_id; 374 u16 index; 375 u16 rx_fetch_size; 376 u16 rxcq_qnum; 377 u8 rx_priority; 378 u8 rx_qos; 379 u8 rx_orderid; 380 u8 rx_sched_priority; 381 u16 flowid_start; 382 u16 flowid_cnt; 383 u8 rx_pause_on_err; 384 u8 rx_atype; 385 u8 rx_chan_type; 386 u8 rx_ignore_short; 387 u8 rx_ignore_long; 388 u8 rx_burst_size; 389 }; 390 391 /** 392 * Configures a Navigator Subsystem UDMAP receive flow 393 * 394 * Configures a Navigator Subsystem UDMAP receive flow's registers. 395 * See @tis_ci_msg_rm_udmap_flow_cfg_req 396 */ 397 struct ti_sci_msg_rm_udmap_flow_cfg { 398 u32 valid_params; 399 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID BIT(0) 400 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID BIT(1) 401 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID BIT(2) 402 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID BIT(3) 403 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SOP_OFFSET_VALID BIT(4) 404 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID BIT(5) 405 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_VALID BIT(6) 406 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_VALID BIT(7) 407 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_VALID BIT(8) 408 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_VALID BIT(9) 409 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID BIT(10) 410 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID BIT(11) 411 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID BIT(12) 412 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID BIT(13) 413 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID BIT(14) 414 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID BIT(15) 415 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID BIT(16) 416 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID BIT(17) 417 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID BIT(18) 418 u16 nav_id; 419 u16 flow_index; 420 u8 rx_einfo_present; 421 u8 rx_psinfo_present; 422 u8 rx_error_handling; 423 u8 rx_desc_type; 424 u16 rx_sop_offset; 425 u16 rx_dest_qnum; 426 u8 rx_src_tag_hi; 427 u8 rx_src_tag_lo; 428 u8 rx_dest_tag_hi; 429 u8 rx_dest_tag_lo; 430 u8 rx_src_tag_hi_sel; 431 u8 rx_src_tag_lo_sel; 432 u8 rx_dest_tag_hi_sel; 433 u8 rx_dest_tag_lo_sel; 434 u16 rx_fdq0_sz0_qnum; 435 u16 rx_fdq1_qnum; 436 u16 rx_fdq2_qnum; 437 u16 rx_fdq3_qnum; 438 u8 rx_ps_location; 439 }; 440 441 /** 442 * struct ti_sci_rm_udmap_ops - UDMA Management operations 443 * @tx_ch_cfg: configure SoC Navigator Subsystem UDMA transmit channel. 444 * @rx_ch_cfg: configure SoC Navigator Subsystem UDMA receive channel. 445 * @rx_flow_cfg1: configure SoC Navigator Subsystem UDMA receive flow. 446 */ 447 struct ti_sci_rm_udmap_ops { 448 int (*tx_ch_cfg)(const struct ti_sci_handle *handle, 449 const struct ti_sci_msg_rm_udmap_tx_ch_cfg *params); 450 int (*rx_ch_cfg)(const struct ti_sci_handle *handle, 451 const struct ti_sci_msg_rm_udmap_rx_ch_cfg *params); 452 int (*rx_flow_cfg)(const struct ti_sci_handle *handle, 453 const struct ti_sci_msg_rm_udmap_flow_cfg *params); 454 }; 455 456 /** 457 * struct ti_sci_proc_ops - Processor Control operations 458 * @request: Request to control a physical processor. The requesting host 459 * should be in the processor access list 460 * @release: Relinquish a physical processor control 461 * @handover: Handover a physical processor control to another host 462 * in the permitted list 463 * @set_config: Set base configuration of a processor 464 * @set_control: Setup limited control flags in specific cases 465 * @get_status: Get the state of physical processor 466 * 467 * NOTE: The following paramteres are generic in nature for all these ops, 468 * -handle: Pointer to TI SCI handle as retrieved by *ti_sci_get_handle 469 * -pid: Processor ID 470 * -hid: Host ID 471 */ 472 struct ti_sci_proc_ops { 473 int (*request)(const struct ti_sci_handle *handle, u8 pid); 474 int (*release)(const struct ti_sci_handle *handle, u8 pid); 475 int (*handover)(const struct ti_sci_handle *handle, u8 pid, u8 hid); 476 int (*set_config)(const struct ti_sci_handle *handle, u8 pid, 477 u64 boot_vector, u32 cfg_set, u32 cfg_clr); 478 int (*set_control)(const struct ti_sci_handle *handle, u8 pid, 479 u32 ctrl_set, u32 ctrl_clr); 480 int (*get_status)(const struct ti_sci_handle *handle, u8 pid, 481 u64 *boot_vector, u32 *cfg_flags, u32 *ctrl_flags, 482 u32 *status_flags); 483 }; 484 485 /** 486 * struct ti_sci_ops - Function support for TI SCI 487 * @dev_ops: Device specific operations 488 * @clk_ops: Clock specific operations 489 * @rm_core_ops: Resource management core operations. 490 * @rm_irq_ops: IRQ management specific operations 491 * @proc_ops: Processor Control specific operations 492 */ 493 struct ti_sci_ops { 494 struct ti_sci_core_ops core_ops; 495 struct ti_sci_dev_ops dev_ops; 496 struct ti_sci_clk_ops clk_ops; 497 struct ti_sci_rm_core_ops rm_core_ops; 498 struct ti_sci_rm_irq_ops rm_irq_ops; 499 struct ti_sci_rm_ringacc_ops rm_ring_ops; 500 struct ti_sci_rm_psil_ops rm_psil_ops; 501 struct ti_sci_rm_udmap_ops rm_udmap_ops; 502 struct ti_sci_proc_ops proc_ops; 503 }; 504 505 /** 506 * struct ti_sci_handle - Handle returned to TI SCI clients for usage. 507 * @version: structure containing version information 508 * @ops: operations that are made available to TI SCI clients 509 */ 510 struct ti_sci_handle { 511 struct ti_sci_version_info version; 512 struct ti_sci_ops ops; 513 }; 514 515 #define TI_SCI_RESOURCE_NULL 0xffff 516 517 /** 518 * struct ti_sci_resource_desc - Description of TI SCI resource instance range. 519 * @start: Start index of the resource. 520 * @num: Number of resources. 521 * @res_map: Bitmap to manage the allocation of these resources. 522 */ 523 struct ti_sci_resource_desc { 524 u16 start; 525 u16 num; 526 unsigned long *res_map; 527 }; 528 529 /** 530 * struct ti_sci_resource - Structure representing a resource assigned 531 * to a device. 532 * @sets: Number of sets available from this resource type 533 * @lock: Lock to guard the res map in each set. 534 * @desc: Array of resource descriptors. 535 */ 536 struct ti_sci_resource { 537 u16 sets; 538 raw_spinlock_t lock; 539 struct ti_sci_resource_desc *desc; 540 }; 541 542 #if IS_ENABLED(CONFIG_TI_SCI_PROTOCOL) 543 const struct ti_sci_handle *ti_sci_get_handle(struct device *dev); 544 int ti_sci_put_handle(const struct ti_sci_handle *handle); 545 const struct ti_sci_handle *devm_ti_sci_get_handle(struct device *dev); 546 const struct ti_sci_handle *ti_sci_get_by_phandle(struct device_node *np, 547 const char *property); 548 const struct ti_sci_handle *devm_ti_sci_get_by_phandle(struct device *dev, 549 const char *property); 550 u16 ti_sci_get_free_resource(struct ti_sci_resource *res); 551 void ti_sci_release_resource(struct ti_sci_resource *res, u16 id); 552 u32 ti_sci_get_num_resources(struct ti_sci_resource *res); 553 struct ti_sci_resource * 554 devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle, 555 struct device *dev, u32 dev_id, char *of_prop); 556 557 #else /* CONFIG_TI_SCI_PROTOCOL */ 558 559 static inline const struct ti_sci_handle *ti_sci_get_handle(struct device *dev) 560 { 561 return ERR_PTR(-EINVAL); 562 } 563 564 static inline int ti_sci_put_handle(const struct ti_sci_handle *handle) 565 { 566 return -EINVAL; 567 } 568 569 static inline 570 const struct ti_sci_handle *devm_ti_sci_get_handle(struct device *dev) 571 { 572 return ERR_PTR(-EINVAL); 573 } 574 575 static inline 576 const struct ti_sci_handle *ti_sci_get_by_phandle(struct device_node *np, 577 const char *property) 578 { 579 return ERR_PTR(-EINVAL); 580 } 581 582 static inline 583 const struct ti_sci_handle *devm_ti_sci_get_by_phandle(struct device *dev, 584 const char *property) 585 { 586 return ERR_PTR(-EINVAL); 587 } 588 589 static inline u16 ti_sci_get_free_resource(struct ti_sci_resource *res) 590 { 591 return TI_SCI_RESOURCE_NULL; 592 } 593 594 static inline void ti_sci_release_resource(struct ti_sci_resource *res, u16 id) 595 { 596 } 597 598 static inline u32 ti_sci_get_num_resources(struct ti_sci_resource *res) 599 { 600 return 0; 601 } 602 603 static inline struct ti_sci_resource * 604 devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle, 605 struct device *dev, u32 dev_id, char *of_prop) 606 { 607 return ERR_PTR(-EINVAL); 608 } 609 #endif /* CONFIG_TI_SCI_PROTOCOL */ 610 611 #endif /* __TISCI_PROTOCOL_H */ 612