1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. 4 * 5 */ 6 7 #include <linux/platform_device.h> 8 #ifndef __LLCC_QCOM__ 9 #define __LLCC_QCOM__ 10 11 #define LLCC_CPUSS 1 12 #define LLCC_VIDSC0 2 13 #define LLCC_VIDSC1 3 14 #define LLCC_ROTATOR 4 15 #define LLCC_VOICE 5 16 #define LLCC_AUDIO 6 17 #define LLCC_MDMHPGRW 7 18 #define LLCC_MDM 8 19 #define LLCC_MODHW 9 20 #define LLCC_CMPT 10 21 #define LLCC_GPUHTW 11 22 #define LLCC_GPU 12 23 #define LLCC_MMUHWT 13 24 #define LLCC_CMPTDMA 15 25 #define LLCC_DISP 16 26 #define LLCC_VIDFW 17 27 #define LLCC_MDMHPFX 20 28 #define LLCC_MDMPNG 21 29 #define LLCC_AUDHW 22 30 #define LLCC_NPU 23 31 #define LLCC_WLHW 24 32 #define LLCC_PIMEM 25 33 #define LLCC_ECC 26 34 #define LLCC_CVP 28 35 #define LLCC_MODPE 29 36 #define LLCC_APTCM 30 37 #define LLCC_WRCACHE 31 38 #define LLCC_CVPFW 32 39 #define LLCC_CPUSS1 33 40 #define LLCC_CAMEXP0 34 41 #define LLCC_CPUMTE 35 42 #define LLCC_CPUHWT 36 43 #define LLCC_MDMCLAD2 37 44 #define LLCC_CAMEXP1 38 45 #define LLCC_CMPTHCP 39 46 #define LLCC_LCPDARE 40 47 #define LLCC_AENPU 45 48 #define LLCC_ISLAND1 46 49 #define LLCC_ISLAND2 47 50 #define LLCC_ISLAND3 48 51 #define LLCC_ISLAND4 49 52 #define LLCC_CAMEXP2 50 53 #define LLCC_CAMEXP3 51 54 #define LLCC_CAMEXP4 52 55 #define LLCC_DISP_WB 53 56 #define LLCC_DISP_1 54 57 #define LLCC_VIEYE 57 58 #define LLCC_VIDPTH 58 59 #define LLCC_GPUMV 59 60 #define LLCC_EVA_LEFT 60 61 #define LLCC_EVA_RIGHT 61 62 #define LLCC_EVAGAIN 62 63 #define LLCC_VIPTH 63 64 #define LLCC_VIDVSP 64 65 #define LLCC_DISP_LEFT 65 66 #define LLCC_DISP_RIGHT 66 67 #define LLCC_EVCS_LEFT 67 68 #define LLCC_EVCS_RIGHT 68 69 #define LLCC_SPAD 69 70 71 /** 72 * struct llcc_slice_desc - Cache slice descriptor 73 * @slice_id: llcc slice id 74 * @slice_size: Size allocated for the llcc slice 75 */ 76 struct llcc_slice_desc { 77 u32 slice_id; 78 size_t slice_size; 79 }; 80 81 /** 82 * struct llcc_edac_reg_data - llcc edac registers data for each error type 83 * @name: Name of the error 84 * @reg_cnt: Number of registers 85 * @count_mask: Mask value to get the error count 86 * @ways_mask: Mask value to get the error ways 87 * @count_shift: Shift value to get the error count 88 * @ways_shift: Shift value to get the error ways 89 */ 90 struct llcc_edac_reg_data { 91 char *name; 92 u32 reg_cnt; 93 u32 count_mask; 94 u32 ways_mask; 95 u8 count_shift; 96 u8 ways_shift; 97 }; 98 99 struct llcc_edac_reg_offset { 100 /* LLCC TRP registers */ 101 u32 trp_ecc_error_status0; 102 u32 trp_ecc_error_status1; 103 u32 trp_ecc_sb_err_syn0; 104 u32 trp_ecc_db_err_syn0; 105 u32 trp_ecc_error_cntr_clear; 106 u32 trp_interrupt_0_status; 107 u32 trp_interrupt_0_clear; 108 u32 trp_interrupt_0_enable; 109 110 /* LLCC Common registers */ 111 u32 cmn_status0; 112 u32 cmn_interrupt_0_enable; 113 u32 cmn_interrupt_2_enable; 114 115 /* LLCC DRP registers */ 116 u32 drp_ecc_error_cfg; 117 u32 drp_ecc_error_cntr_clear; 118 u32 drp_interrupt_status; 119 u32 drp_interrupt_clear; 120 u32 drp_interrupt_enable; 121 u32 drp_ecc_error_status0; 122 u32 drp_ecc_error_status1; 123 u32 drp_ecc_sb_err_syn0; 124 u32 drp_ecc_db_err_syn0; 125 }; 126 127 /** 128 * struct llcc_drv_data - Data associated with the llcc driver 129 * @regmaps: regmaps associated with the llcc device 130 * @bcast_regmap: regmap associated with llcc broadcast OR offset 131 * @bcast_and_regmap: regmap associated with llcc broadcast AND offset 132 * @cfg: pointer to the data structure for slice configuration 133 * @edac_reg_offset: Offset of the LLCC EDAC registers 134 * @lock: mutex associated with each slice 135 * @cfg_size: size of the config data table 136 * @max_slices: max slices as read from device tree 137 * @num_banks: Number of llcc banks 138 * @bitmap: Bit map to track the active slice ids 139 * @ecc_irq: interrupt for llcc cache error detection and reporting 140 * @version: Indicates the LLCC version 141 */ 142 struct llcc_drv_data { 143 struct regmap **regmaps; 144 struct regmap *bcast_regmap; 145 struct regmap *bcast_and_regmap; 146 const struct llcc_slice_config *cfg; 147 const struct llcc_edac_reg_offset *edac_reg_offset; 148 struct mutex lock; 149 u32 cfg_size; 150 u32 max_slices; 151 u32 num_banks; 152 unsigned long *bitmap; 153 int ecc_irq; 154 u32 version; 155 }; 156 157 #if IS_ENABLED(CONFIG_QCOM_LLCC) 158 /** 159 * llcc_slice_getd - get llcc slice descriptor 160 * @uid: usecase_id of the client 161 */ 162 struct llcc_slice_desc *llcc_slice_getd(u32 uid); 163 164 /** 165 * llcc_slice_putd - llcc slice descritpor 166 * @desc: Pointer to llcc slice descriptor 167 */ 168 void llcc_slice_putd(struct llcc_slice_desc *desc); 169 170 /** 171 * llcc_get_slice_id - get slice id 172 * @desc: Pointer to llcc slice descriptor 173 */ 174 int llcc_get_slice_id(struct llcc_slice_desc *desc); 175 176 /** 177 * llcc_get_slice_size - llcc slice size 178 * @desc: Pointer to llcc slice descriptor 179 */ 180 size_t llcc_get_slice_size(struct llcc_slice_desc *desc); 181 182 /** 183 * llcc_slice_activate - Activate the llcc slice 184 * @desc: Pointer to llcc slice descriptor 185 */ 186 int llcc_slice_activate(struct llcc_slice_desc *desc); 187 188 /** 189 * llcc_slice_deactivate - Deactivate the llcc slice 190 * @desc: Pointer to llcc slice descriptor 191 */ 192 int llcc_slice_deactivate(struct llcc_slice_desc *desc); 193 194 #else 195 static inline struct llcc_slice_desc *llcc_slice_getd(u32 uid) 196 { 197 return NULL; 198 } 199 200 static inline void llcc_slice_putd(struct llcc_slice_desc *desc) 201 { 202 203 }; 204 205 static inline int llcc_get_slice_id(struct llcc_slice_desc *desc) 206 { 207 return -EINVAL; 208 } 209 210 static inline size_t llcc_get_slice_size(struct llcc_slice_desc *desc) 211 { 212 return 0; 213 } 214 static inline int llcc_slice_activate(struct llcc_slice_desc *desc) 215 { 216 return -EINVAL; 217 } 218 219 static inline int llcc_slice_deactivate(struct llcc_slice_desc *desc) 220 { 221 return -EINVAL; 222 } 223 #endif 224 225 #endif 226