1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _LINUX_QCOM_GENI_SE 7 #define _LINUX_QCOM_GENI_SE 8 9 #include <linux/interconnect.h> 10 11 /** 12 * enum geni_se_xfer_mode: Transfer modes supported by Serial Engines 13 * 14 * @GENI_SE_INVALID: Invalid mode 15 * @GENI_SE_FIFO: FIFO mode. Data is transferred with SE FIFO 16 * by programmed IO method 17 * @GENI_SE_DMA: Serial Engine DMA mode. Data is transferred 18 * with SE by DMAengine internal to SE 19 * @GENI_GPI_DMA: GPI DMA mode. Data is transferred using a DMAengine 20 * configured by a firmware residing on a GSI engine. This DMA name is 21 * interchangeably used as GSI or GPI which seem to imply the same DMAengine 22 */ 23 24 enum geni_se_xfer_mode { 25 GENI_SE_INVALID, 26 GENI_SE_FIFO, 27 GENI_SE_DMA, 28 GENI_GPI_DMA, 29 }; 30 31 /* Protocols supported by GENI Serial Engines */ 32 enum geni_se_protocol_type { 33 GENI_SE_NONE, 34 GENI_SE_SPI, 35 GENI_SE_UART, 36 GENI_SE_I2C, 37 GENI_SE_I3C, 38 GENI_SE_SPI_SLAVE, 39 }; 40 41 struct geni_wrapper; 42 struct clk; 43 44 enum geni_icc_path_index { 45 GENI_TO_CORE, 46 CPU_TO_GENI, 47 GENI_TO_DDR 48 }; 49 50 struct geni_icc_path { 51 struct icc_path *path; 52 unsigned int avg_bw; 53 }; 54 55 /** 56 * struct geni_se - GENI Serial Engine 57 * @base: Base Address of the Serial Engine's register block 58 * @dev: Pointer to the Serial Engine device 59 * @wrapper: Pointer to the parent QUP Wrapper core 60 * @clk: Handle to the core serial engine clock 61 * @num_clk_levels: Number of valid clock levels in clk_perf_tbl 62 * @clk_perf_tbl: Table of clock frequency input to serial engine clock 63 * @icc_paths: Array of ICC paths for SE 64 */ 65 struct geni_se { 66 void __iomem *base; 67 struct device *dev; 68 struct geni_wrapper *wrapper; 69 struct clk *clk; 70 unsigned int num_clk_levels; 71 unsigned long *clk_perf_tbl; 72 struct geni_icc_path icc_paths[3]; 73 }; 74 75 /* Common SE registers */ 76 #define GENI_FORCE_DEFAULT_REG 0x20 77 #define GENI_OUTPUT_CTRL 0x24 78 #define SE_GENI_STATUS 0x40 79 #define GENI_SER_M_CLK_CFG 0x48 80 #define GENI_SER_S_CLK_CFG 0x4c 81 #define GENI_IF_DISABLE_RO 0x64 82 #define GENI_FW_REVISION_RO 0x68 83 #define SE_GENI_CLK_SEL 0x7c 84 #define SE_GENI_CFG_SEQ_START 0x84 85 #define SE_GENI_DMA_MODE_EN 0x258 86 #define SE_GENI_M_CMD0 0x600 87 #define SE_GENI_M_CMD_CTRL_REG 0x604 88 #define SE_GENI_M_IRQ_STATUS 0x610 89 #define SE_GENI_M_IRQ_EN 0x614 90 #define SE_GENI_M_IRQ_CLEAR 0x618 91 #define SE_GENI_M_IRQ_EN_SET 0x61c 92 #define SE_GENI_M_IRQ_EN_CLEAR 0x620 93 #define SE_GENI_S_CMD0 0x630 94 #define SE_GENI_S_CMD_CTRL_REG 0x634 95 #define SE_GENI_S_IRQ_STATUS 0x640 96 #define SE_GENI_S_IRQ_EN 0x644 97 #define SE_GENI_S_IRQ_CLEAR 0x648 98 #define SE_GENI_S_IRQ_EN_SET 0x64c 99 #define SE_GENI_S_IRQ_EN_CLEAR 0x650 100 #define SE_GENI_TX_FIFOn 0x700 101 #define SE_GENI_RX_FIFOn 0x780 102 #define SE_GENI_TX_FIFO_STATUS 0x800 103 #define SE_GENI_RX_FIFO_STATUS 0x804 104 #define SE_GENI_TX_WATERMARK_REG 0x80c 105 #define SE_GENI_RX_WATERMARK_REG 0x810 106 #define SE_GENI_RX_RFR_WATERMARK_REG 0x814 107 #define SE_GENI_IOS 0x908 108 #define SE_GENI_M_GP_LENGTH 0x910 109 #define SE_GENI_S_GP_LENGTH 0x914 110 #define SE_DMA_TX_IRQ_STAT 0xc40 111 #define SE_DMA_TX_IRQ_CLR 0xc44 112 #define SE_DMA_TX_FSM_RST 0xc58 113 #define SE_DMA_RX_IRQ_STAT 0xd40 114 #define SE_DMA_RX_IRQ_CLR 0xd44 115 #define SE_DMA_RX_LEN_IN 0xd54 116 #define SE_DMA_RX_FSM_RST 0xd58 117 #define SE_HW_PARAM_0 0xe24 118 #define SE_HW_PARAM_1 0xe28 119 120 /* GENI_FORCE_DEFAULT_REG fields */ 121 #define FORCE_DEFAULT BIT(0) 122 123 /* GENI_OUTPUT_CTRL fields */ 124 #define GENI_IO_MUX_0_EN BIT(0) 125 126 /* GENI_STATUS fields */ 127 #define M_GENI_CMD_ACTIVE BIT(0) 128 #define S_GENI_CMD_ACTIVE BIT(12) 129 130 /* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */ 131 #define SER_CLK_EN BIT(0) 132 #define CLK_DIV_MSK GENMASK(15, 4) 133 #define CLK_DIV_SHFT 4 134 135 /* GENI_IF_DISABLE_RO fields */ 136 #define FIFO_IF_DISABLE (BIT(0)) 137 138 /* GENI_FW_REVISION_RO fields */ 139 #define FW_REV_PROTOCOL_MSK GENMASK(15, 8) 140 #define FW_REV_PROTOCOL_SHFT 8 141 142 /* GENI_CLK_SEL fields */ 143 #define CLK_SEL_MSK GENMASK(2, 0) 144 145 /* SE_GENI_CFG_SEQ_START fields */ 146 #define START_TRIGGER BIT(0) 147 148 /* SE_GENI_DMA_MODE_EN */ 149 #define GENI_DMA_MODE_EN BIT(0) 150 151 /* GENI_M_CMD0 fields */ 152 #define M_OPCODE_MSK GENMASK(31, 27) 153 #define M_OPCODE_SHFT 27 154 #define M_PARAMS_MSK GENMASK(26, 0) 155 156 /* GENI_M_CMD_CTRL_REG */ 157 #define M_GENI_CMD_CANCEL BIT(2) 158 #define M_GENI_CMD_ABORT BIT(1) 159 #define M_GENI_DISABLE BIT(0) 160 161 /* GENI_S_CMD0 fields */ 162 #define S_OPCODE_MSK GENMASK(31, 27) 163 #define S_OPCODE_SHFT 27 164 #define S_PARAMS_MSK GENMASK(26, 0) 165 166 /* GENI_S_CMD_CTRL_REG */ 167 #define S_GENI_CMD_CANCEL BIT(2) 168 #define S_GENI_CMD_ABORT BIT(1) 169 #define S_GENI_DISABLE BIT(0) 170 171 /* GENI_M_IRQ_EN fields */ 172 #define M_CMD_DONE_EN BIT(0) 173 #define M_CMD_OVERRUN_EN BIT(1) 174 #define M_ILLEGAL_CMD_EN BIT(2) 175 #define M_CMD_FAILURE_EN BIT(3) 176 #define M_CMD_CANCEL_EN BIT(4) 177 #define M_CMD_ABORT_EN BIT(5) 178 #define M_TIMESTAMP_EN BIT(6) 179 #define M_RX_IRQ_EN BIT(7) 180 #define M_GP_SYNC_IRQ_0_EN BIT(8) 181 #define M_GP_IRQ_0_EN BIT(9) 182 #define M_GP_IRQ_1_EN BIT(10) 183 #define M_GP_IRQ_2_EN BIT(11) 184 #define M_GP_IRQ_3_EN BIT(12) 185 #define M_GP_IRQ_4_EN BIT(13) 186 #define M_GP_IRQ_5_EN BIT(14) 187 #define M_TX_FIFO_NOT_EMPTY_EN BIT(21) 188 #define M_IO_DATA_DEASSERT_EN BIT(22) 189 #define M_IO_DATA_ASSERT_EN BIT(23) 190 #define M_RX_FIFO_RD_ERR_EN BIT(24) 191 #define M_RX_FIFO_WR_ERR_EN BIT(25) 192 #define M_RX_FIFO_WATERMARK_EN BIT(26) 193 #define M_RX_FIFO_LAST_EN BIT(27) 194 #define M_TX_FIFO_RD_ERR_EN BIT(28) 195 #define M_TX_FIFO_WR_ERR_EN BIT(29) 196 #define M_TX_FIFO_WATERMARK_EN BIT(30) 197 #define M_SEC_IRQ_EN BIT(31) 198 #define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \ 199 M_IO_DATA_DEASSERT_EN | \ 200 M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \ 201 M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \ 202 M_TX_FIFO_WR_ERR_EN) 203 204 /* GENI_S_IRQ_EN fields */ 205 #define S_CMD_DONE_EN BIT(0) 206 #define S_CMD_OVERRUN_EN BIT(1) 207 #define S_ILLEGAL_CMD_EN BIT(2) 208 #define S_CMD_FAILURE_EN BIT(3) 209 #define S_CMD_CANCEL_EN BIT(4) 210 #define S_CMD_ABORT_EN BIT(5) 211 #define S_GP_SYNC_IRQ_0_EN BIT(8) 212 #define S_GP_IRQ_0_EN BIT(9) 213 #define S_GP_IRQ_1_EN BIT(10) 214 #define S_GP_IRQ_2_EN BIT(11) 215 #define S_GP_IRQ_3_EN BIT(12) 216 #define S_GP_IRQ_4_EN BIT(13) 217 #define S_GP_IRQ_5_EN BIT(14) 218 #define S_IO_DATA_DEASSERT_EN BIT(22) 219 #define S_IO_DATA_ASSERT_EN BIT(23) 220 #define S_RX_FIFO_RD_ERR_EN BIT(24) 221 #define S_RX_FIFO_WR_ERR_EN BIT(25) 222 #define S_RX_FIFO_WATERMARK_EN BIT(26) 223 #define S_RX_FIFO_LAST_EN BIT(27) 224 #define S_COMMON_GENI_S_IRQ_EN (GENMASK(5, 1) | GENMASK(13, 9) | \ 225 S_RX_FIFO_RD_ERR_EN | S_RX_FIFO_WR_ERR_EN) 226 227 /* GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */ 228 #define WATERMARK_MSK GENMASK(5, 0) 229 230 /* GENI_TX_FIFO_STATUS fields */ 231 #define TX_FIFO_WC GENMASK(27, 0) 232 233 /* GENI_RX_FIFO_STATUS fields */ 234 #define RX_LAST BIT(31) 235 #define RX_LAST_BYTE_VALID_MSK GENMASK(30, 28) 236 #define RX_LAST_BYTE_VALID_SHFT 28 237 #define RX_FIFO_WC_MSK GENMASK(24, 0) 238 239 /* SE_GENI_IOS fields */ 240 #define IO2_DATA_IN BIT(1) 241 #define RX_DATA_IN BIT(0) 242 243 /* SE_GENI_M_GP_LENGTH and SE_GENI_S_GP_LENGTH fields */ 244 #define GP_LENGTH GENMASK(31, 0) 245 246 /* SE_DMA_TX_IRQ_STAT Register fields */ 247 #define TX_DMA_DONE BIT(0) 248 #define TX_EOT BIT(1) 249 #define TX_SBE BIT(2) 250 #define TX_RESET_DONE BIT(3) 251 252 /* SE_DMA_RX_IRQ_STAT Register fields */ 253 #define RX_DMA_DONE BIT(0) 254 #define RX_EOT BIT(1) 255 #define RX_SBE BIT(2) 256 #define RX_RESET_DONE BIT(3) 257 #define RX_FLUSH_DONE BIT(4) 258 #define RX_DMA_PARITY_ERR BIT(5) 259 #define RX_DMA_BREAK GENMASK(8, 7) 260 #define RX_GENI_GP_IRQ GENMASK(10, 5) 261 #define RX_GENI_GP_IRQ_EXT GENMASK(13, 12) 262 #define RX_GENI_CANCEL_IRQ BIT(14) 263 264 /* SE_HW_PARAM_0 fields */ 265 #define TX_FIFO_WIDTH_MSK GENMASK(29, 24) 266 #define TX_FIFO_WIDTH_SHFT 24 267 /* 268 * For QUP HW Version >= 3.10 Tx fifo depth support is increased 269 * to 256bytes and corresponding bits are 16 to 23 270 */ 271 #define TX_FIFO_DEPTH_MSK_256_BYTES GENMASK(23, 16) 272 #define TX_FIFO_DEPTH_MSK GENMASK(21, 16) 273 #define TX_FIFO_DEPTH_SHFT 16 274 275 /* SE_HW_PARAM_1 fields */ 276 #define RX_FIFO_WIDTH_MSK GENMASK(29, 24) 277 #define RX_FIFO_WIDTH_SHFT 24 278 /* 279 * For QUP HW Version >= 3.10 Rx fifo depth support is increased 280 * to 256bytes and corresponding bits are 16 to 23 281 */ 282 #define RX_FIFO_DEPTH_MSK_256_BYTES GENMASK(23, 16) 283 #define RX_FIFO_DEPTH_MSK GENMASK(21, 16) 284 #define RX_FIFO_DEPTH_SHFT 16 285 286 #define HW_VER_MAJOR_MASK GENMASK(31, 28) 287 #define HW_VER_MAJOR_SHFT 28 288 #define HW_VER_MINOR_MASK GENMASK(27, 16) 289 #define HW_VER_MINOR_SHFT 16 290 #define HW_VER_STEP_MASK GENMASK(15, 0) 291 292 #define GENI_SE_VERSION_MAJOR(ver) ((ver & HW_VER_MAJOR_MASK) >> HW_VER_MAJOR_SHFT) 293 #define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT) 294 #define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK) 295 296 /* QUP SE VERSION value for major number 2 and minor number 5 */ 297 #define QUP_SE_VERSION_2_5 0x20050000 298 299 /* 300 * Define bandwidth thresholds that cause the underlying Core 2X interconnect 301 * clock to run at the named frequency. These baseline values are recommended 302 * by the hardware team, and are not dynamically scaled with GENI bandwidth 303 * beyond basic on/off. 304 */ 305 #define CORE_2X_19_2_MHZ 960 306 #define CORE_2X_50_MHZ 2500 307 #define CORE_2X_100_MHZ 5000 308 #define CORE_2X_150_MHZ 7500 309 #define CORE_2X_200_MHZ 10000 310 #define CORE_2X_236_MHZ 16383 311 312 #define GENI_DEFAULT_BW Bps_to_icc(1000) 313 314 #if IS_ENABLED(CONFIG_QCOM_GENI_SE) 315 316 u32 geni_se_get_qup_hw_version(struct geni_se *se); 317 318 /** 319 * geni_se_read_proto() - Read the protocol configured for a serial engine 320 * @se: Pointer to the concerned serial engine. 321 * 322 * Return: Protocol value as configured in the serial engine. 323 */ 324 static inline u32 geni_se_read_proto(struct geni_se *se) 325 { 326 u32 val; 327 328 val = readl_relaxed(se->base + GENI_FW_REVISION_RO); 329 330 return (val & FW_REV_PROTOCOL_MSK) >> FW_REV_PROTOCOL_SHFT; 331 } 332 333 /** 334 * geni_se_setup_m_cmd() - Setup the primary sequencer 335 * @se: Pointer to the concerned serial engine. 336 * @cmd: Command/Operation to setup in the primary sequencer. 337 * @params: Parameter for the sequencer command. 338 * 339 * This function is used to configure the primary sequencer with the 340 * command and its associated parameters. 341 */ 342 static inline void geni_se_setup_m_cmd(struct geni_se *se, u32 cmd, u32 params) 343 { 344 u32 m_cmd; 345 346 m_cmd = (cmd << M_OPCODE_SHFT) | (params & M_PARAMS_MSK); 347 writel(m_cmd, se->base + SE_GENI_M_CMD0); 348 } 349 350 /** 351 * geni_se_setup_s_cmd() - Setup the secondary sequencer 352 * @se: Pointer to the concerned serial engine. 353 * @cmd: Command/Operation to setup in the secondary sequencer. 354 * @params: Parameter for the sequencer command. 355 * 356 * This function is used to configure the secondary sequencer with the 357 * command and its associated parameters. 358 */ 359 static inline void geni_se_setup_s_cmd(struct geni_se *se, u32 cmd, u32 params) 360 { 361 u32 s_cmd; 362 363 s_cmd = readl_relaxed(se->base + SE_GENI_S_CMD0); 364 s_cmd &= ~(S_OPCODE_MSK | S_PARAMS_MSK); 365 s_cmd |= (cmd << S_OPCODE_SHFT); 366 s_cmd |= (params & S_PARAMS_MSK); 367 writel(s_cmd, se->base + SE_GENI_S_CMD0); 368 } 369 370 /** 371 * geni_se_cancel_m_cmd() - Cancel the command configured in the primary 372 * sequencer 373 * @se: Pointer to the concerned serial engine. 374 * 375 * This function is used to cancel the currently configured command in the 376 * primary sequencer. 377 */ 378 static inline void geni_se_cancel_m_cmd(struct geni_se *se) 379 { 380 writel_relaxed(M_GENI_CMD_CANCEL, se->base + SE_GENI_M_CMD_CTRL_REG); 381 } 382 383 /** 384 * geni_se_cancel_s_cmd() - Cancel the command configured in the secondary 385 * sequencer 386 * @se: Pointer to the concerned serial engine. 387 * 388 * This function is used to cancel the currently configured command in the 389 * secondary sequencer. 390 */ 391 static inline void geni_se_cancel_s_cmd(struct geni_se *se) 392 { 393 writel_relaxed(S_GENI_CMD_CANCEL, se->base + SE_GENI_S_CMD_CTRL_REG); 394 } 395 396 /** 397 * geni_se_abort_m_cmd() - Abort the command configured in the primary sequencer 398 * @se: Pointer to the concerned serial engine. 399 * 400 * This function is used to force abort the currently configured command in the 401 * primary sequencer. 402 */ 403 static inline void geni_se_abort_m_cmd(struct geni_se *se) 404 { 405 writel_relaxed(M_GENI_CMD_ABORT, se->base + SE_GENI_M_CMD_CTRL_REG); 406 } 407 408 /** 409 * geni_se_abort_s_cmd() - Abort the command configured in the secondary 410 * sequencer 411 * @se: Pointer to the concerned serial engine. 412 * 413 * This function is used to force abort the currently configured command in the 414 * secondary sequencer. 415 */ 416 static inline void geni_se_abort_s_cmd(struct geni_se *se) 417 { 418 writel_relaxed(S_GENI_CMD_ABORT, se->base + SE_GENI_S_CMD_CTRL_REG); 419 } 420 421 /** 422 * geni_se_get_tx_fifo_depth() - Get the TX fifo depth of the serial engine 423 * based on QUP HW version 424 * @se: Pointer to the concerned serial engine. 425 * 426 * This function is used to get the depth i.e. number of elements in the 427 * TX fifo of the serial engine. 428 * 429 * Return: TX fifo depth in units of FIFO words. 430 */ 431 static inline u32 geni_se_get_tx_fifo_depth(struct geni_se *se) 432 { 433 u32 val, hw_version, hw_major, hw_minor, tx_fifo_depth_mask; 434 435 hw_version = geni_se_get_qup_hw_version(se); 436 hw_major = GENI_SE_VERSION_MAJOR(hw_version); 437 hw_minor = GENI_SE_VERSION_MINOR(hw_version); 438 439 if ((hw_major == 3 && hw_minor >= 10) || hw_major > 3) 440 tx_fifo_depth_mask = TX_FIFO_DEPTH_MSK_256_BYTES; 441 else 442 tx_fifo_depth_mask = TX_FIFO_DEPTH_MSK; 443 444 val = readl_relaxed(se->base + SE_HW_PARAM_0); 445 446 return (val & tx_fifo_depth_mask) >> TX_FIFO_DEPTH_SHFT; 447 } 448 449 /** 450 * geni_se_get_tx_fifo_width() - Get the TX fifo width of the serial engine 451 * @se: Pointer to the concerned serial engine. 452 * 453 * This function is used to get the width i.e. word size per element in the 454 * TX fifo of the serial engine. 455 * 456 * Return: TX fifo width in bits 457 */ 458 static inline u32 geni_se_get_tx_fifo_width(struct geni_se *se) 459 { 460 u32 val; 461 462 val = readl_relaxed(se->base + SE_HW_PARAM_0); 463 464 return (val & TX_FIFO_WIDTH_MSK) >> TX_FIFO_WIDTH_SHFT; 465 } 466 467 /** 468 * geni_se_get_rx_fifo_depth() - Get the RX fifo depth of the serial engine 469 * based on QUP HW version 470 * @se: Pointer to the concerned serial engine. 471 * 472 * This function is used to get the depth i.e. number of elements in the 473 * RX fifo of the serial engine. 474 * 475 * Return: RX fifo depth in units of FIFO words 476 */ 477 static inline u32 geni_se_get_rx_fifo_depth(struct geni_se *se) 478 { 479 u32 val, hw_version, hw_major, hw_minor, rx_fifo_depth_mask; 480 481 hw_version = geni_se_get_qup_hw_version(se); 482 hw_major = GENI_SE_VERSION_MAJOR(hw_version); 483 hw_minor = GENI_SE_VERSION_MINOR(hw_version); 484 485 if ((hw_major == 3 && hw_minor >= 10) || hw_major > 3) 486 rx_fifo_depth_mask = RX_FIFO_DEPTH_MSK_256_BYTES; 487 else 488 rx_fifo_depth_mask = RX_FIFO_DEPTH_MSK; 489 490 val = readl_relaxed(se->base + SE_HW_PARAM_1); 491 492 return (val & rx_fifo_depth_mask) >> RX_FIFO_DEPTH_SHFT; 493 } 494 495 void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr); 496 497 void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode); 498 499 void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words, 500 bool msb_to_lsb, bool tx_cfg, bool rx_cfg); 501 502 int geni_se_resources_off(struct geni_se *se); 503 504 int geni_se_resources_on(struct geni_se *se); 505 506 int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl); 507 508 int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq, 509 unsigned int *index, unsigned long *res_freq, 510 bool exact); 511 512 void geni_se_tx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len); 513 514 int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len, 515 dma_addr_t *iova); 516 517 void geni_se_rx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len); 518 519 int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len, 520 dma_addr_t *iova); 521 522 void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len); 523 524 void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len); 525 526 int geni_icc_get(struct geni_se *se, const char *icc_ddr); 527 528 int geni_icc_set_bw(struct geni_se *se); 529 void geni_icc_set_tag(struct geni_se *se, u32 tag); 530 531 int geni_icc_enable(struct geni_se *se); 532 533 int geni_icc_disable(struct geni_se *se); 534 #endif 535 #endif 536