1 #ifndef __SH_CLOCK_H 2 #define __SH_CLOCK_H 3 4 #include <linux/list.h> 5 #include <linux/seq_file.h> 6 #include <linux/cpufreq.h> 7 #include <linux/types.h> 8 #include <linux/kref.h> 9 #include <linux/clk.h> 10 #include <linux/err.h> 11 12 struct clk; 13 14 struct clk_mapping { 15 phys_addr_t phys; 16 void __iomem *base; 17 unsigned long len; 18 struct kref ref; 19 }; 20 21 struct clk_ops { 22 #ifdef CONFIG_SH_CLK_CPG_LEGACY 23 void (*init)(struct clk *clk); 24 #endif 25 int (*enable)(struct clk *clk); 26 void (*disable)(struct clk *clk); 27 unsigned long (*recalc)(struct clk *clk); 28 int (*set_rate)(struct clk *clk, unsigned long rate); 29 int (*set_parent)(struct clk *clk, struct clk *parent); 30 long (*round_rate)(struct clk *clk, unsigned long rate); 31 }; 32 33 struct clk { 34 struct list_head node; 35 struct clk *parent; 36 struct clk **parent_table; /* list of parents to */ 37 unsigned short parent_num; /* choose between */ 38 unsigned char src_shift; /* source clock field in the */ 39 unsigned char src_width; /* configuration register */ 40 struct clk_ops *ops; 41 42 struct list_head children; 43 struct list_head sibling; /* node for children */ 44 45 int usecount; 46 47 unsigned long rate; 48 unsigned long flags; 49 50 void __iomem *enable_reg; 51 unsigned int enable_bit; 52 53 unsigned long arch_flags; 54 void *priv; 55 struct clk_mapping *mapping; 56 struct cpufreq_frequency_table *freq_table; 57 unsigned int nr_freqs; 58 }; 59 60 #define CLK_ENABLE_ON_INIT (1 << 0) 61 62 /* drivers/sh/clk.c */ 63 unsigned long followparent_recalc(struct clk *); 64 void recalculate_root_clocks(void); 65 void propagate_rate(struct clk *); 66 int clk_reparent(struct clk *child, struct clk *parent); 67 int clk_register(struct clk *); 68 void clk_unregister(struct clk *); 69 void clk_enable_init_clocks(void); 70 71 struct clk_div_mult_table { 72 unsigned int *divisors; 73 unsigned int nr_divisors; 74 unsigned int *multipliers; 75 unsigned int nr_multipliers; 76 }; 77 78 struct cpufreq_frequency_table; 79 void clk_rate_table_build(struct clk *clk, 80 struct cpufreq_frequency_table *freq_table, 81 int nr_freqs, 82 struct clk_div_mult_table *src_table, 83 unsigned long *bitmap); 84 85 long clk_rate_table_round(struct clk *clk, 86 struct cpufreq_frequency_table *freq_table, 87 unsigned long rate); 88 89 int clk_rate_table_find(struct clk *clk, 90 struct cpufreq_frequency_table *freq_table, 91 unsigned long rate); 92 93 long clk_rate_div_range_round(struct clk *clk, unsigned int div_min, 94 unsigned int div_max, unsigned long rate); 95 96 long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min, 97 unsigned int mult_max, unsigned long rate); 98 99 long clk_round_parent(struct clk *clk, unsigned long target, 100 unsigned long *best_freq, unsigned long *parent_freq, 101 unsigned int div_min, unsigned int div_max); 102 103 #define SH_CLK_MSTP32(_parent, _enable_reg, _enable_bit, _flags) \ 104 { \ 105 .parent = _parent, \ 106 .enable_reg = (void __iomem *)_enable_reg, \ 107 .enable_bit = _enable_bit, \ 108 .flags = _flags, \ 109 } 110 111 int sh_clk_mstp32_register(struct clk *clks, int nr); 112 113 #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \ 114 { \ 115 .parent = _parent, \ 116 .enable_reg = (void __iomem *)_reg, \ 117 .enable_bit = _shift, \ 118 .arch_flags = _div_bitmap, \ 119 .flags = _flags, \ 120 } 121 122 struct clk_div4_table { 123 struct clk_div_mult_table *div_mult_table; 124 void (*kick)(struct clk *clk); 125 }; 126 127 int sh_clk_div4_register(struct clk *clks, int nr, 128 struct clk_div4_table *table); 129 int sh_clk_div4_enable_register(struct clk *clks, int nr, 130 struct clk_div4_table *table); 131 int sh_clk_div4_reparent_register(struct clk *clks, int nr, 132 struct clk_div4_table *table); 133 134 #define SH_CLK_DIV6_EXT(_parent, _reg, _flags, _parents, \ 135 _num_parents, _src_shift, _src_width) \ 136 { \ 137 .parent = _parent, \ 138 .enable_reg = (void __iomem *)_reg, \ 139 .flags = _flags, \ 140 .parent_table = _parents, \ 141 .parent_num = _num_parents, \ 142 .src_shift = _src_shift, \ 143 .src_width = _src_width, \ 144 } 145 146 #define SH_CLK_DIV6(_parent, _reg, _flags) \ 147 SH_CLK_DIV6_EXT(_parent, _reg, _flags, NULL, 0, 0, 0) 148 149 int sh_clk_div6_register(struct clk *clks, int nr); 150 int sh_clk_div6_reparent_register(struct clk *clks, int nr); 151 152 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } 153 #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk } 154 #define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk } 155 156 #endif /* __SH_CLOCK_H */ 157