1 #ifndef __SH_CLOCK_H 2 #define __SH_CLOCK_H 3 4 #include <linux/list.h> 5 #include <linux/seq_file.h> 6 #include <linux/cpufreq.h> 7 #include <linux/types.h> 8 #include <linux/kref.h> 9 #include <linux/clk.h> 10 #include <linux/err.h> 11 12 struct clk; 13 14 struct clk_mapping { 15 phys_addr_t phys; 16 void __iomem *base; 17 unsigned long len; 18 struct kref ref; 19 }; 20 21 #define sh_clk_ops clk_ops 22 23 struct clk_ops { 24 #ifdef CONFIG_SH_CLK_CPG_LEGACY 25 void (*init)(struct clk *clk); 26 #endif 27 int (*enable)(struct clk *clk); 28 void (*disable)(struct clk *clk); 29 unsigned long (*recalc)(struct clk *clk); 30 int (*set_rate)(struct clk *clk, unsigned long rate); 31 int (*set_parent)(struct clk *clk, struct clk *parent); 32 long (*round_rate)(struct clk *clk, unsigned long rate); 33 }; 34 35 struct clk { 36 struct list_head node; 37 struct clk *parent; 38 struct clk **parent_table; /* list of parents to */ 39 unsigned short parent_num; /* choose between */ 40 unsigned char src_shift; /* source clock field in the */ 41 unsigned char src_width; /* configuration register */ 42 struct clk_ops *ops; 43 44 struct list_head children; 45 struct list_head sibling; /* node for children */ 46 47 int usecount; 48 49 unsigned long rate; 50 unsigned long flags; 51 52 void __iomem *enable_reg; 53 unsigned int enable_bit; 54 void __iomem *mapped_reg; 55 56 unsigned long arch_flags; 57 void *priv; 58 struct clk_mapping *mapping; 59 struct cpufreq_frequency_table *freq_table; 60 unsigned int nr_freqs; 61 }; 62 63 #define CLK_ENABLE_ON_INIT (1 << 0) 64 65 /* drivers/sh/clk.c */ 66 unsigned long followparent_recalc(struct clk *); 67 void recalculate_root_clocks(void); 68 void propagate_rate(struct clk *); 69 int clk_reparent(struct clk *child, struct clk *parent); 70 int clk_register(struct clk *); 71 void clk_unregister(struct clk *); 72 void clk_enable_init_clocks(void); 73 74 struct clk_div_mult_table { 75 unsigned int *divisors; 76 unsigned int nr_divisors; 77 unsigned int *multipliers; 78 unsigned int nr_multipliers; 79 }; 80 81 struct cpufreq_frequency_table; 82 void clk_rate_table_build(struct clk *clk, 83 struct cpufreq_frequency_table *freq_table, 84 int nr_freqs, 85 struct clk_div_mult_table *src_table, 86 unsigned long *bitmap); 87 88 long clk_rate_table_round(struct clk *clk, 89 struct cpufreq_frequency_table *freq_table, 90 unsigned long rate); 91 92 int clk_rate_table_find(struct clk *clk, 93 struct cpufreq_frequency_table *freq_table, 94 unsigned long rate); 95 96 long clk_rate_div_range_round(struct clk *clk, unsigned int div_min, 97 unsigned int div_max, unsigned long rate); 98 99 long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min, 100 unsigned int mult_max, unsigned long rate); 101 102 long clk_round_parent(struct clk *clk, unsigned long target, 103 unsigned long *best_freq, unsigned long *parent_freq, 104 unsigned int div_min, unsigned int div_max); 105 106 #define SH_CLK_MSTP32(_parent, _enable_reg, _enable_bit, _flags) \ 107 { \ 108 .parent = _parent, \ 109 .enable_reg = (void __iomem *)_enable_reg, \ 110 .enable_bit = _enable_bit, \ 111 .flags = _flags, \ 112 } 113 114 int sh_clk_mstp32_register(struct clk *clks, int nr); 115 116 #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \ 117 { \ 118 .parent = _parent, \ 119 .enable_reg = (void __iomem *)_reg, \ 120 .enable_bit = _shift, \ 121 .arch_flags = _div_bitmap, \ 122 .flags = _flags, \ 123 } 124 125 struct clk_div4_table { 126 struct clk_div_mult_table *div_mult_table; 127 void (*kick)(struct clk *clk); 128 }; 129 130 int sh_clk_div4_register(struct clk *clks, int nr, 131 struct clk_div4_table *table); 132 int sh_clk_div4_enable_register(struct clk *clks, int nr, 133 struct clk_div4_table *table); 134 int sh_clk_div4_reparent_register(struct clk *clks, int nr, 135 struct clk_div4_table *table); 136 137 #define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \ 138 _num_parents, _src_shift, _src_width) \ 139 { \ 140 .enable_reg = (void __iomem *)_reg, \ 141 .flags = _flags, \ 142 .parent_table = _parents, \ 143 .parent_num = _num_parents, \ 144 .src_shift = _src_shift, \ 145 .src_width = _src_width, \ 146 } 147 148 #define SH_CLK_DIV6(_parent, _reg, _flags) \ 149 { \ 150 .parent = _parent, \ 151 .enable_reg = (void __iomem *)_reg, \ 152 .flags = _flags, \ 153 } 154 155 int sh_clk_div6_register(struct clk *clks, int nr); 156 int sh_clk_div6_reparent_register(struct clk *clks, int nr); 157 158 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } 159 #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk } 160 #define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk } 161 162 #endif /* __SH_CLOCK_H */ 163