1 #ifndef __SH_CLOCK_H 2 #define __SH_CLOCK_H 3 4 #include <linux/list.h> 5 #include <linux/seq_file.h> 6 #include <linux/cpufreq.h> 7 #include <linux/types.h> 8 #include <linux/kref.h> 9 #include <linux/clk.h> 10 #include <linux/err.h> 11 12 struct clk; 13 14 struct clk_mapping { 15 phys_addr_t phys; 16 void __iomem *base; 17 unsigned long len; 18 struct kref ref; 19 }; 20 21 22 struct sh_clk_ops { 23 #ifdef CONFIG_SH_CLK_CPG_LEGACY 24 void (*init)(struct clk *clk); 25 #endif 26 int (*enable)(struct clk *clk); 27 void (*disable)(struct clk *clk); 28 unsigned long (*recalc)(struct clk *clk); 29 int (*set_rate)(struct clk *clk, unsigned long rate); 30 int (*set_parent)(struct clk *clk, struct clk *parent); 31 long (*round_rate)(struct clk *clk, unsigned long rate); 32 }; 33 34 struct clk { 35 struct list_head node; 36 struct clk *parent; 37 struct clk **parent_table; /* list of parents to */ 38 unsigned short parent_num; /* choose between */ 39 unsigned char src_shift; /* source clock field in the */ 40 unsigned char src_width; /* configuration register */ 41 struct sh_clk_ops *ops; 42 43 struct list_head children; 44 struct list_head sibling; /* node for children */ 45 46 int usecount; 47 48 unsigned long rate; 49 unsigned long flags; 50 51 void __iomem *enable_reg; 52 unsigned int enable_bit; 53 void __iomem *mapped_reg; 54 55 unsigned long arch_flags; 56 void *priv; 57 struct clk_mapping *mapping; 58 struct cpufreq_frequency_table *freq_table; 59 unsigned int nr_freqs; 60 }; 61 62 #define CLK_ENABLE_ON_INIT BIT(0) 63 64 #define CLK_ENABLE_REG_32BIT BIT(1) /* default access size */ 65 #define CLK_ENABLE_REG_16BIT BIT(2) 66 #define CLK_ENABLE_REG_8BIT BIT(3) 67 68 #define CLK_ENABLE_REG_MASK (CLK_ENABLE_REG_32BIT | \ 69 CLK_ENABLE_REG_16BIT | \ 70 CLK_ENABLE_REG_8BIT) 71 72 /* drivers/sh/clk.c */ 73 unsigned long followparent_recalc(struct clk *); 74 void recalculate_root_clocks(void); 75 void propagate_rate(struct clk *); 76 int clk_reparent(struct clk *child, struct clk *parent); 77 int clk_register(struct clk *); 78 void clk_unregister(struct clk *); 79 void clk_enable_init_clocks(void); 80 81 struct clk_div_mult_table { 82 unsigned int *divisors; 83 unsigned int nr_divisors; 84 unsigned int *multipliers; 85 unsigned int nr_multipliers; 86 }; 87 88 struct cpufreq_frequency_table; 89 void clk_rate_table_build(struct clk *clk, 90 struct cpufreq_frequency_table *freq_table, 91 int nr_freqs, 92 struct clk_div_mult_table *src_table, 93 unsigned long *bitmap); 94 95 long clk_rate_table_round(struct clk *clk, 96 struct cpufreq_frequency_table *freq_table, 97 unsigned long rate); 98 99 int clk_rate_table_find(struct clk *clk, 100 struct cpufreq_frequency_table *freq_table, 101 unsigned long rate); 102 103 long clk_rate_div_range_round(struct clk *clk, unsigned int div_min, 104 unsigned int div_max, unsigned long rate); 105 106 long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min, 107 unsigned int mult_max, unsigned long rate); 108 109 long clk_round_parent(struct clk *clk, unsigned long target, 110 unsigned long *best_freq, unsigned long *parent_freq, 111 unsigned int div_min, unsigned int div_max); 112 113 #define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _flags) \ 114 { \ 115 .parent = _parent, \ 116 .enable_reg = (void __iomem *)_enable_reg, \ 117 .enable_bit = _enable_bit, \ 118 .flags = _flags, \ 119 } 120 121 #define SH_CLK_MSTP32(_p, _r, _b, _f) \ 122 SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_32BIT) 123 124 #define SH_CLK_MSTP16(_p, _r, _b, _f) \ 125 SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_16BIT) 126 127 #define SH_CLK_MSTP8(_p, _r, _b, _f) \ 128 SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_8BIT) 129 130 int sh_clk_mstp_register(struct clk *clks, int nr); 131 132 /* 133 * MSTP registration never really cared about access size, despite the 134 * original enable/disable pairs assuming a 32-bit access. Clocks are 135 * responsible for defining their access sizes either directly or via the 136 * clock definition wrappers. 137 */ 138 static inline int __deprecated sh_clk_mstp32_register(struct clk *clks, int nr) 139 { 140 return sh_clk_mstp_register(clks, nr); 141 } 142 143 #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \ 144 { \ 145 .parent = _parent, \ 146 .enable_reg = (void __iomem *)_reg, \ 147 .enable_bit = _shift, \ 148 .arch_flags = _div_bitmap, \ 149 .flags = _flags, \ 150 } 151 152 struct clk_div4_table { 153 struct clk_div_mult_table *div_mult_table; 154 void (*kick)(struct clk *clk); 155 }; 156 157 int sh_clk_div4_register(struct clk *clks, int nr, 158 struct clk_div4_table *table); 159 int sh_clk_div4_enable_register(struct clk *clks, int nr, 160 struct clk_div4_table *table); 161 int sh_clk_div4_reparent_register(struct clk *clks, int nr, 162 struct clk_div4_table *table); 163 164 #define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \ 165 _num_parents, _src_shift, _src_width) \ 166 { \ 167 .enable_reg = (void __iomem *)_reg, \ 168 .flags = _flags, \ 169 .parent_table = _parents, \ 170 .parent_num = _num_parents, \ 171 .src_shift = _src_shift, \ 172 .src_width = _src_width, \ 173 } 174 175 #define SH_CLK_DIV6(_parent, _reg, _flags) \ 176 { \ 177 .parent = _parent, \ 178 .enable_reg = (void __iomem *)_reg, \ 179 .flags = _flags, \ 180 } 181 182 int sh_clk_div6_register(struct clk *clks, int nr); 183 int sh_clk_div6_reparent_register(struct clk *clks, int nr); 184 185 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } 186 #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk } 187 #define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk } 188 189 #endif /* __SH_CLOCK_H */ 190