1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 274e200c7SFlorian Fainelli #ifndef _LINUX_SERIAL_BCM63XX_H 374e200c7SFlorian Fainelli #define _LINUX_SERIAL_BCM63XX_H 474e200c7SFlorian Fainelli 574e200c7SFlorian Fainelli /* UART Control Register */ 674e200c7SFlorian Fainelli #define UART_CTL_REG 0x0 774e200c7SFlorian Fainelli #define UART_CTL_RXTMOUTCNT_SHIFT 0 874e200c7SFlorian Fainelli #define UART_CTL_RXTMOUTCNT_MASK (0x1f << UART_CTL_RXTMOUTCNT_SHIFT) 974e200c7SFlorian Fainelli #define UART_CTL_RSTTXDN_SHIFT 5 1074e200c7SFlorian Fainelli #define UART_CTL_RSTTXDN_MASK (1 << UART_CTL_RSTTXDN_SHIFT) 1174e200c7SFlorian Fainelli #define UART_CTL_RSTRXFIFO_SHIFT 6 1274e200c7SFlorian Fainelli #define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT) 1374e200c7SFlorian Fainelli #define UART_CTL_RSTTXFIFO_SHIFT 7 1474e200c7SFlorian Fainelli #define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT) 1574e200c7SFlorian Fainelli #define UART_CTL_STOPBITS_SHIFT 8 1674e200c7SFlorian Fainelli #define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT) 1774e200c7SFlorian Fainelli #define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT) 1874e200c7SFlorian Fainelli #define UART_CTL_STOPBITS_2 (0xf << UART_CTL_STOPBITS_SHIFT) 1974e200c7SFlorian Fainelli #define UART_CTL_BITSPERSYM_SHIFT 12 2074e200c7SFlorian Fainelli #define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT) 2174e200c7SFlorian Fainelli #define UART_CTL_XMITBRK_SHIFT 14 2274e200c7SFlorian Fainelli #define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT) 2374e200c7SFlorian Fainelli #define UART_CTL_RSVD_SHIFT 15 2474e200c7SFlorian Fainelli #define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT) 2574e200c7SFlorian Fainelli #define UART_CTL_RXPAREVEN_SHIFT 16 2674e200c7SFlorian Fainelli #define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT) 2774e200c7SFlorian Fainelli #define UART_CTL_RXPAREN_SHIFT 17 2874e200c7SFlorian Fainelli #define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT) 2974e200c7SFlorian Fainelli #define UART_CTL_TXPAREVEN_SHIFT 18 3074e200c7SFlorian Fainelli #define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT) 3174e200c7SFlorian Fainelli #define UART_CTL_TXPAREN_SHIFT 18 3274e200c7SFlorian Fainelli #define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT) 3374e200c7SFlorian Fainelli #define UART_CTL_LOOPBACK_SHIFT 20 3474e200c7SFlorian Fainelli #define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT) 3574e200c7SFlorian Fainelli #define UART_CTL_RXEN_SHIFT 21 3674e200c7SFlorian Fainelli #define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT) 3774e200c7SFlorian Fainelli #define UART_CTL_TXEN_SHIFT 22 3874e200c7SFlorian Fainelli #define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT) 3974e200c7SFlorian Fainelli #define UART_CTL_BRGEN_SHIFT 23 4074e200c7SFlorian Fainelli #define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT) 4174e200c7SFlorian Fainelli 4274e200c7SFlorian Fainelli /* UART Baudword register */ 4374e200c7SFlorian Fainelli #define UART_BAUD_REG 0x4 4474e200c7SFlorian Fainelli 4574e200c7SFlorian Fainelli /* UART Misc Control register */ 4674e200c7SFlorian Fainelli #define UART_MCTL_REG 0x8 4774e200c7SFlorian Fainelli #define UART_MCTL_DTR_SHIFT 0 4874e200c7SFlorian Fainelli #define UART_MCTL_DTR_MASK (1 << UART_MCTL_DTR_SHIFT) 4974e200c7SFlorian Fainelli #define UART_MCTL_RTS_SHIFT 1 5074e200c7SFlorian Fainelli #define UART_MCTL_RTS_MASK (1 << UART_MCTL_RTS_SHIFT) 5174e200c7SFlorian Fainelli #define UART_MCTL_RXFIFOTHRESH_SHIFT 8 5274e200c7SFlorian Fainelli #define UART_MCTL_RXFIFOTHRESH_MASK (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT) 5374e200c7SFlorian Fainelli #define UART_MCTL_TXFIFOTHRESH_SHIFT 12 5474e200c7SFlorian Fainelli #define UART_MCTL_TXFIFOTHRESH_MASK (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT) 5574e200c7SFlorian Fainelli #define UART_MCTL_RXFIFOFILL_SHIFT 16 5674e200c7SFlorian Fainelli #define UART_MCTL_RXFIFOFILL_MASK (0x1f << UART_MCTL_RXFIFOFILL_SHIFT) 5774e200c7SFlorian Fainelli #define UART_MCTL_TXFIFOFILL_SHIFT 24 5874e200c7SFlorian Fainelli #define UART_MCTL_TXFIFOFILL_MASK (0x1f << UART_MCTL_TXFIFOFILL_SHIFT) 5974e200c7SFlorian Fainelli 6074e200c7SFlorian Fainelli /* UART External Input Configuration register */ 6174e200c7SFlorian Fainelli #define UART_EXTINP_REG 0xc 6274e200c7SFlorian Fainelli #define UART_EXTINP_RI_SHIFT 0 6374e200c7SFlorian Fainelli #define UART_EXTINP_RI_MASK (1 << UART_EXTINP_RI_SHIFT) 6474e200c7SFlorian Fainelli #define UART_EXTINP_CTS_SHIFT 1 6574e200c7SFlorian Fainelli #define UART_EXTINP_CTS_MASK (1 << UART_EXTINP_CTS_SHIFT) 6674e200c7SFlorian Fainelli #define UART_EXTINP_DCD_SHIFT 2 6774e200c7SFlorian Fainelli #define UART_EXTINP_DCD_MASK (1 << UART_EXTINP_DCD_SHIFT) 6874e200c7SFlorian Fainelli #define UART_EXTINP_DSR_SHIFT 3 6974e200c7SFlorian Fainelli #define UART_EXTINP_DSR_MASK (1 << UART_EXTINP_DSR_SHIFT) 7074e200c7SFlorian Fainelli #define UART_EXTINP_IRSTAT(x) (1 << (x + 4)) 7174e200c7SFlorian Fainelli #define UART_EXTINP_IRMASK(x) (1 << (x + 8)) 7274e200c7SFlorian Fainelli #define UART_EXTINP_IR_RI 0 7374e200c7SFlorian Fainelli #define UART_EXTINP_IR_CTS 1 7474e200c7SFlorian Fainelli #define UART_EXTINP_IR_DCD 2 7574e200c7SFlorian Fainelli #define UART_EXTINP_IR_DSR 3 7674e200c7SFlorian Fainelli #define UART_EXTINP_RI_NOSENSE_SHIFT 16 7774e200c7SFlorian Fainelli #define UART_EXTINP_RI_NOSENSE_MASK (1 << UART_EXTINP_RI_NOSENSE_SHIFT) 7874e200c7SFlorian Fainelli #define UART_EXTINP_CTS_NOSENSE_SHIFT 17 7974e200c7SFlorian Fainelli #define UART_EXTINP_CTS_NOSENSE_MASK (1 << UART_EXTINP_CTS_NOSENSE_SHIFT) 8074e200c7SFlorian Fainelli #define UART_EXTINP_DCD_NOSENSE_SHIFT 18 8174e200c7SFlorian Fainelli #define UART_EXTINP_DCD_NOSENSE_MASK (1 << UART_EXTINP_DCD_NOSENSE_SHIFT) 8274e200c7SFlorian Fainelli #define UART_EXTINP_DSR_NOSENSE_SHIFT 19 8374e200c7SFlorian Fainelli #define UART_EXTINP_DSR_NOSENSE_MASK (1 << UART_EXTINP_DSR_NOSENSE_SHIFT) 8474e200c7SFlorian Fainelli 8574e200c7SFlorian Fainelli /* UART Interrupt register */ 8674e200c7SFlorian Fainelli #define UART_IR_REG 0x10 8774e200c7SFlorian Fainelli #define UART_IR_MASK(x) (1 << (x + 16)) 8874e200c7SFlorian Fainelli #define UART_IR_STAT(x) (1 << (x)) 8974e200c7SFlorian Fainelli #define UART_IR_EXTIP 0 9074e200c7SFlorian Fainelli #define UART_IR_TXUNDER 1 9174e200c7SFlorian Fainelli #define UART_IR_TXOVER 2 9274e200c7SFlorian Fainelli #define UART_IR_TXTRESH 3 9374e200c7SFlorian Fainelli #define UART_IR_TXRDLATCH 4 9474e200c7SFlorian Fainelli #define UART_IR_TXEMPTY 5 9574e200c7SFlorian Fainelli #define UART_IR_RXUNDER 6 9674e200c7SFlorian Fainelli #define UART_IR_RXOVER 7 9774e200c7SFlorian Fainelli #define UART_IR_RXTIMEOUT 8 9874e200c7SFlorian Fainelli #define UART_IR_RXFULL 9 9974e200c7SFlorian Fainelli #define UART_IR_RXTHRESH 10 10074e200c7SFlorian Fainelli #define UART_IR_RXNOTEMPTY 11 10174e200c7SFlorian Fainelli #define UART_IR_RXFRAMEERR 12 10274e200c7SFlorian Fainelli #define UART_IR_RXPARERR 13 10374e200c7SFlorian Fainelli #define UART_IR_RXBRK 14 10474e200c7SFlorian Fainelli #define UART_IR_TXDONE 15 10574e200c7SFlorian Fainelli 10674e200c7SFlorian Fainelli /* UART Fifo register */ 10774e200c7SFlorian Fainelli #define UART_FIFO_REG 0x14 10874e200c7SFlorian Fainelli #define UART_FIFO_VALID_SHIFT 0 10974e200c7SFlorian Fainelli #define UART_FIFO_VALID_MASK 0xff 11074e200c7SFlorian Fainelli #define UART_FIFO_FRAMEERR_SHIFT 8 11174e200c7SFlorian Fainelli #define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT) 11274e200c7SFlorian Fainelli #define UART_FIFO_PARERR_SHIFT 9 11374e200c7SFlorian Fainelli #define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT) 11474e200c7SFlorian Fainelli #define UART_FIFO_BRKDET_SHIFT 10 11574e200c7SFlorian Fainelli #define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT) 11674e200c7SFlorian Fainelli #define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \ 11774e200c7SFlorian Fainelli UART_FIFO_PARERR_MASK | \ 11874e200c7SFlorian Fainelli UART_FIFO_BRKDET_MASK) 11974e200c7SFlorian Fainelli 12074e200c7SFlorian Fainelli #endif /* _LINUX_SERIAL_BCM63XX_H */ 121