1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _RESCTRL_H 3 #define _RESCTRL_H 4 5 #include <linux/kernel.h> 6 #include <linux/list.h> 7 #include <linux/pid.h> 8 9 /* CLOSID, RMID value used by the default control group */ 10 #define RESCTRL_RESERVED_CLOSID 0 11 #define RESCTRL_RESERVED_RMID 0 12 13 #define RESCTRL_PICK_ANY_CPU -1 14 15 #ifdef CONFIG_PROC_CPU_RESCTRL 16 17 int proc_resctrl_show(struct seq_file *m, 18 struct pid_namespace *ns, 19 struct pid *pid, 20 struct task_struct *tsk); 21 22 #endif 23 24 /* max value for struct rdt_domain's mbps_val */ 25 #define MBA_MAX_MBPS U32_MAX 26 27 /** 28 * enum resctrl_conf_type - The type of configuration. 29 * @CDP_NONE: No prioritisation, both code and data are controlled or monitored. 30 * @CDP_CODE: Configuration applies to instruction fetches. 31 * @CDP_DATA: Configuration applies to reads and writes. 32 */ 33 enum resctrl_conf_type { 34 CDP_NONE, 35 CDP_CODE, 36 CDP_DATA, 37 }; 38 39 #define CDP_NUM_TYPES (CDP_DATA + 1) 40 41 /* 42 * Event IDs, the values match those used to program IA32_QM_EVTSEL before 43 * reading IA32_QM_CTR on RDT systems. 44 */ 45 enum resctrl_event_id { 46 QOS_L3_OCCUP_EVENT_ID = 0x01, 47 QOS_L3_MBM_TOTAL_EVENT_ID = 0x02, 48 QOS_L3_MBM_LOCAL_EVENT_ID = 0x03, 49 }; 50 51 /** 52 * struct resctrl_staged_config - parsed configuration to be applied 53 * @new_ctrl: new ctrl value to be loaded 54 * @have_new_ctrl: whether the user provided new_ctrl is valid 55 */ 56 struct resctrl_staged_config { 57 u32 new_ctrl; 58 bool have_new_ctrl; 59 }; 60 61 enum resctrl_domain_type { 62 RESCTRL_CTRL_DOMAIN, 63 RESCTRL_MON_DOMAIN, 64 }; 65 66 /** 67 * struct rdt_domain_hdr - common header for different domain types 68 * @list: all instances of this resource 69 * @id: unique id for this instance 70 * @type: type of this instance 71 * @cpu_mask: which CPUs share this resource 72 */ 73 struct rdt_domain_hdr { 74 struct list_head list; 75 int id; 76 enum resctrl_domain_type type; 77 struct cpumask cpu_mask; 78 }; 79 80 /** 81 * struct rdt_domain - group of CPUs sharing a resctrl resource 82 * @hdr: common header for different domain types 83 * @rmid_busy_llc: bitmap of which limbo RMIDs are above threshold 84 * @mbm_total: saved state for MBM total bandwidth 85 * @mbm_local: saved state for MBM local bandwidth 86 * @mbm_over: worker to periodically read MBM h/w counters 87 * @cqm_limbo: worker to periodically read CQM h/w counters 88 * @mbm_work_cpu: worker CPU for MBM h/w counters 89 * @cqm_work_cpu: worker CPU for CQM h/w counters 90 * @plr: pseudo-locked region (if any) associated with domain 91 * @staged_config: parsed configuration to be applied 92 * @mbps_val: When mba_sc is enabled, this holds the array of user 93 * specified control values for mba_sc in MBps, indexed 94 * by closid 95 */ 96 struct rdt_domain { 97 struct rdt_domain_hdr hdr; 98 unsigned long *rmid_busy_llc; 99 struct mbm_state *mbm_total; 100 struct mbm_state *mbm_local; 101 struct delayed_work mbm_over; 102 struct delayed_work cqm_limbo; 103 int mbm_work_cpu; 104 int cqm_work_cpu; 105 struct pseudo_lock_region *plr; 106 struct resctrl_staged_config staged_config[CDP_NUM_TYPES]; 107 u32 *mbps_val; 108 }; 109 110 /** 111 * struct resctrl_cache - Cache allocation related data 112 * @cbm_len: Length of the cache bit mask 113 * @min_cbm_bits: Minimum number of consecutive bits to be set. 114 * The value 0 means the architecture can support 115 * zero CBM. 116 * @shareable_bits: Bitmask of shareable resource with other 117 * executing entities 118 * @arch_has_sparse_bitmasks: True if a bitmask like f00f is valid. 119 * @arch_has_per_cpu_cfg: True if QOS_CFG register for this cache 120 * level has CPU scope. 121 */ 122 struct resctrl_cache { 123 unsigned int cbm_len; 124 unsigned int min_cbm_bits; 125 unsigned int shareable_bits; 126 bool arch_has_sparse_bitmasks; 127 bool arch_has_per_cpu_cfg; 128 }; 129 130 /** 131 * enum membw_throttle_mode - System's memory bandwidth throttling mode 132 * @THREAD_THROTTLE_UNDEFINED: Not relevant to the system 133 * @THREAD_THROTTLE_MAX: Memory bandwidth is throttled at the core 134 * always using smallest bandwidth percentage 135 * assigned to threads, aka "max throttling" 136 * @THREAD_THROTTLE_PER_THREAD: Memory bandwidth is throttled at the thread 137 */ 138 enum membw_throttle_mode { 139 THREAD_THROTTLE_UNDEFINED = 0, 140 THREAD_THROTTLE_MAX, 141 THREAD_THROTTLE_PER_THREAD, 142 }; 143 144 /** 145 * struct resctrl_membw - Memory bandwidth allocation related data 146 * @min_bw: Minimum memory bandwidth percentage user can request 147 * @bw_gran: Granularity at which the memory bandwidth is allocated 148 * @delay_linear: True if memory B/W delay is in linear scale 149 * @arch_needs_linear: True if we can't configure non-linear resources 150 * @throttle_mode: Bandwidth throttling mode when threads request 151 * different memory bandwidths 152 * @mba_sc: True if MBA software controller(mba_sc) is enabled 153 * @mb_map: Mapping of memory B/W percentage to memory B/W delay 154 */ 155 struct resctrl_membw { 156 u32 min_bw; 157 u32 bw_gran; 158 u32 delay_linear; 159 bool arch_needs_linear; 160 enum membw_throttle_mode throttle_mode; 161 bool mba_sc; 162 u32 *mb_map; 163 }; 164 165 struct rdt_parse_data; 166 struct resctrl_schema; 167 168 enum resctrl_scope { 169 RESCTRL_L2_CACHE = 2, 170 RESCTRL_L3_CACHE = 3, 171 }; 172 173 /** 174 * struct rdt_resource - attributes of a resctrl resource 175 * @rid: The index of the resource 176 * @alloc_capable: Is allocation available on this machine 177 * @mon_capable: Is monitor feature available on this machine 178 * @num_rmid: Number of RMIDs available 179 * @ctrl_scope: Scope of this resource for control functions 180 * @mon_scope: Scope of this resource for monitor functions 181 * @cache: Cache allocation related data 182 * @membw: If the component has bandwidth controls, their properties. 183 * @ctrl_domains: RCU list of all control domains for this resource 184 * @mon_domains: RCU list of all monitor domains for this resource 185 * @name: Name to use in "schemata" file. 186 * @data_width: Character width of data when displaying 187 * @default_ctrl: Specifies default cache cbm or memory B/W percent. 188 * @format_str: Per resource format string to show domain value 189 * @parse_ctrlval: Per resource function pointer to parse control values 190 * @evt_list: List of monitoring events 191 * @fflags: flags to choose base and info files 192 * @cdp_capable: Is the CDP feature available on this resource 193 */ 194 struct rdt_resource { 195 int rid; 196 bool alloc_capable; 197 bool mon_capable; 198 int num_rmid; 199 enum resctrl_scope ctrl_scope; 200 enum resctrl_scope mon_scope; 201 struct resctrl_cache cache; 202 struct resctrl_membw membw; 203 struct list_head ctrl_domains; 204 struct list_head mon_domains; 205 char *name; 206 int data_width; 207 u32 default_ctrl; 208 const char *format_str; 209 int (*parse_ctrlval)(struct rdt_parse_data *data, 210 struct resctrl_schema *s, 211 struct rdt_domain *d); 212 struct list_head evt_list; 213 unsigned long fflags; 214 bool cdp_capable; 215 }; 216 217 /** 218 * struct resctrl_schema - configuration abilities of a resource presented to 219 * user-space 220 * @list: Member of resctrl_schema_all. 221 * @name: The name to use in the "schemata" file. 222 * @conf_type: Whether this schema is specific to code/data. 223 * @res: The resource structure exported by the architecture to describe 224 * the hardware that is configured by this schema. 225 * @num_closid: The number of closid that can be used with this schema. When 226 * features like CDP are enabled, this will be lower than the 227 * hardware supports for the resource. 228 */ 229 struct resctrl_schema { 230 struct list_head list; 231 char name[8]; 232 enum resctrl_conf_type conf_type; 233 struct rdt_resource *res; 234 u32 num_closid; 235 }; 236 237 /* The number of closid supported by this resource regardless of CDP */ 238 u32 resctrl_arch_get_num_closid(struct rdt_resource *r); 239 int resctrl_arch_update_domains(struct rdt_resource *r, u32 closid); 240 241 /* 242 * Update the ctrl_val and apply this config right now. 243 * Must be called on one of the domain's CPUs. 244 */ 245 int resctrl_arch_update_one(struct rdt_resource *r, struct rdt_domain *d, 246 u32 closid, enum resctrl_conf_type t, u32 cfg_val); 247 248 u32 resctrl_arch_get_config(struct rdt_resource *r, struct rdt_domain *d, 249 u32 closid, enum resctrl_conf_type type); 250 int resctrl_online_ctrl_domain(struct rdt_resource *r, struct rdt_domain *d); 251 int resctrl_online_mon_domain(struct rdt_resource *r, struct rdt_domain *d); 252 void resctrl_offline_ctrl_domain(struct rdt_resource *r, struct rdt_domain *d); 253 void resctrl_offline_mon_domain(struct rdt_resource *r, struct rdt_domain *d); 254 void resctrl_online_cpu(unsigned int cpu); 255 void resctrl_offline_cpu(unsigned int cpu); 256 257 /** 258 * resctrl_arch_rmid_read() - Read the eventid counter corresponding to rmid 259 * for this resource and domain. 260 * @r: resource that the counter should be read from. 261 * @d: domain that the counter should be read from. 262 * @closid: closid that matches the rmid. Depending on the architecture, the 263 * counter may match traffic of both @closid and @rmid, or @rmid 264 * only. 265 * @rmid: rmid of the counter to read. 266 * @eventid: eventid to read, e.g. L3 occupancy. 267 * @val: result of the counter read in bytes. 268 * @arch_mon_ctx: An architecture specific value from 269 * resctrl_arch_mon_ctx_alloc(), for MPAM this identifies 270 * the hardware monitor allocated for this read request. 271 * 272 * Some architectures need to sleep when first programming some of the counters. 273 * (specifically: arm64's MPAM cache occupancy counters can return 'not ready' 274 * for a short period of time). Call from a non-migrateable process context on 275 * a CPU that belongs to domain @d. e.g. use smp_call_on_cpu() or 276 * schedule_work_on(). This function can be called with interrupts masked, 277 * e.g. using smp_call_function_any(), but may consistently return an error. 278 * 279 * Return: 280 * 0 on success, or -EIO, -EINVAL etc on error. 281 */ 282 int resctrl_arch_rmid_read(struct rdt_resource *r, struct rdt_domain *d, 283 u32 closid, u32 rmid, enum resctrl_event_id eventid, 284 u64 *val, void *arch_mon_ctx); 285 286 /** 287 * resctrl_arch_rmid_read_context_check() - warn about invalid contexts 288 * 289 * When built with CONFIG_DEBUG_ATOMIC_SLEEP generate a warning when 290 * resctrl_arch_rmid_read() is called with preemption disabled. 291 * 292 * The contract with resctrl_arch_rmid_read() is that if interrupts 293 * are unmasked, it can sleep. This allows NOHZ_FULL systems to use an 294 * IPI, (and fail if the call needed to sleep), while most of the time 295 * the work is scheduled, allowing the call to sleep. 296 */ 297 static inline void resctrl_arch_rmid_read_context_check(void) 298 { 299 if (!irqs_disabled()) 300 might_sleep(); 301 } 302 303 /** 304 * resctrl_arch_reset_rmid() - Reset any private state associated with rmid 305 * and eventid. 306 * @r: The domain's resource. 307 * @d: The rmid's domain. 308 * @closid: closid that matches the rmid. Depending on the architecture, the 309 * counter may match traffic of both @closid and @rmid, or @rmid only. 310 * @rmid: The rmid whose counter values should be reset. 311 * @eventid: The eventid whose counter values should be reset. 312 * 313 * This can be called from any CPU. 314 */ 315 void resctrl_arch_reset_rmid(struct rdt_resource *r, struct rdt_domain *d, 316 u32 closid, u32 rmid, 317 enum resctrl_event_id eventid); 318 319 /** 320 * resctrl_arch_reset_rmid_all() - Reset all private state associated with 321 * all rmids and eventids. 322 * @r: The resctrl resource. 323 * @d: The domain for which all architectural counter state will 324 * be cleared. 325 * 326 * This can be called from any CPU. 327 */ 328 void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_domain *d); 329 330 extern unsigned int resctrl_rmid_realloc_threshold; 331 extern unsigned int resctrl_rmid_realloc_limit; 332 333 #endif /* _RESCTRL_H */ 334