1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015 QLogic Corporation 3 * 4 * This software is available under the terms of the GNU General Public License 5 * (GPL) Version 2, available from the file COPYING in the main directory of 6 * this source tree. 7 */ 8 9 #ifndef __ETH_COMMON__ 10 #define __ETH_COMMON__ 11 12 /********************/ 13 /* ETH FW CONSTANTS */ 14 /********************/ 15 #define ETH_CACHE_LINE_SIZE 64 16 17 #define ETH_MAX_RAMROD_PER_CON 8 18 #define ETH_TX_BD_PAGE_SIZE_BYTES 4096 19 #define ETH_RX_BD_PAGE_SIZE_BYTES 4096 20 #define ETH_RX_CQE_PAGE_SIZE_BYTES 4096 21 #define ETH_RX_NUM_NEXT_PAGE_BDS 2 22 23 #define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1 24 #define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18 25 #define ETH_TX_MAX_LSO_HDR_NBD 4 26 #define ETH_TX_MIN_BDS_PER_LSO_PKT 3 27 #define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3 28 #define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2 29 #define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2 30 #define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 12 + 8)) 31 #define ETH_TX_MAX_LSO_HDR_BYTES 510 32 33 #define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS 34 35 /* Maximum number of buffers, used for RX packet placement */ 36 #define ETH_RX_MAX_BUFF_PER_PKT 5 37 38 /* num of MAC/VLAN filters */ 39 #define ETH_NUM_MAC_FILTERS 512 40 #define ETH_NUM_VLAN_FILTERS 512 41 42 /* approx. multicast constants */ 43 #define ETH_MULTICAST_BIN_FROM_MAC_SEED 0 44 #define ETH_MULTICAST_MAC_BINS 256 45 #define ETH_MULTICAST_MAC_BINS_IN_REGS (ETH_MULTICAST_MAC_BINS / 32) 46 47 /* ethernet vport update constants */ 48 #define ETH_FILTER_RULES_COUNT 10 49 #define ETH_RSS_IND_TABLE_ENTRIES_NUM 128 50 #define ETH_RSS_KEY_SIZE_REGS 10 51 #define ETH_RSS_ENGINE_NUM_K2 207 52 #define ETH_RSS_ENGINE_NUM_BB 127 53 54 /* TPA constants */ 55 #define ETH_TPA_MAX_AGGS_NUM 64 56 #define ETH_TPA_CQE_START_LEN_LIST_SIZE ETH_RX_MAX_BUFF_PER_PKT 57 #define ETH_TPA_CQE_CONT_LEN_LIST_SIZE 6 58 #define ETH_TPA_CQE_END_LEN_LIST_SIZE 4 59 60 /* Queue Zone sizes */ 61 #define TSTORM_QZONE_SIZE 0 62 #define MSTORM_QZONE_SIZE sizeof(struct mstorm_eth_queue_zone) 63 #define USTORM_QZONE_SIZE sizeof(struct ustorm_eth_queue_zone) 64 #define XSTORM_QZONE_SIZE 0 65 #define YSTORM_QZONE_SIZE sizeof(struct ystorm_eth_queue_zone) 66 #define PSTORM_QZONE_SIZE 0 67 68 /* Interrupt coalescing TimeSet */ 69 struct coalescing_timeset { 70 u8 timeset; 71 u8 valid; 72 }; 73 74 struct eth_tx_1st_bd_flags { 75 u8 bitfields; 76 #define ETH_TX_1ST_BD_FLAGS_START_BD_MASK 0x1 77 #define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT 0 78 #define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1 79 #define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 1 80 #define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK 0x1 81 #define ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT 2 82 #define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK 0x1 83 #define ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT 3 84 #define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK 0x1 85 #define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT 4 86 #define ETH_TX_1ST_BD_FLAGS_LSO_MASK 0x1 87 #define ETH_TX_1ST_BD_FLAGS_LSO_SHIFT 5 88 #define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK 0x1 89 #define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT 6 90 #define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1 91 #define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT 7 92 }; 93 94 /* The parsing information data fo rthe first tx bd of a given packet. */ 95 struct eth_tx_data_1st_bd { 96 __le16 vlan; 97 u8 nbds; 98 struct eth_tx_1st_bd_flags bd_flags; 99 __le16 bitfields; 100 #define ETH_TX_DATA_1ST_BD_TUNN_CFG_OVERRIDE_MASK 0x1 101 #define ETH_TX_DATA_1ST_BD_TUNN_CFG_OVERRIDE_SHIFT 0 102 #define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1 103 #define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT 1 104 #define ETH_TX_DATA_1ST_BD_FW_USE_ONLY_MASK 0x3FFF 105 #define ETH_TX_DATA_1ST_BD_FW_USE_ONLY_SHIFT 2 106 }; 107 108 /* The parsing information data for the second tx bd of a given packet. */ 109 struct eth_tx_data_2nd_bd { 110 __le16 tunn_ip_size; 111 __le16 bitfields1; 112 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK 0xF 113 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0 114 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK 0x3 115 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT 4 116 #define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_MASK 0x3 117 #define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_SHIFT 6 118 #define ETH_TX_DATA_2ND_BD_START_BD_MASK 0x1 119 #define ETH_TX_DATA_2ND_BD_START_BD_SHIFT 8 120 #define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK 0x3 121 #define ETH_TX_DATA_2ND_BD_TUNN_TYPE_SHIFT 9 122 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_MASK 0x1 123 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT 11 124 #define ETH_TX_DATA_2ND_BD_IPV6_EXT_MASK 0x1 125 #define ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT 12 126 #define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_MASK 0x1 127 #define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT 13 128 #define ETH_TX_DATA_2ND_BD_L4_UDP_MASK 0x1 129 #define ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT 14 130 #define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_MASK 0x1 131 #define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT 15 132 __le16 bitfields2; 133 #define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK 0x1FFF 134 #define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT 0 135 #define ETH_TX_DATA_2ND_BD_RESERVED0_MASK 0x7 136 #define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT 13 137 }; 138 139 /* Regular ETH Rx FP CQE. */ 140 struct eth_fast_path_rx_reg_cqe { 141 u8 type; 142 u8 bitfields; 143 #define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK 0x7 144 #define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT 0 145 #define ETH_FAST_PATH_RX_REG_CQE_TC_MASK 0xF 146 #define ETH_FAST_PATH_RX_REG_CQE_TC_SHIFT 3 147 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK 0x1 148 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_SHIFT 7 149 __le16 pkt_len; 150 struct parsing_and_err_flags pars_flags; 151 __le16 vlan_tag; 152 __le32 rss_hash; 153 __le16 len_on_first_bd; 154 u8 placement_offset; 155 struct tunnel_parsing_flags tunnel_pars_flags; 156 u8 bd_num; 157 u8 reserved[7]; 158 u32 fw_debug; 159 u8 reserved1[3]; 160 u8 flags; 161 #define ETH_FAST_PATH_RX_REG_CQE_VALID_MASK 0x1 162 #define ETH_FAST_PATH_RX_REG_CQE_VALID_SHIFT 0 163 #define ETH_FAST_PATH_RX_REG_CQE_VALID_TOGGLE_MASK 0x1 164 #define ETH_FAST_PATH_RX_REG_CQE_VALID_TOGGLE_SHIFT 1 165 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED2_MASK 0x3F 166 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED2_SHIFT 2 167 }; 168 169 /* TPA-continue ETH Rx FP CQE. */ 170 struct eth_fast_path_rx_tpa_cont_cqe { 171 u8 type; 172 u8 tpa_agg_index; 173 __le16 len_list[ETH_TPA_CQE_CONT_LEN_LIST_SIZE]; 174 u8 reserved[5]; 175 u8 reserved1; 176 __le16 reserved2[ETH_TPA_CQE_CONT_LEN_LIST_SIZE]; 177 }; 178 179 /* TPA-end ETH Rx FP CQE. */ 180 struct eth_fast_path_rx_tpa_end_cqe { 181 u8 type; 182 u8 tpa_agg_index; 183 __le16 total_packet_len; 184 u8 num_of_bds; 185 u8 end_reason; 186 __le16 num_of_coalesced_segs; 187 __le32 ts_delta; 188 __le16 len_list[ETH_TPA_CQE_END_LEN_LIST_SIZE]; 189 u8 reserved1[3]; 190 u8 reserved2; 191 __le16 reserved3[ETH_TPA_CQE_END_LEN_LIST_SIZE]; 192 }; 193 194 /* TPA-start ETH Rx FP CQE. */ 195 struct eth_fast_path_rx_tpa_start_cqe { 196 u8 type; 197 u8 bitfields; 198 #define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_MASK 0x7 199 #define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_SHIFT 0 200 #define ETH_FAST_PATH_RX_TPA_START_CQE_TC_MASK 0xF 201 #define ETH_FAST_PATH_RX_TPA_START_CQE_TC_SHIFT 3 202 #define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_MASK 0x1 203 #define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_SHIFT 7 204 __le16 seg_len; 205 struct parsing_and_err_flags pars_flags; 206 __le16 vlan_tag; 207 __le32 rss_hash; 208 __le16 len_on_first_bd; 209 u8 placement_offset; 210 struct tunnel_parsing_flags tunnel_pars_flags; 211 u8 tpa_agg_index; 212 u8 header_len; 213 __le16 ext_bd_len_list[ETH_TPA_CQE_START_LEN_LIST_SIZE]; 214 u32 fw_debug; 215 }; 216 217 /* The L4 pseudo checksum mode for Ethernet */ 218 enum eth_l4_pseudo_checksum_mode { 219 ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH, 220 ETH_L4_PSEUDO_CSUM_ZERO_LENGTH, 221 MAX_ETH_L4_PSEUDO_CHECKSUM_MODE 222 }; 223 224 struct eth_rx_bd { 225 struct regpair addr; 226 }; 227 228 /* regular ETH Rx SP CQE */ 229 struct eth_slow_path_rx_cqe { 230 u8 type; 231 u8 ramrod_cmd_id; 232 u8 error_flag; 233 u8 reserved[25]; 234 __le16 echo; 235 u8 reserved1; 236 u8 flags; 237 /* for PMD mode - valid indication */ 238 #define ETH_SLOW_PATH_RX_CQE_VALID_MASK 0x1 239 #define ETH_SLOW_PATH_RX_CQE_VALID_SHIFT 0 240 /* for PMD mode - valid toggle indication */ 241 #define ETH_SLOW_PATH_RX_CQE_VALID_TOGGLE_MASK 0x1 242 #define ETH_SLOW_PATH_RX_CQE_VALID_TOGGLE_SHIFT 1 243 #define ETH_SLOW_PATH_RX_CQE_RESERVED2_MASK 0x3F 244 #define ETH_SLOW_PATH_RX_CQE_RESERVED2_SHIFT 2 245 }; 246 247 /* union for all ETH Rx CQE types */ 248 union eth_rx_cqe { 249 struct eth_fast_path_rx_reg_cqe fast_path_regular; 250 struct eth_fast_path_rx_tpa_start_cqe fast_path_tpa_start; 251 struct eth_fast_path_rx_tpa_cont_cqe fast_path_tpa_cont; 252 struct eth_fast_path_rx_tpa_end_cqe fast_path_tpa_end; 253 struct eth_slow_path_rx_cqe slow_path; 254 }; 255 256 /* ETH Rx CQE type */ 257 enum eth_rx_cqe_type { 258 ETH_RX_CQE_TYPE_UNUSED, 259 ETH_RX_CQE_TYPE_REGULAR, 260 ETH_RX_CQE_TYPE_SLOW_PATH, 261 ETH_RX_CQE_TYPE_TPA_START, 262 ETH_RX_CQE_TYPE_TPA_CONT, 263 ETH_RX_CQE_TYPE_TPA_END, 264 MAX_ETH_RX_CQE_TYPE 265 }; 266 267 /* ETH Rx producers data */ 268 struct eth_rx_prod_data { 269 __le16 bd_prod; 270 __le16 cqe_prod; 271 __le16 reserved; 272 __le16 reserved1; 273 }; 274 275 /* The first tx bd of a given packet */ 276 struct eth_tx_1st_bd { 277 struct regpair addr; 278 __le16 nbytes; 279 struct eth_tx_data_1st_bd data; 280 }; 281 282 /* The second tx bd of a given packet */ 283 struct eth_tx_2nd_bd { 284 struct regpair addr; 285 __le16 nbytes; 286 struct eth_tx_data_2nd_bd data; 287 }; 288 289 /* The parsing information data for the third tx bd of a given packet. */ 290 struct eth_tx_data_3rd_bd { 291 __le16 lso_mss; 292 __le16 bitfields; 293 #define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK 0xF 294 #define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0 295 #define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK 0xF 296 #define ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT 4 297 #define ETH_TX_DATA_3RD_BD_START_BD_MASK 0x1 298 #define ETH_TX_DATA_3RD_BD_START_BD_SHIFT 8 299 #define ETH_TX_DATA_3RD_BD_RESERVED0_MASK 0x7F 300 #define ETH_TX_DATA_3RD_BD_RESERVED0_SHIFT 9 301 u8 tunn_l4_hdr_start_offset_w; 302 u8 tunn_hdr_size_w; 303 }; 304 305 /* The third tx bd of a given packet */ 306 struct eth_tx_3rd_bd { 307 struct regpair addr; 308 __le16 nbytes; 309 struct eth_tx_data_3rd_bd data; 310 }; 311 312 /* Complementary information for the regular tx bd of a given packet. */ 313 struct eth_tx_data_bd { 314 __le16 reserved0; 315 __le16 bitfields; 316 #define ETH_TX_DATA_BD_RESERVED1_MASK 0xFF 317 #define ETH_TX_DATA_BD_RESERVED1_SHIFT 0 318 #define ETH_TX_DATA_BD_START_BD_MASK 0x1 319 #define ETH_TX_DATA_BD_START_BD_SHIFT 8 320 #define ETH_TX_DATA_BD_RESERVED2_MASK 0x7F 321 #define ETH_TX_DATA_BD_RESERVED2_SHIFT 9 322 __le16 reserved3; 323 }; 324 325 /* The common non-special TX BD ring element */ 326 struct eth_tx_bd { 327 struct regpair addr; 328 __le16 nbytes; 329 struct eth_tx_data_bd data; 330 }; 331 332 union eth_tx_bd_types { 333 struct eth_tx_1st_bd first_bd; 334 struct eth_tx_2nd_bd second_bd; 335 struct eth_tx_3rd_bd third_bd; 336 struct eth_tx_bd reg_bd; 337 }; 338 339 /* Mstorm Queue Zone */ 340 struct mstorm_eth_queue_zone { 341 struct eth_rx_prod_data rx_producers; 342 __le32 reserved[2]; 343 }; 344 345 /* Ustorm Queue Zone */ 346 struct ustorm_eth_queue_zone { 347 struct coalescing_timeset int_coalescing_timeset; 348 __le16 reserved[3]; 349 }; 350 351 /* Ystorm Queue Zone */ 352 struct ystorm_eth_queue_zone { 353 struct coalescing_timeset int_coalescing_timeset; 354 __le16 reserved[3]; 355 }; 356 357 /* ETH doorbell data */ 358 struct eth_db_data { 359 u8 params; 360 #define ETH_DB_DATA_DEST_MASK 0x3 361 #define ETH_DB_DATA_DEST_SHIFT 0 362 #define ETH_DB_DATA_AGG_CMD_MASK 0x3 363 #define ETH_DB_DATA_AGG_CMD_SHIFT 2 364 #define ETH_DB_DATA_BYPASS_EN_MASK 0x1 365 #define ETH_DB_DATA_BYPASS_EN_SHIFT 4 366 #define ETH_DB_DATA_RESERVED_MASK 0x1 367 #define ETH_DB_DATA_RESERVED_SHIFT 5 368 #define ETH_DB_DATA_AGG_VAL_SEL_MASK 0x3 369 #define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6 370 u8 agg_flags; 371 __le16 bd_prod; 372 }; 373 374 #endif /* __ETH_COMMON__ */ 375