1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015 QLogic Corporation 3 * 4 * This software is available under the terms of the GNU General Public License 5 * (GPL) Version 2, available from the file COPYING in the main directory of 6 * this source tree. 7 */ 8 9 #ifndef __COMMON_HSI__ 10 #define __COMMON_HSI__ 11 12 #define CORE_SPQE_PAGE_SIZE_BYTES 4096 13 14 #define X_FINAL_CLEANUP_AGG_INT 1 15 #define NUM_OF_GLOBAL_QUEUES 128 16 17 /* Queue Zone sizes in bytes */ 18 #define TSTORM_QZONE_SIZE 8 19 #define MSTORM_QZONE_SIZE 0 20 #define USTORM_QZONE_SIZE 8 21 #define XSTORM_QZONE_SIZE 8 22 #define YSTORM_QZONE_SIZE 0 23 #define PSTORM_QZONE_SIZE 0 24 25 #define ETH_MAX_NUM_RX_QUEUES_PER_VF 16 26 27 #define FW_MAJOR_VERSION 8 28 #define FW_MINOR_VERSION 10 29 #define FW_REVISION_VERSION 5 30 #define FW_ENGINEERING_VERSION 0 31 32 /***********************/ 33 /* COMMON HW CONSTANTS */ 34 /***********************/ 35 36 /* PCI functions */ 37 #define MAX_NUM_PORTS_K2 (4) 38 #define MAX_NUM_PORTS_BB (2) 39 #define MAX_NUM_PORTS (MAX_NUM_PORTS_K2) 40 41 #define MAX_NUM_PFS_K2 (16) 42 #define MAX_NUM_PFS_BB (8) 43 #define MAX_NUM_PFS (MAX_NUM_PFS_K2) 44 #define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */ 45 46 #define MAX_NUM_VFS_K2 (192) 47 #define MAX_NUM_VFS_BB (120) 48 #define MAX_NUM_VFS (MAX_NUM_VFS_K2) 49 50 #define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB) 51 #define MAX_NUM_FUNCTIONS (MAX_NUM_PFS + MAX_NUM_VFS) 52 53 #define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB) 54 #define MAX_FUNCTION_NUMBER (MAX_NUM_PFS + MAX_NUM_VFS) 55 56 #define MAX_NUM_VPORTS_K2 (208) 57 #define MAX_NUM_VPORTS_BB (160) 58 #define MAX_NUM_VPORTS (MAX_NUM_VPORTS_K2) 59 60 #define MAX_NUM_L2_QUEUES_K2 (320) 61 #define MAX_NUM_L2_QUEUES_BB (256) 62 #define MAX_NUM_L2_QUEUES (MAX_NUM_L2_QUEUES_K2) 63 64 /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */ 65 #define NUM_PHYS_TCS_4PORT_K2 (4) 66 #define NUM_OF_PHYS_TCS (8) 67 68 #define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1) 69 #define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1) 70 71 #define LB_TC (NUM_OF_PHYS_TCS) 72 73 /* Num of possible traffic priority values */ 74 #define NUM_OF_PRIO (8) 75 76 #define MAX_NUM_VOQS_K2 (NUM_TCS_4PORT_K2 * MAX_NUM_PORTS_K2) 77 #define MAX_NUM_VOQS_BB (NUM_OF_TCS * MAX_NUM_PORTS_BB) 78 #define MAX_NUM_VOQS (MAX_NUM_VOQS_K2) 79 #define MAX_PHYS_VOQS (NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB) 80 81 /* CIDs */ 82 #define NUM_OF_CONNECTION_TYPES (8) 83 #define NUM_OF_LCIDS (320) 84 #define NUM_OF_LTIDS (320) 85 86 /*****************/ 87 /* CDU CONSTANTS */ 88 /*****************/ 89 90 #define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17) 91 #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff) 92 93 /*****************/ 94 /* DQ CONSTANTS */ 95 /*****************/ 96 97 /* DEMS */ 98 #define DQ_DEMS_LEGACY 0 99 100 /* XCM agg val selection */ 101 #define DQ_XCM_AGG_VAL_SEL_WORD2 0 102 #define DQ_XCM_AGG_VAL_SEL_WORD3 1 103 #define DQ_XCM_AGG_VAL_SEL_WORD4 2 104 #define DQ_XCM_AGG_VAL_SEL_WORD5 3 105 #define DQ_XCM_AGG_VAL_SEL_REG3 4 106 #define DQ_XCM_AGG_VAL_SEL_REG4 5 107 #define DQ_XCM_AGG_VAL_SEL_REG5 6 108 #define DQ_XCM_AGG_VAL_SEL_REG6 7 109 110 /* XCM agg val selection */ 111 #define DQ_XCM_CORE_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 112 #define DQ_XCM_CORE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 113 #define DQ_XCM_CORE_SPQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 114 #define DQ_XCM_ETH_EDPM_NUM_BDS_CMD DQ_XCM_AGG_VAL_SEL_WORD2 115 #define DQ_XCM_ETH_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 116 #define DQ_XCM_ETH_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 117 #define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5 118 119 /* UCM agg val selection (HW) */ 120 #define DQ_UCM_AGG_VAL_SEL_WORD0 0 121 #define DQ_UCM_AGG_VAL_SEL_WORD1 1 122 #define DQ_UCM_AGG_VAL_SEL_WORD2 2 123 #define DQ_UCM_AGG_VAL_SEL_WORD3 3 124 #define DQ_UCM_AGG_VAL_SEL_REG0 4 125 #define DQ_UCM_AGG_VAL_SEL_REG1 5 126 #define DQ_UCM_AGG_VAL_SEL_REG2 6 127 #define DQ_UCM_AGG_VAL_SEL_REG3 7 128 129 /* UCM agg val selection (FW) */ 130 #define DQ_UCM_ETH_PMD_TX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD2 131 #define DQ_UCM_ETH_PMD_RX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD3 132 #define DQ_UCM_ROCE_CQ_CONS_CMD DQ_UCM_AGG_VAL_SEL_REG0 133 #define DQ_UCM_ROCE_CQ_PROD_CMD DQ_UCM_AGG_VAL_SEL_REG2 134 135 /* TCM agg val selection (HW) */ 136 #define DQ_TCM_AGG_VAL_SEL_WORD0 0 137 #define DQ_TCM_AGG_VAL_SEL_WORD1 1 138 #define DQ_TCM_AGG_VAL_SEL_WORD2 2 139 #define DQ_TCM_AGG_VAL_SEL_WORD3 3 140 #define DQ_TCM_AGG_VAL_SEL_REG1 4 141 #define DQ_TCM_AGG_VAL_SEL_REG2 5 142 #define DQ_TCM_AGG_VAL_SEL_REG6 6 143 #define DQ_TCM_AGG_VAL_SEL_REG9 7 144 145 /* TCM agg val selection (FW) */ 146 #define DQ_TCM_L2B_BD_PROD_CMD \ 147 DQ_TCM_AGG_VAL_SEL_WORD1 148 #define DQ_TCM_ROCE_RQ_PROD_CMD \ 149 DQ_TCM_AGG_VAL_SEL_WORD0 150 151 /* XCM agg counter flag selection */ 152 #define DQ_XCM_AGG_FLG_SHIFT_BIT14 0 153 #define DQ_XCM_AGG_FLG_SHIFT_BIT15 1 154 #define DQ_XCM_AGG_FLG_SHIFT_CF12 2 155 #define DQ_XCM_AGG_FLG_SHIFT_CF13 3 156 #define DQ_XCM_AGG_FLG_SHIFT_CF18 4 157 #define DQ_XCM_AGG_FLG_SHIFT_CF19 5 158 #define DQ_XCM_AGG_FLG_SHIFT_CF22 6 159 #define DQ_XCM_AGG_FLG_SHIFT_CF23 7 160 161 /* XCM agg counter flag selection */ 162 #define DQ_XCM_CORE_DQ_CF_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF18) 163 #define DQ_XCM_CORE_TERMINATE_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 164 #define DQ_XCM_CORE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 165 #define DQ_XCM_ETH_DQ_CF_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF18) 166 #define DQ_XCM_ETH_TERMINATE_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 167 #define DQ_XCM_ETH_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 168 #define DQ_XCM_ETH_TPH_EN_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF23) 169 170 /* UCM agg counter flag selection (HW) */ 171 #define DQ_UCM_AGG_FLG_SHIFT_CF0 0 172 #define DQ_UCM_AGG_FLG_SHIFT_CF1 1 173 #define DQ_UCM_AGG_FLG_SHIFT_CF3 2 174 #define DQ_UCM_AGG_FLG_SHIFT_CF4 3 175 #define DQ_UCM_AGG_FLG_SHIFT_CF5 4 176 #define DQ_UCM_AGG_FLG_SHIFT_CF6 5 177 #define DQ_UCM_AGG_FLG_SHIFT_RULE0EN 6 178 #define DQ_UCM_AGG_FLG_SHIFT_RULE1EN 7 179 180 /* UCM agg counter flag selection (FW) */ 181 #define DQ_UCM_ETH_PMD_TX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) 182 #define DQ_UCM_ETH_PMD_RX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) 183 184 #define DQ_REGION_SHIFT (12) 185 186 /* DPM */ 187 #define DQ_DPM_WQE_BUFF_SIZE (320) 188 189 /* Conn type ranges */ 190 #define DQ_CONN_TYPE_RANGE_SHIFT (4) 191 192 /*****************/ 193 /* QM CONSTANTS */ 194 /*****************/ 195 196 /* number of TX queues in the QM */ 197 #define MAX_QM_TX_QUEUES_K2 512 198 #define MAX_QM_TX_QUEUES_BB 448 199 #define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2 200 201 /* number of Other queues in the QM */ 202 #define MAX_QM_OTHER_QUEUES_BB 64 203 #define MAX_QM_OTHER_QUEUES_K2 128 204 #define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2 205 206 /* number of queues in a PF queue group */ 207 #define QM_PF_QUEUE_GROUP_SIZE 8 208 209 /* the size of a single queue element in bytes */ 210 #define QM_PQ_ELEMENT_SIZE 4 211 212 /* base number of Tx PQs in the CM PQ representation. 213 * should be used when storing PQ IDs in CM PQ registers and context 214 */ 215 #define CM_TX_PQ_BASE 0x200 216 217 /* QM registers data */ 218 #define QM_LINE_CRD_REG_WIDTH 16 219 #define QM_LINE_CRD_REG_SIGN_BIT (1 << (QM_LINE_CRD_REG_WIDTH - 1)) 220 #define QM_BYTE_CRD_REG_WIDTH 24 221 #define QM_BYTE_CRD_REG_SIGN_BIT (1 << (QM_BYTE_CRD_REG_WIDTH - 1)) 222 #define QM_WFQ_CRD_REG_WIDTH 32 223 #define QM_WFQ_CRD_REG_SIGN_BIT (1 << (QM_WFQ_CRD_REG_WIDTH - 1)) 224 #define QM_RL_CRD_REG_WIDTH 32 225 #define QM_RL_CRD_REG_SIGN_BIT (1 << (QM_RL_CRD_REG_WIDTH - 1)) 226 227 /*****************/ 228 /* CAU CONSTANTS */ 229 /*****************/ 230 231 #define CAU_FSM_ETH_RX 0 232 #define CAU_FSM_ETH_TX 1 233 234 /* Number of Protocol Indices per Status Block */ 235 #define PIS_PER_SB 12 236 237 #define CAU_HC_STOPPED_STATE 3 238 #define CAU_HC_DISABLE_STATE 4 239 #define CAU_HC_ENABLE_STATE 0 240 241 /*****************/ 242 /* IGU CONSTANTS */ 243 /*****************/ 244 245 #define MAX_SB_PER_PATH_K2 (368) 246 #define MAX_SB_PER_PATH_BB (288) 247 #define MAX_TOT_SB_PER_PATH \ 248 MAX_SB_PER_PATH_K2 249 250 #define MAX_SB_PER_PF_MIMD 129 251 #define MAX_SB_PER_PF_SIMD 64 252 #define MAX_SB_PER_VF 64 253 254 /* Memory addresses on the BAR for the IGU Sub Block */ 255 #define IGU_MEM_BASE 0x0000 256 257 #define IGU_MEM_MSIX_BASE 0x0000 258 #define IGU_MEM_MSIX_UPPER 0x0101 259 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff 260 261 #define IGU_MEM_PBA_MSIX_BASE 0x0200 262 #define IGU_MEM_PBA_MSIX_UPPER 0x0202 263 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff 264 265 #define IGU_CMD_INT_ACK_BASE 0x0400 266 #define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + \ 267 MAX_TOT_SB_PER_PATH - \ 268 1) 269 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff 270 271 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0 272 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05f1 273 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05f2 274 275 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05f3 276 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05f4 277 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05f5 278 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05f6 279 280 #define IGU_CMD_PROD_UPD_BASE 0x0600 281 #define IGU_CMD_PROD_UPD_UPPER (IGU_CMD_PROD_UPD_BASE +\ 282 MAX_TOT_SB_PER_PATH - \ 283 1) 284 #define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff 285 286 /*****************/ 287 /* PXP CONSTANTS */ 288 /*****************/ 289 290 /* PTT and GTT */ 291 #define PXP_NUM_PF_WINDOWS 12 292 #define PXP_PER_PF_ENTRY_SIZE 8 293 #define PXP_NUM_GLOBAL_WINDOWS 243 294 #define PXP_GLOBAL_ENTRY_SIZE 4 295 #define PXP_ADMIN_WINDOW_ALLOWED_LENGTH 4 296 #define PXP_PF_WINDOW_ADMIN_START 0 297 #define PXP_PF_WINDOW_ADMIN_LENGTH 0x1000 298 #define PXP_PF_WINDOW_ADMIN_END (PXP_PF_WINDOW_ADMIN_START + \ 299 PXP_PF_WINDOW_ADMIN_LENGTH - 1) 300 #define PXP_PF_WINDOW_ADMIN_PER_PF_START 0 301 #define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH (PXP_NUM_PF_WINDOWS * \ 302 PXP_PER_PF_ENTRY_SIZE) 303 #define PXP_PF_WINDOW_ADMIN_PER_PF_END (PXP_PF_WINDOW_ADMIN_PER_PF_START + \ 304 PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1) 305 #define PXP_PF_WINDOW_ADMIN_GLOBAL_START 0x200 306 #define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH (PXP_NUM_GLOBAL_WINDOWS * \ 307 PXP_GLOBAL_ENTRY_SIZE) 308 #define PXP_PF_WINDOW_ADMIN_GLOBAL_END \ 309 (PXP_PF_WINDOW_ADMIN_GLOBAL_START + \ 310 PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1) 311 #define PXP_PF_GLOBAL_PRETEND_ADDR 0x1f0 312 #define PXP_PF_ME_OPAQUE_MASK_ADDR 0xf4 313 #define PXP_PF_ME_OPAQUE_ADDR 0x1f8 314 #define PXP_PF_ME_CONCRETE_ADDR 0x1fc 315 316 #define PXP_EXTERNAL_BAR_PF_WINDOW_START 0x1000 317 #define PXP_EXTERNAL_BAR_PF_WINDOW_NUM PXP_NUM_PF_WINDOWS 318 #define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE 0x1000 319 #define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH \ 320 (PXP_EXTERNAL_BAR_PF_WINDOW_NUM * \ 321 PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) 322 #define PXP_EXTERNAL_BAR_PF_WINDOW_END \ 323 (PXP_EXTERNAL_BAR_PF_WINDOW_START + \ 324 PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH - 1) 325 326 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START \ 327 (PXP_EXTERNAL_BAR_PF_WINDOW_END + 1) 328 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM PXP_NUM_GLOBAL_WINDOWS 329 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE 0x1000 330 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH \ 331 (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM * \ 332 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE) 333 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END \ 334 (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + \ 335 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1) 336 337 338 #define PXP_VF_BAR0_START_IGU 0 339 #define PXP_VF_BAR0_IGU_LENGTH 0x3000 340 #define PXP_VF_BAR0_END_IGU (PXP_VF_BAR0_START_IGU + \ 341 PXP_VF_BAR0_IGU_LENGTH - 1) 342 343 #define PXP_VF_BAR0_START_DQ 0x3000 344 #define PXP_VF_BAR0_DQ_LENGTH 0x200 345 #define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0 346 #define PXP_VF_BAR0_ME_OPAQUE_ADDRESS (PXP_VF_BAR0_START_DQ + \ 347 PXP_VF_BAR0_DQ_OPAQUE_OFFSET) 348 #define PXP_VF_BAR0_ME_CONCRETE_ADDRESS (PXP_VF_BAR0_ME_OPAQUE_ADDRESS \ 349 + 4) 350 #define PXP_VF_BAR0_END_DQ (PXP_VF_BAR0_START_DQ + \ 351 PXP_VF_BAR0_DQ_LENGTH - 1) 352 353 #define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200 354 #define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200 355 #define PXP_VF_BAR0_END_TSDM_ZONE_B (PXP_VF_BAR0_START_TSDM_ZONE_B \ 356 + \ 357 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 358 - 1) 359 360 #define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400 361 #define PXP_VF_BAR0_END_MSDM_ZONE_B (PXP_VF_BAR0_START_MSDM_ZONE_B \ 362 + \ 363 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 364 - 1) 365 366 #define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600 367 #define PXP_VF_BAR0_END_USDM_ZONE_B (PXP_VF_BAR0_START_USDM_ZONE_B \ 368 + \ 369 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 370 - 1) 371 372 #define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800 373 #define PXP_VF_BAR0_END_XSDM_ZONE_B (PXP_VF_BAR0_START_XSDM_ZONE_B \ 374 + \ 375 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 376 - 1) 377 378 #define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00 379 #define PXP_VF_BAR0_END_YSDM_ZONE_B (PXP_VF_BAR0_START_YSDM_ZONE_B \ 380 + \ 381 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 382 - 1) 383 384 #define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00 385 #define PXP_VF_BAR0_END_PSDM_ZONE_B (PXP_VF_BAR0_START_PSDM_ZONE_B \ 386 + \ 387 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 388 - 1) 389 390 #define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000 391 #define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000 392 393 #define PXP_VF_BAR0_GRC_WINDOW_LENGTH 32 394 395 #define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12 396 #define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024 397 398 /* ILT Records */ 399 #define PXP_NUM_ILT_RECORDS_BB 7600 400 #define PXP_NUM_ILT_RECORDS_K2 11000 401 #define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2) 402 403 #define SDM_COMP_TYPE_NONE 0 404 #define SDM_COMP_TYPE_WAKE_THREAD 1 405 #define SDM_COMP_TYPE_AGG_INT 2 406 #define SDM_COMP_TYPE_CM 3 407 #define SDM_COMP_TYPE_LOADER 4 408 #define SDM_COMP_TYPE_PXP 5 409 #define SDM_COMP_TYPE_INDICATE_ERROR 6 410 #define SDM_COMP_TYPE_RELEASE_THREAD 7 411 #define SDM_COMP_TYPE_RAM 8 412 413 /******************/ 414 /* PBF CONSTANTS */ 415 /******************/ 416 417 /* Number of PBF command queue lines. Each line is 32B. */ 418 #define PBF_MAX_CMD_LINES 3328 419 420 /* Number of BTB blocks. Each block is 256B. */ 421 #define BTB_MAX_BLOCKS 1440 422 423 /*****************/ 424 /* PRS CONSTANTS */ 425 /*****************/ 426 427 /* Async data KCQ CQE */ 428 struct async_data { 429 __le32 cid; 430 __le16 itid; 431 u8 error_code; 432 u8 fw_debug_param; 433 }; 434 435 struct coalescing_timeset { 436 u8 value; 437 #define COALESCING_TIMESET_TIMESET_MASK 0x7F 438 #define COALESCING_TIMESET_TIMESET_SHIFT 0 439 #define COALESCING_TIMESET_VALID_MASK 0x1 440 #define COALESCING_TIMESET_VALID_SHIFT 7 441 }; 442 443 struct common_prs_pf_msg_info { 444 __le32 value; 445 #define COMMON_PRS_PF_MSG_INFO_NPAR_DEFAULT_PF_MASK 0x1 446 #define COMMON_PRS_PF_MSG_INFO_NPAR_DEFAULT_PF_SHIFT 0 447 #define COMMON_PRS_PF_MSG_INFO_FW_DEBUG_1_MASK 0x1 448 #define COMMON_PRS_PF_MSG_INFO_FW_DEBUG_1_SHIFT 1 449 #define COMMON_PRS_PF_MSG_INFO_FW_DEBUG_2_MASK 0x1 450 #define COMMON_PRS_PF_MSG_INFO_FW_DEBUG_2_SHIFT 2 451 #define COMMON_PRS_PF_MSG_INFO_FW_DEBUG_3_MASK 0x1 452 #define COMMON_PRS_PF_MSG_INFO_FW_DEBUG_3_SHIFT 3 453 #define COMMON_PRS_PF_MSG_INFO_RESERVED_MASK 0xFFFFFFF 454 #define COMMON_PRS_PF_MSG_INFO_RESERVED_SHIFT 4 455 }; 456 457 struct common_queue_zone { 458 __le16 ring_drv_data_consumer; 459 __le16 reserved; 460 }; 461 462 struct eth_rx_prod_data { 463 __le16 bd_prod; 464 __le16 cqe_prod; 465 }; 466 467 struct regpair { 468 __le32 lo; 469 __le32 hi; 470 }; 471 472 struct vf_pf_channel_eqe_data { 473 struct regpair msg_addr; 474 }; 475 476 struct malicious_vf_eqe_data { 477 u8 vf_id; 478 u8 err_id; 479 __le16 reserved[3]; 480 }; 481 482 struct initial_cleanup_eqe_data { 483 u8 vf_id; 484 u8 reserved[7]; 485 }; 486 487 /* Event Data Union */ 488 union event_ring_data { 489 u8 bytes[8]; 490 struct vf_pf_channel_eqe_data vf_pf_channel; 491 struct malicious_vf_eqe_data malicious_vf; 492 struct initial_cleanup_eqe_data vf_init_cleanup; 493 }; 494 495 /* Event Ring Entry */ 496 struct event_ring_entry { 497 u8 protocol_id; 498 u8 opcode; 499 __le16 reserved0; 500 __le16 echo; 501 u8 fw_return_code; 502 u8 flags; 503 #define EVENT_RING_ENTRY_ASYNC_MASK 0x1 504 #define EVENT_RING_ENTRY_ASYNC_SHIFT 0 505 #define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F 506 #define EVENT_RING_ENTRY_RESERVED1_SHIFT 1 507 union event_ring_data data; 508 }; 509 510 /* Multi function mode */ 511 enum mf_mode { 512 ERROR_MODE /* Unsupported mode */, 513 MF_OVLAN, 514 MF_NPAR, 515 MAX_MF_MODE 516 }; 517 518 /* Per-protocol connection types */ 519 enum protocol_type { 520 PROTOCOLID_ISCSI, 521 PROTOCOLID_RESERVED2, 522 PROTOCOLID_ROCE, 523 PROTOCOLID_CORE, 524 PROTOCOLID_ETH, 525 PROTOCOLID_RESERVED4, 526 PROTOCOLID_RESERVED5, 527 PROTOCOLID_PREROCE, 528 PROTOCOLID_COMMON, 529 PROTOCOLID_RESERVED6, 530 MAX_PROTOCOL_TYPE 531 }; 532 533 struct ustorm_eth_queue_zone { 534 struct coalescing_timeset int_coalescing_timeset; 535 u8 reserved[3]; 536 }; 537 538 struct ustorm_queue_zone { 539 struct ustorm_eth_queue_zone eth; 540 struct common_queue_zone common; 541 }; 542 543 /* status block structure */ 544 struct cau_pi_entry { 545 u32 prod; 546 #define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF 547 #define CAU_PI_ENTRY_PROD_VAL_SHIFT 0 548 #define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F 549 #define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16 550 #define CAU_PI_ENTRY_FSM_SEL_MASK 0x1 551 #define CAU_PI_ENTRY_FSM_SEL_SHIFT 23 552 #define CAU_PI_ENTRY_RESERVED_MASK 0xFF 553 #define CAU_PI_ENTRY_RESERVED_SHIFT 24 554 }; 555 556 /* status block structure */ 557 struct cau_sb_entry { 558 u32 data; 559 #define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF 560 #define CAU_SB_ENTRY_SB_PROD_SHIFT 0 561 #define CAU_SB_ENTRY_STATE0_MASK 0xF 562 #define CAU_SB_ENTRY_STATE0_SHIFT 24 563 #define CAU_SB_ENTRY_STATE1_MASK 0xF 564 #define CAU_SB_ENTRY_STATE1_SHIFT 28 565 u32 params; 566 #define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F 567 #define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0 568 #define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F 569 #define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7 570 #define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3 571 #define CAU_SB_ENTRY_TIMER_RES0_SHIFT 14 572 #define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3 573 #define CAU_SB_ENTRY_TIMER_RES1_SHIFT 16 574 #define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF 575 #define CAU_SB_ENTRY_VF_NUMBER_SHIFT 18 576 #define CAU_SB_ENTRY_VF_VALID_MASK 0x1 577 #define CAU_SB_ENTRY_VF_VALID_SHIFT 26 578 #define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF 579 #define CAU_SB_ENTRY_PF_NUMBER_SHIFT 27 580 #define CAU_SB_ENTRY_TPH_MASK 0x1 581 #define CAU_SB_ENTRY_TPH_SHIFT 31 582 }; 583 584 /* core doorbell data */ 585 struct core_db_data { 586 u8 params; 587 #define CORE_DB_DATA_DEST_MASK 0x3 588 #define CORE_DB_DATA_DEST_SHIFT 0 589 #define CORE_DB_DATA_AGG_CMD_MASK 0x3 590 #define CORE_DB_DATA_AGG_CMD_SHIFT 2 591 #define CORE_DB_DATA_BYPASS_EN_MASK 0x1 592 #define CORE_DB_DATA_BYPASS_EN_SHIFT 4 593 #define CORE_DB_DATA_RESERVED_MASK 0x1 594 #define CORE_DB_DATA_RESERVED_SHIFT 5 595 #define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3 596 #define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6 597 u8 agg_flags; 598 __le16 spq_prod; 599 }; 600 601 /* Enum of doorbell aggregative command selection */ 602 enum db_agg_cmd_sel { 603 DB_AGG_CMD_NOP, 604 DB_AGG_CMD_SET, 605 DB_AGG_CMD_ADD, 606 DB_AGG_CMD_MAX, 607 MAX_DB_AGG_CMD_SEL 608 }; 609 610 /* Enum of doorbell destination */ 611 enum db_dest { 612 DB_DEST_XCM, 613 DB_DEST_UCM, 614 DB_DEST_TCM, 615 DB_NUM_DESTINATIONS, 616 MAX_DB_DEST 617 }; 618 619 /* Structure for doorbell address, in legacy mode */ 620 struct db_legacy_addr { 621 __le32 addr; 622 #define DB_LEGACY_ADDR_RESERVED0_MASK 0x3 623 #define DB_LEGACY_ADDR_RESERVED0_SHIFT 0 624 #define DB_LEGACY_ADDR_DEMS_MASK 0x7 625 #define DB_LEGACY_ADDR_DEMS_SHIFT 2 626 #define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF 627 #define DB_LEGACY_ADDR_ICID_SHIFT 5 628 }; 629 630 /* Igu interrupt command */ 631 enum igu_int_cmd { 632 IGU_INT_ENABLE = 0, 633 IGU_INT_DISABLE = 1, 634 IGU_INT_NOP = 2, 635 IGU_INT_NOP2 = 3, 636 MAX_IGU_INT_CMD 637 }; 638 639 /* IGU producer or consumer update command */ 640 struct igu_prod_cons_update { 641 u32 sb_id_and_flags; 642 #define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF 643 #define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0 644 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1 645 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT 24 646 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3 647 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT 25 648 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1 649 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27 650 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1 651 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT 28 652 #define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3 653 #define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT 29 654 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1 655 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT 31 656 u32 reserved1; 657 }; 658 659 /* Igu segments access for default status block only */ 660 enum igu_seg_access { 661 IGU_SEG_ACCESS_REG = 0, 662 IGU_SEG_ACCESS_ATTN = 1, 663 MAX_IGU_SEG_ACCESS 664 }; 665 666 struct parsing_and_err_flags { 667 __le16 flags; 668 #define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3 669 #define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0 670 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3 671 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2 672 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1 673 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4 674 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1 675 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5 676 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1 677 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6 678 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1 679 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7 680 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1 681 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT 8 682 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1 683 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT 9 684 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1 685 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10 686 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1 687 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11 688 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1 689 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12 690 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1 691 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13 692 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1 693 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14 694 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1 695 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15 696 }; 697 698 struct pb_context { 699 __le32 crc[4]; 700 }; 701 702 struct pxp_concrete_fid { 703 __le16 fid; 704 #define PXP_CONCRETE_FID_PFID_MASK 0xF 705 #define PXP_CONCRETE_FID_PFID_SHIFT 0 706 #define PXP_CONCRETE_FID_PORT_MASK 0x3 707 #define PXP_CONCRETE_FID_PORT_SHIFT 4 708 #define PXP_CONCRETE_FID_PATH_MASK 0x1 709 #define PXP_CONCRETE_FID_PATH_SHIFT 6 710 #define PXP_CONCRETE_FID_VFVALID_MASK 0x1 711 #define PXP_CONCRETE_FID_VFVALID_SHIFT 7 712 #define PXP_CONCRETE_FID_VFID_MASK 0xFF 713 #define PXP_CONCRETE_FID_VFID_SHIFT 8 714 }; 715 716 struct pxp_pretend_concrete_fid { 717 __le16 fid; 718 #define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF 719 #define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0 720 #define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7 721 #define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4 722 #define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1 723 #define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT 7 724 #define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF 725 #define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8 726 }; 727 728 union pxp_pretend_fid { 729 struct pxp_pretend_concrete_fid concrete_fid; 730 __le16 opaque_fid; 731 }; 732 733 /* Pxp Pretend Command Register. */ 734 struct pxp_pretend_cmd { 735 union pxp_pretend_fid fid; 736 __le16 control; 737 #define PXP_PRETEND_CMD_PATH_MASK 0x1 738 #define PXP_PRETEND_CMD_PATH_SHIFT 0 739 #define PXP_PRETEND_CMD_USE_PORT_MASK 0x1 740 #define PXP_PRETEND_CMD_USE_PORT_SHIFT 1 741 #define PXP_PRETEND_CMD_PORT_MASK 0x3 742 #define PXP_PRETEND_CMD_PORT_SHIFT 2 743 #define PXP_PRETEND_CMD_RESERVED0_MASK 0xF 744 #define PXP_PRETEND_CMD_RESERVED0_SHIFT 4 745 #define PXP_PRETEND_CMD_RESERVED1_MASK 0xF 746 #define PXP_PRETEND_CMD_RESERVED1_SHIFT 8 747 #define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1 748 #define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT 12 749 #define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1 750 #define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT 13 751 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1 752 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14 753 #define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1 754 #define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15 755 }; 756 757 /* PTT Record in PXP Admin Window. */ 758 struct pxp_ptt_entry { 759 __le32 offset; 760 #define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF 761 #define PXP_PTT_ENTRY_OFFSET_SHIFT 0 762 #define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF 763 #define PXP_PTT_ENTRY_RESERVED0_SHIFT 23 764 struct pxp_pretend_cmd pretend; 765 }; 766 767 /* RSS hash type */ 768 struct rdif_task_context { 769 __le32 initial_ref_tag; 770 __le16 app_tag_value; 771 __le16 app_tag_mask; 772 u8 flags0; 773 #define RDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1 774 #define RDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0 775 #define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1 776 #define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1 777 #define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1 778 #define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2 779 #define RDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1 780 #define RDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3 781 #define RDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3 782 #define RDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4 783 #define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 784 #define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 785 #define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1 786 #define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 7 787 u8 partial_dif_data[7]; 788 __le16 partial_crc_value; 789 __le16 partial_checksum_value; 790 __le32 offset_in_io; 791 __le16 flags1; 792 #define RDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1 793 #define RDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0 794 #define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1 795 #define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1 796 #define RDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1 797 #define RDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2 798 #define RDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1 799 #define RDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3 800 #define RDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1 801 #define RDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4 802 #define RDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1 803 #define RDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5 804 #define RDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7 805 #define RDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6 806 #define RDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3 807 #define RDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9 808 #define RDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1 809 #define RDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11 810 #define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1 811 #define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12 812 #define RDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1 813 #define RDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13 814 #define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1 815 #define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 14 816 #define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1 817 #define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 15 818 __le16 state; 819 #define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_MASK 0xF 820 #define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_SHIFT 0 821 #define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_MASK 0xF 822 #define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_SHIFT 4 823 #define RDIF_TASK_CONTEXT_ERRORINIO_MASK 0x1 824 #define RDIF_TASK_CONTEXT_ERRORINIO_SHIFT 8 825 #define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1 826 #define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9 827 #define RDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF 828 #define RDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 10 829 #define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3 830 #define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14 831 __le32 reserved2; 832 }; 833 834 enum rss_hash_type { 835 RSS_HASH_TYPE_DEFAULT = 0, 836 RSS_HASH_TYPE_IPV4 = 1, 837 RSS_HASH_TYPE_TCP_IPV4 = 2, 838 RSS_HASH_TYPE_IPV6 = 3, 839 RSS_HASH_TYPE_TCP_IPV6 = 4, 840 RSS_HASH_TYPE_UDP_IPV4 = 5, 841 RSS_HASH_TYPE_UDP_IPV6 = 6, 842 MAX_RSS_HASH_TYPE 843 }; 844 845 /* status block structure */ 846 struct status_block { 847 __le16 pi_array[PIS_PER_SB]; 848 __le32 sb_num; 849 #define STATUS_BLOCK_SB_NUM_MASK 0x1FF 850 #define STATUS_BLOCK_SB_NUM_SHIFT 0 851 #define STATUS_BLOCK_ZERO_PAD_MASK 0x7F 852 #define STATUS_BLOCK_ZERO_PAD_SHIFT 9 853 #define STATUS_BLOCK_ZERO_PAD2_MASK 0xFFFF 854 #define STATUS_BLOCK_ZERO_PAD2_SHIFT 16 855 __le32 prod_index; 856 #define STATUS_BLOCK_PROD_INDEX_MASK 0xFFFFFF 857 #define STATUS_BLOCK_PROD_INDEX_SHIFT 0 858 #define STATUS_BLOCK_ZERO_PAD3_MASK 0xFF 859 #define STATUS_BLOCK_ZERO_PAD3_SHIFT 24 860 }; 861 862 struct tdif_task_context { 863 __le32 initial_ref_tag; 864 __le16 app_tag_value; 865 __le16 app_tag_mask; 866 __le16 partial_crc_valueB; 867 __le16 partial_checksum_valueB; 868 __le16 stateB; 869 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_MASK 0xF 870 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_SHIFT 0 871 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_MASK 0xF 872 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_SHIFT 4 873 #define TDIF_TASK_CONTEXT_ERRORINIOB_MASK 0x1 874 #define TDIF_TASK_CONTEXT_ERRORINIOB_SHIFT 8 875 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1 876 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9 877 #define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F 878 #define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10 879 u8 reserved1; 880 u8 flags0; 881 #define TDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1 882 #define TDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0 883 #define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1 884 #define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1 885 #define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1 886 #define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2 887 #define TDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1 888 #define TDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3 889 #define TDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3 890 #define TDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4 891 #define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 892 #define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 893 #define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1 894 #define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7 895 __le32 flags1; 896 #define TDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1 897 #define TDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0 898 #define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1 899 #define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1 900 #define TDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1 901 #define TDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2 902 #define TDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1 903 #define TDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3 904 #define TDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1 905 #define TDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4 906 #define TDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1 907 #define TDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5 908 #define TDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7 909 #define TDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6 910 #define TDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3 911 #define TDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9 912 #define TDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1 913 #define TDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11 914 #define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1 915 #define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12 916 #define TDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1 917 #define TDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13 918 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_MASK 0xF 919 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_SHIFT 14 920 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_MASK 0xF 921 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_SHIFT 18 922 #define TDIF_TASK_CONTEXT_ERRORINIOA_MASK 0x1 923 #define TDIF_TASK_CONTEXT_ERRORINIOA_SHIFT 22 924 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_MASK 0x1 925 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_SHIFT 23 926 #define TDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF 927 #define TDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 24 928 #define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1 929 #define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 28 930 #define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1 931 #define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 29 932 #define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1 933 #define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 30 934 #define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1 935 #define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31 936 __le32 offset_in_iob; 937 __le16 partial_crc_value_a; 938 __le16 partial_checksum_valuea_; 939 __le32 offset_in_ioa; 940 u8 partial_dif_data_a[8]; 941 u8 partial_dif_data_b[8]; 942 }; 943 944 struct timers_context { 945 __le32 logical_client0; 946 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0xFFFFFFF 947 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT 0 948 #define TIMERS_CONTEXT_VALIDLC0_MASK 0x1 949 #define TIMERS_CONTEXT_VALIDLC0_SHIFT 28 950 #define TIMERS_CONTEXT_ACTIVELC0_MASK 0x1 951 #define TIMERS_CONTEXT_ACTIVELC0_SHIFT 29 952 #define TIMERS_CONTEXT_RESERVED0_MASK 0x3 953 #define TIMERS_CONTEXT_RESERVED0_SHIFT 30 954 __le32 logical_client1; 955 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK 0xFFFFFFF 956 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT 0 957 #define TIMERS_CONTEXT_VALIDLC1_MASK 0x1 958 #define TIMERS_CONTEXT_VALIDLC1_SHIFT 28 959 #define TIMERS_CONTEXT_ACTIVELC1_MASK 0x1 960 #define TIMERS_CONTEXT_ACTIVELC1_SHIFT 29 961 #define TIMERS_CONTEXT_RESERVED1_MASK 0x3 962 #define TIMERS_CONTEXT_RESERVED1_SHIFT 30 963 __le32 logical_client2; 964 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK 0xFFFFFFF 965 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT 0 966 #define TIMERS_CONTEXT_VALIDLC2_MASK 0x1 967 #define TIMERS_CONTEXT_VALIDLC2_SHIFT 28 968 #define TIMERS_CONTEXT_ACTIVELC2_MASK 0x1 969 #define TIMERS_CONTEXT_ACTIVELC2_SHIFT 29 970 #define TIMERS_CONTEXT_RESERVED2_MASK 0x3 971 #define TIMERS_CONTEXT_RESERVED2_SHIFT 30 972 __le32 host_expiration_fields; 973 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_MASK 0xFFFFFFF 974 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_SHIFT 0 975 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_MASK 0x1 976 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_SHIFT 28 977 #define TIMERS_CONTEXT_RESERVED3_MASK 0x7 978 #define TIMERS_CONTEXT_RESERVED3_SHIFT 29 979 }; 980 #endif /* __COMMON_HSI__ */ 981