1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2016 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _COMMON_HSI_H 34 #define _COMMON_HSI_H 35 #include <linux/types.h> 36 #include <asm/byteorder.h> 37 #include <linux/bitops.h> 38 #include <linux/slab.h> 39 40 /* dma_addr_t manip */ 41 #define DMA_LO_LE(x) cpu_to_le32(lower_32_bits(x)) 42 #define DMA_HI_LE(x) cpu_to_le32(upper_32_bits(x)) 43 #define DMA_REGPAIR_LE(x, val) do { \ 44 (x).hi = DMA_HI_LE((val)); \ 45 (x).lo = DMA_LO_LE((val)); \ 46 } while (0) 47 48 #define HILO_GEN(hi, lo, type) ((((type)(hi)) << 32) + (lo)) 49 #define HILO_64(hi, lo) HILO_GEN((le32_to_cpu(hi)), (le32_to_cpu(lo)), u64) 50 #define HILO_64_REGPAIR(regpair) (HILO_64(regpair.hi, regpair.lo)) 51 #define HILO_DMA_REGPAIR(regpair) ((dma_addr_t)HILO_64_REGPAIR(regpair)) 52 53 #ifndef __COMMON_HSI__ 54 #define __COMMON_HSI__ 55 56 57 #define X_FINAL_CLEANUP_AGG_INT 1 58 59 #define EVENT_RING_PAGE_SIZE_BYTES 4096 60 61 #define NUM_OF_GLOBAL_QUEUES 128 62 #define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64 63 64 #define ISCSI_CDU_TASK_SEG_TYPE 0 65 #define FCOE_CDU_TASK_SEG_TYPE 0 66 #define RDMA_CDU_TASK_SEG_TYPE 1 67 68 #define FW_ASSERT_GENERAL_ATTN_IDX 32 69 70 #define MAX_PINNED_CCFC 32 71 72 /* Queue Zone sizes in bytes */ 73 #define TSTORM_QZONE_SIZE 8 74 #define MSTORM_QZONE_SIZE 16 75 #define USTORM_QZONE_SIZE 8 76 #define XSTORM_QZONE_SIZE 8 77 #define YSTORM_QZONE_SIZE 0 78 #define PSTORM_QZONE_SIZE 0 79 80 #define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7 81 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT 16 82 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE 48 83 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD 112 84 85 /********************************/ 86 /* CORE (LIGHT L2) FW CONSTANTS */ 87 /********************************/ 88 89 #define CORE_LL2_MAX_RAMROD_PER_CON 8 90 #define CORE_LL2_TX_BD_PAGE_SIZE_BYTES 4096 91 #define CORE_LL2_RX_BD_PAGE_SIZE_BYTES 4096 92 #define CORE_LL2_RX_CQE_PAGE_SIZE_BYTES 4096 93 #define CORE_LL2_RX_NUM_NEXT_PAGE_BDS 1 94 95 #define CORE_LL2_TX_MAX_BDS_PER_PACKET 12 96 97 #define CORE_SPQE_PAGE_SIZE_BYTES 4096 98 99 #define MAX_NUM_LL2_RX_QUEUES 32 100 #define MAX_NUM_LL2_TX_STATS_COUNTERS 32 101 102 #define FW_MAJOR_VERSION 8 103 #define FW_MINOR_VERSION 15 104 #define FW_REVISION_VERSION 3 105 #define FW_ENGINEERING_VERSION 0 106 107 /***********************/ 108 /* COMMON HW CONSTANTS */ 109 /***********************/ 110 111 /* PCI functions */ 112 #define MAX_NUM_PORTS_K2 (4) 113 #define MAX_NUM_PORTS_BB (2) 114 #define MAX_NUM_PORTS (MAX_NUM_PORTS_K2) 115 116 #define MAX_NUM_PFS_K2 (16) 117 #define MAX_NUM_PFS_BB (8) 118 #define MAX_NUM_PFS (MAX_NUM_PFS_K2) 119 #define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */ 120 121 #define MAX_NUM_VFS_K2 (192) 122 #define MAX_NUM_VFS_BB (120) 123 #define MAX_NUM_VFS (MAX_NUM_VFS_K2) 124 125 #define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB) 126 #define MAX_NUM_FUNCTIONS (MAX_NUM_PFS + MAX_NUM_VFS) 127 128 #define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB) 129 #define MAX_FUNCTION_NUMBER (MAX_NUM_PFS + MAX_NUM_VFS) 130 131 #define MAX_NUM_VPORTS_K2 (208) 132 #define MAX_NUM_VPORTS_BB (160) 133 #define MAX_NUM_VPORTS (MAX_NUM_VPORTS_K2) 134 135 #define MAX_NUM_L2_QUEUES_K2 (320) 136 #define MAX_NUM_L2_QUEUES_BB (256) 137 #define MAX_NUM_L2_QUEUES (MAX_NUM_L2_QUEUES_K2) 138 139 /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */ 140 #define NUM_PHYS_TCS_4PORT_K2 (4) 141 #define NUM_OF_PHYS_TCS (8) 142 143 #define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1) 144 #define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1) 145 146 #define LB_TC (NUM_OF_PHYS_TCS) 147 148 /* Num of possible traffic priority values */ 149 #define NUM_OF_PRIO (8) 150 151 #define MAX_NUM_VOQS_K2 (NUM_TCS_4PORT_K2 * MAX_NUM_PORTS_K2) 152 #define MAX_NUM_VOQS_BB (NUM_OF_TCS * MAX_NUM_PORTS_BB) 153 #define MAX_NUM_VOQS (MAX_NUM_VOQS_K2) 154 #define MAX_PHYS_VOQS (NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB) 155 156 /* CIDs */ 157 #define NUM_OF_CONNECTION_TYPES (8) 158 #define NUM_OF_LCIDS (320) 159 #define NUM_OF_LTIDS (320) 160 161 /* Clock values */ 162 #define MASTER_CLK_FREQ_E4 (375e6) 163 #define STORM_CLK_FREQ_E4 (1000e6) 164 #define CLK25M_CLK_FREQ_E4 (25e6) 165 166 /* Global PXP windows (GTT) */ 167 #define NUM_OF_GTT 19 168 #define GTT_DWORD_SIZE_BITS 10 169 #define GTT_BYTE_SIZE_BITS (GTT_DWORD_SIZE_BITS + 2) 170 #define GTT_DWORD_SIZE BIT(GTT_DWORD_SIZE_BITS) 171 172 /* Tools Version */ 173 #define TOOLS_VERSION 10 174 175 /*****************/ 176 /* CDU CONSTANTS */ 177 /*****************/ 178 179 #define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17) 180 #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff) 181 182 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12) 183 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff) 184 /*****************/ 185 /* DQ CONSTANTS */ 186 /*****************/ 187 188 /* DEMS */ 189 #define DQ_DEMS_LEGACY 0 190 #define DQ_DEMS_TOE_MORE_TO_SEND 3 191 #define DQ_DEMS_TOE_LOCAL_ADV_WND 4 192 #define DQ_DEMS_ROCE_CQ_CONS 7 193 194 /* XCM agg val selection */ 195 #define DQ_XCM_AGG_VAL_SEL_WORD2 0 196 #define DQ_XCM_AGG_VAL_SEL_WORD3 1 197 #define DQ_XCM_AGG_VAL_SEL_WORD4 2 198 #define DQ_XCM_AGG_VAL_SEL_WORD5 3 199 #define DQ_XCM_AGG_VAL_SEL_REG3 4 200 #define DQ_XCM_AGG_VAL_SEL_REG4 5 201 #define DQ_XCM_AGG_VAL_SEL_REG5 6 202 #define DQ_XCM_AGG_VAL_SEL_REG6 7 203 204 /* XCM agg val selection */ 205 #define DQ_XCM_CORE_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 206 #define DQ_XCM_CORE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 207 #define DQ_XCM_CORE_SPQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 208 #define DQ_XCM_ETH_EDPM_NUM_BDS_CMD DQ_XCM_AGG_VAL_SEL_WORD2 209 #define DQ_XCM_ETH_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 210 #define DQ_XCM_ETH_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 211 #define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5 212 #define DQ_XCM_FCOE_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 213 #define DQ_XCM_FCOE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 214 #define DQ_XCM_FCOE_X_FERQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD5 215 #define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 216 #define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 217 #define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 218 #define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6 219 #define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 220 #define DQ_XCM_TOE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 221 #define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 222 #define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG4 223 224 /* UCM agg val selection (HW) */ 225 #define DQ_UCM_AGG_VAL_SEL_WORD0 0 226 #define DQ_UCM_AGG_VAL_SEL_WORD1 1 227 #define DQ_UCM_AGG_VAL_SEL_WORD2 2 228 #define DQ_UCM_AGG_VAL_SEL_WORD3 3 229 #define DQ_UCM_AGG_VAL_SEL_REG0 4 230 #define DQ_UCM_AGG_VAL_SEL_REG1 5 231 #define DQ_UCM_AGG_VAL_SEL_REG2 6 232 #define DQ_UCM_AGG_VAL_SEL_REG3 7 233 234 /* UCM agg val selection (FW) */ 235 #define DQ_UCM_ETH_PMD_TX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD2 236 #define DQ_UCM_ETH_PMD_RX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD3 237 #define DQ_UCM_ROCE_CQ_CONS_CMD DQ_UCM_AGG_VAL_SEL_REG0 238 #define DQ_UCM_ROCE_CQ_PROD_CMD DQ_UCM_AGG_VAL_SEL_REG2 239 240 /* TCM agg val selection (HW) */ 241 #define DQ_TCM_AGG_VAL_SEL_WORD0 0 242 #define DQ_TCM_AGG_VAL_SEL_WORD1 1 243 #define DQ_TCM_AGG_VAL_SEL_WORD2 2 244 #define DQ_TCM_AGG_VAL_SEL_WORD3 3 245 #define DQ_TCM_AGG_VAL_SEL_REG1 4 246 #define DQ_TCM_AGG_VAL_SEL_REG2 5 247 #define DQ_TCM_AGG_VAL_SEL_REG6 6 248 #define DQ_TCM_AGG_VAL_SEL_REG9 7 249 250 /* TCM agg val selection (FW) */ 251 #define DQ_TCM_L2B_BD_PROD_CMD \ 252 DQ_TCM_AGG_VAL_SEL_WORD1 253 #define DQ_TCM_ROCE_RQ_PROD_CMD \ 254 DQ_TCM_AGG_VAL_SEL_WORD0 255 256 /* XCM agg counter flag selection */ 257 #define DQ_XCM_AGG_FLG_SHIFT_BIT14 0 258 #define DQ_XCM_AGG_FLG_SHIFT_BIT15 1 259 #define DQ_XCM_AGG_FLG_SHIFT_CF12 2 260 #define DQ_XCM_AGG_FLG_SHIFT_CF13 3 261 #define DQ_XCM_AGG_FLG_SHIFT_CF18 4 262 #define DQ_XCM_AGG_FLG_SHIFT_CF19 5 263 #define DQ_XCM_AGG_FLG_SHIFT_CF22 6 264 #define DQ_XCM_AGG_FLG_SHIFT_CF23 7 265 266 /* XCM agg counter flag selection */ 267 #define DQ_XCM_CORE_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18) 268 #define DQ_XCM_CORE_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19) 269 #define DQ_XCM_CORE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) 270 #define DQ_XCM_ETH_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18) 271 #define DQ_XCM_ETH_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19) 272 #define DQ_XCM_ETH_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) 273 #define DQ_XCM_ETH_TPH_EN_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23) 274 #define DQ_XCM_FCOE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) 275 #define DQ_XCM_ISCSI_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19) 276 #define DQ_XCM_ISCSI_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) 277 #define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23) 278 #define DQ_XCM_TOE_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19) 279 #define DQ_XCM_TOE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) 280 281 /* UCM agg counter flag selection (HW) */ 282 #define DQ_UCM_AGG_FLG_SHIFT_CF0 0 283 #define DQ_UCM_AGG_FLG_SHIFT_CF1 1 284 #define DQ_UCM_AGG_FLG_SHIFT_CF3 2 285 #define DQ_UCM_AGG_FLG_SHIFT_CF4 3 286 #define DQ_UCM_AGG_FLG_SHIFT_CF5 4 287 #define DQ_UCM_AGG_FLG_SHIFT_CF6 5 288 #define DQ_UCM_AGG_FLG_SHIFT_RULE0EN 6 289 #define DQ_UCM_AGG_FLG_SHIFT_RULE1EN 7 290 291 /* UCM agg counter flag selection (FW) */ 292 #define DQ_UCM_ETH_PMD_TX_ARM_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF4) 293 #define DQ_UCM_ETH_PMD_RX_ARM_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF5) 294 #define DQ_UCM_ROCE_CQ_ARM_SE_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF4) 295 #define DQ_UCM_ROCE_CQ_ARM_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF5) 296 #define DQ_UCM_TOE_TIMER_STOP_ALL_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF3) 297 #define DQ_UCM_TOE_SLOW_PATH_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF4) 298 #define DQ_UCM_TOE_DQ_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF5) 299 300 /* TCM agg counter flag selection (HW) */ 301 #define DQ_TCM_AGG_FLG_SHIFT_CF0 0 302 #define DQ_TCM_AGG_FLG_SHIFT_CF1 1 303 #define DQ_TCM_AGG_FLG_SHIFT_CF2 2 304 #define DQ_TCM_AGG_FLG_SHIFT_CF3 3 305 #define DQ_TCM_AGG_FLG_SHIFT_CF4 4 306 #define DQ_TCM_AGG_FLG_SHIFT_CF5 5 307 #define DQ_TCM_AGG_FLG_SHIFT_CF6 6 308 #define DQ_TCM_AGG_FLG_SHIFT_CF7 7 309 /* TCM agg counter flag selection (FW) */ 310 #define DQ_TCM_FCOE_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1) 311 #define DQ_TCM_FCOE_DUMMY_TIMER_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF2) 312 #define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3) 313 #define DQ_TCM_ISCSI_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1) 314 #define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3) 315 #define DQ_TCM_TOE_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1) 316 #define DQ_TCM_TOE_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3) 317 #define DQ_TCM_IWARP_POST_RQ_CF_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1) 318 319 /* PWM address mapping */ 320 #define DQ_PWM_OFFSET_DPM_BASE 0x0 321 #define DQ_PWM_OFFSET_DPM_END 0x27 322 #define DQ_PWM_OFFSET_XCM16_BASE 0x40 323 #define DQ_PWM_OFFSET_XCM32_BASE 0x44 324 #define DQ_PWM_OFFSET_UCM16_BASE 0x48 325 #define DQ_PWM_OFFSET_UCM32_BASE 0x4C 326 #define DQ_PWM_OFFSET_UCM16_4 0x50 327 #define DQ_PWM_OFFSET_TCM16_BASE 0x58 328 #define DQ_PWM_OFFSET_TCM32_BASE 0x5C 329 #define DQ_PWM_OFFSET_XCM_FLAGS 0x68 330 #define DQ_PWM_OFFSET_UCM_FLAGS 0x69 331 #define DQ_PWM_OFFSET_TCM_FLAGS 0x6B 332 333 #define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD (DQ_PWM_OFFSET_XCM16_BASE + 2) 334 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT (DQ_PWM_OFFSET_UCM32_BASE) 335 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_16BIT (DQ_PWM_OFFSET_UCM16_4) 336 #define DQ_PWM_OFFSET_UCM_RDMA_INT_TIMEOUT (DQ_PWM_OFFSET_UCM16_BASE + 2) 337 #define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS (DQ_PWM_OFFSET_UCM_FLAGS) 338 #define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 1) 339 #define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 3) 340 #define DQ_REGION_SHIFT (12) 341 342 /* DPM */ 343 #define DQ_DPM_WQE_BUFF_SIZE (320) 344 345 /* Conn type ranges */ 346 #define DQ_CONN_TYPE_RANGE_SHIFT (4) 347 348 /*****************/ 349 /* QM CONSTANTS */ 350 /*****************/ 351 352 /* number of TX queues in the QM */ 353 #define MAX_QM_TX_QUEUES_K2 512 354 #define MAX_QM_TX_QUEUES_BB 448 355 #define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2 356 357 /* number of Other queues in the QM */ 358 #define MAX_QM_OTHER_QUEUES_BB 64 359 #define MAX_QM_OTHER_QUEUES_K2 128 360 #define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2 361 362 /* number of queues in a PF queue group */ 363 #define QM_PF_QUEUE_GROUP_SIZE 8 364 365 /* the size of a single queue element in bytes */ 366 #define QM_PQ_ELEMENT_SIZE 4 367 368 /* base number of Tx PQs in the CM PQ representation. 369 * should be used when storing PQ IDs in CM PQ registers and context 370 */ 371 #define CM_TX_PQ_BASE 0x200 372 373 /* number of global Vport/QCN rate limiters */ 374 #define MAX_QM_GLOBAL_RLS 256 375 /* QM registers data */ 376 #define QM_LINE_CRD_REG_WIDTH 16 377 #define QM_LINE_CRD_REG_SIGN_BIT BIT((QM_LINE_CRD_REG_WIDTH - 1)) 378 #define QM_BYTE_CRD_REG_WIDTH 24 379 #define QM_BYTE_CRD_REG_SIGN_BIT BIT((QM_BYTE_CRD_REG_WIDTH - 1)) 380 #define QM_WFQ_CRD_REG_WIDTH 32 381 #define QM_WFQ_CRD_REG_SIGN_BIT BIT((QM_WFQ_CRD_REG_WIDTH - 1)) 382 #define QM_RL_CRD_REG_WIDTH 32 383 #define QM_RL_CRD_REG_SIGN_BIT BIT((QM_RL_CRD_REG_WIDTH - 1)) 384 385 /*****************/ 386 /* CAU CONSTANTS */ 387 /*****************/ 388 389 #define CAU_FSM_ETH_RX 0 390 #define CAU_FSM_ETH_TX 1 391 392 /* Number of Protocol Indices per Status Block */ 393 #define PIS_PER_SB 12 394 395 #define CAU_HC_STOPPED_STATE 3 396 #define CAU_HC_DISABLE_STATE 4 397 #define CAU_HC_ENABLE_STATE 0 398 399 /*****************/ 400 /* IGU CONSTANTS */ 401 /*****************/ 402 403 #define MAX_SB_PER_PATH_K2 (368) 404 #define MAX_SB_PER_PATH_BB (288) 405 #define MAX_TOT_SB_PER_PATH \ 406 MAX_SB_PER_PATH_K2 407 408 #define MAX_SB_PER_PF_MIMD 129 409 #define MAX_SB_PER_PF_SIMD 64 410 #define MAX_SB_PER_VF 64 411 412 /* Memory addresses on the BAR for the IGU Sub Block */ 413 #define IGU_MEM_BASE 0x0000 414 415 #define IGU_MEM_MSIX_BASE 0x0000 416 #define IGU_MEM_MSIX_UPPER 0x0101 417 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff 418 419 #define IGU_MEM_PBA_MSIX_BASE 0x0200 420 #define IGU_MEM_PBA_MSIX_UPPER 0x0202 421 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff 422 423 #define IGU_CMD_INT_ACK_BASE 0x0400 424 #define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + \ 425 MAX_TOT_SB_PER_PATH - \ 426 1) 427 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff 428 429 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0 430 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05f1 431 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05f2 432 433 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05f3 434 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05f4 435 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05f5 436 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05f6 437 438 #define IGU_CMD_PROD_UPD_BASE 0x0600 439 #define IGU_CMD_PROD_UPD_UPPER (IGU_CMD_PROD_UPD_BASE +\ 440 MAX_TOT_SB_PER_PATH - \ 441 1) 442 #define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff 443 444 /*****************/ 445 /* PXP CONSTANTS */ 446 /*****************/ 447 448 /* Bars for Blocks */ 449 #define PXP_BAR_GRC 0 450 #define PXP_BAR_TSDM 0 451 #define PXP_BAR_USDM 0 452 #define PXP_BAR_XSDM 0 453 #define PXP_BAR_MSDM 0 454 #define PXP_BAR_YSDM 0 455 #define PXP_BAR_PSDM 0 456 #define PXP_BAR_IGU 0 457 #define PXP_BAR_DQ 1 458 459 /* PTT and GTT */ 460 #define PXP_NUM_PF_WINDOWS 12 461 #define PXP_PER_PF_ENTRY_SIZE 8 462 #define PXP_NUM_GLOBAL_WINDOWS 243 463 #define PXP_GLOBAL_ENTRY_SIZE 4 464 #define PXP_ADMIN_WINDOW_ALLOWED_LENGTH 4 465 #define PXP_PF_WINDOW_ADMIN_START 0 466 #define PXP_PF_WINDOW_ADMIN_LENGTH 0x1000 467 #define PXP_PF_WINDOW_ADMIN_END (PXP_PF_WINDOW_ADMIN_START + \ 468 PXP_PF_WINDOW_ADMIN_LENGTH - 1) 469 #define PXP_PF_WINDOW_ADMIN_PER_PF_START 0 470 #define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH (PXP_NUM_PF_WINDOWS * \ 471 PXP_PER_PF_ENTRY_SIZE) 472 #define PXP_PF_WINDOW_ADMIN_PER_PF_END (PXP_PF_WINDOW_ADMIN_PER_PF_START + \ 473 PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1) 474 #define PXP_PF_WINDOW_ADMIN_GLOBAL_START 0x200 475 #define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH (PXP_NUM_GLOBAL_WINDOWS * \ 476 PXP_GLOBAL_ENTRY_SIZE) 477 #define PXP_PF_WINDOW_ADMIN_GLOBAL_END \ 478 (PXP_PF_WINDOW_ADMIN_GLOBAL_START + \ 479 PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1) 480 #define PXP_PF_GLOBAL_PRETEND_ADDR 0x1f0 481 #define PXP_PF_ME_OPAQUE_MASK_ADDR 0xf4 482 #define PXP_PF_ME_OPAQUE_ADDR 0x1f8 483 #define PXP_PF_ME_CONCRETE_ADDR 0x1fc 484 485 #define PXP_EXTERNAL_BAR_PF_WINDOW_START 0x1000 486 #define PXP_EXTERNAL_BAR_PF_WINDOW_NUM PXP_NUM_PF_WINDOWS 487 #define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE 0x1000 488 #define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH \ 489 (PXP_EXTERNAL_BAR_PF_WINDOW_NUM * \ 490 PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) 491 #define PXP_EXTERNAL_BAR_PF_WINDOW_END \ 492 (PXP_EXTERNAL_BAR_PF_WINDOW_START + \ 493 PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH - 1) 494 495 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START \ 496 (PXP_EXTERNAL_BAR_PF_WINDOW_END + 1) 497 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM PXP_NUM_GLOBAL_WINDOWS 498 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE 0x1000 499 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH \ 500 (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM * \ 501 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE) 502 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END \ 503 (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + \ 504 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1) 505 506 /* PF BAR */ 507 #define PXP_BAR0_START_GRC 0x0000 508 #define PXP_BAR0_GRC_LENGTH 0x1C00000 509 #define PXP_BAR0_END_GRC (PXP_BAR0_START_GRC + \ 510 PXP_BAR0_GRC_LENGTH - 1) 511 512 #define PXP_BAR0_START_IGU 0x1C00000 513 #define PXP_BAR0_IGU_LENGTH 0x10000 514 #define PXP_BAR0_END_IGU (PXP_BAR0_START_IGU + \ 515 PXP_BAR0_IGU_LENGTH - 1) 516 517 #define PXP_BAR0_START_TSDM 0x1C80000 518 #define PXP_BAR0_SDM_LENGTH 0x40000 519 #define PXP_BAR0_SDM_RESERVED_LENGTH 0x40000 520 #define PXP_BAR0_END_TSDM (PXP_BAR0_START_TSDM + \ 521 PXP_BAR0_SDM_LENGTH - 1) 522 523 #define PXP_BAR0_START_MSDM 0x1D00000 524 #define PXP_BAR0_END_MSDM (PXP_BAR0_START_MSDM + \ 525 PXP_BAR0_SDM_LENGTH - 1) 526 527 #define PXP_BAR0_START_USDM 0x1D80000 528 #define PXP_BAR0_END_USDM (PXP_BAR0_START_USDM + \ 529 PXP_BAR0_SDM_LENGTH - 1) 530 531 #define PXP_BAR0_START_XSDM 0x1E00000 532 #define PXP_BAR0_END_XSDM (PXP_BAR0_START_XSDM + \ 533 PXP_BAR0_SDM_LENGTH - 1) 534 535 #define PXP_BAR0_START_YSDM 0x1E80000 536 #define PXP_BAR0_END_YSDM (PXP_BAR0_START_YSDM + \ 537 PXP_BAR0_SDM_LENGTH - 1) 538 539 #define PXP_BAR0_START_PSDM 0x1F00000 540 #define PXP_BAR0_END_PSDM (PXP_BAR0_START_PSDM + \ 541 PXP_BAR0_SDM_LENGTH - 1) 542 543 #define PXP_BAR0_FIRST_INVALID_ADDRESS (PXP_BAR0_END_PSDM + 1) 544 545 /* VF BAR */ 546 #define PXP_VF_BAR0 0 547 548 #define PXP_VF_BAR0_START_GRC 0x3E00 549 #define PXP_VF_BAR0_GRC_LENGTH 0x200 550 #define PXP_VF_BAR0_END_GRC (PXP_VF_BAR0_START_GRC + \ 551 PXP_VF_BAR0_GRC_LENGTH - 1) 552 553 #define PXP_VF_BAR0_START_IGU 0 554 #define PXP_VF_BAR0_IGU_LENGTH 0x3000 555 #define PXP_VF_BAR0_END_IGU (PXP_VF_BAR0_START_IGU + \ 556 PXP_VF_BAR0_IGU_LENGTH - 1) 557 558 #define PXP_VF_BAR0_START_DQ 0x3000 559 #define PXP_VF_BAR0_DQ_LENGTH 0x200 560 #define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0 561 #define PXP_VF_BAR0_ME_OPAQUE_ADDRESS (PXP_VF_BAR0_START_DQ + \ 562 PXP_VF_BAR0_DQ_OPAQUE_OFFSET) 563 #define PXP_VF_BAR0_ME_CONCRETE_ADDRESS (PXP_VF_BAR0_ME_OPAQUE_ADDRESS \ 564 + 4) 565 #define PXP_VF_BAR0_END_DQ (PXP_VF_BAR0_START_DQ + \ 566 PXP_VF_BAR0_DQ_LENGTH - 1) 567 568 #define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200 569 #define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200 570 #define PXP_VF_BAR0_END_TSDM_ZONE_B (PXP_VF_BAR0_START_TSDM_ZONE_B \ 571 + \ 572 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 573 - 1) 574 575 #define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400 576 #define PXP_VF_BAR0_END_MSDM_ZONE_B (PXP_VF_BAR0_START_MSDM_ZONE_B \ 577 + \ 578 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 579 - 1) 580 581 #define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600 582 #define PXP_VF_BAR0_END_USDM_ZONE_B (PXP_VF_BAR0_START_USDM_ZONE_B \ 583 + \ 584 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 585 - 1) 586 587 #define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800 588 #define PXP_VF_BAR0_END_XSDM_ZONE_B (PXP_VF_BAR0_START_XSDM_ZONE_B \ 589 + \ 590 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 591 - 1) 592 593 #define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00 594 #define PXP_VF_BAR0_END_YSDM_ZONE_B (PXP_VF_BAR0_START_YSDM_ZONE_B \ 595 + \ 596 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 597 - 1) 598 599 #define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00 600 #define PXP_VF_BAR0_END_PSDM_ZONE_B (PXP_VF_BAR0_START_PSDM_ZONE_B \ 601 + \ 602 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 603 - 1) 604 605 #define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000 606 #define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000 607 608 #define PXP_VF_BAR0_GRC_WINDOW_LENGTH 32 609 610 #define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12 611 #define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024 612 613 /* ILT Records */ 614 #define PXP_NUM_ILT_RECORDS_BB 7600 615 #define PXP_NUM_ILT_RECORDS_K2 11000 616 #define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2) 617 #define PXP_QUEUES_ZONE_MAX_NUM 320 618 /*****************/ 619 /* PRM CONSTANTS */ 620 /*****************/ 621 #define PRM_DMA_PAD_BYTES_NUM 2 622 /******************/ 623 /* SDMs CONSTANTS */ 624 /******************/ 625 #define SDM_OP_GEN_TRIG_NONE 0 626 #define SDM_OP_GEN_TRIG_WAKE_THREAD 1 627 #define SDM_OP_GEN_TRIG_AGG_INT 2 628 #define SDM_OP_GEN_TRIG_LOADER 4 629 #define SDM_OP_GEN_TRIG_INDICATE_ERROR 6 630 #define SDM_OP_GEN_TRIG_RELEASE_THREAD 7 631 632 #define SDM_COMP_TYPE_NONE 0 633 #define SDM_COMP_TYPE_WAKE_THREAD 1 634 #define SDM_COMP_TYPE_AGG_INT 2 635 #define SDM_COMP_TYPE_CM 3 636 #define SDM_COMP_TYPE_LOADER 4 637 #define SDM_COMP_TYPE_PXP 5 638 #define SDM_COMP_TYPE_INDICATE_ERROR 6 639 #define SDM_COMP_TYPE_RELEASE_THREAD 7 640 #define SDM_COMP_TYPE_RAM 8 641 642 /******************/ 643 /* PBF CONSTANTS */ 644 /******************/ 645 646 /* Number of PBF command queue lines. Each line is 32B. */ 647 #define PBF_MAX_CMD_LINES 3328 648 649 /* Number of BTB blocks. Each block is 256B. */ 650 #define BTB_MAX_BLOCKS 1440 651 652 /*****************/ 653 /* PRS CONSTANTS */ 654 /*****************/ 655 656 #define PRS_GFT_CAM_LINES_NO_MATCH 31 657 658 /* Async data KCQ CQE */ 659 struct async_data { 660 __le32 cid; 661 __le16 itid; 662 u8 error_code; 663 u8 fw_debug_param; 664 }; 665 666 struct coalescing_timeset { 667 u8 value; 668 #define COALESCING_TIMESET_TIMESET_MASK 0x7F 669 #define COALESCING_TIMESET_TIMESET_SHIFT 0 670 #define COALESCING_TIMESET_VALID_MASK 0x1 671 #define COALESCING_TIMESET_VALID_SHIFT 7 672 }; 673 674 struct common_queue_zone { 675 __le16 ring_drv_data_consumer; 676 __le16 reserved; 677 }; 678 679 struct eth_rx_prod_data { 680 __le16 bd_prod; 681 __le16 cqe_prod; 682 }; 683 684 struct regpair { 685 __le32 lo; 686 __le32 hi; 687 }; 688 689 struct vf_pf_channel_eqe_data { 690 struct regpair msg_addr; 691 }; 692 693 struct iscsi_eqe_data { 694 __le32 cid; 695 __le16 conn_id; 696 u8 error_code; 697 u8 error_pdu_opcode_reserved; 698 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK 0x3F 699 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_SHIFT 0 700 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_MASK 0x1 701 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_SHIFT 6 702 #define ISCSI_EQE_DATA_RESERVED0_MASK 0x1 703 #define ISCSI_EQE_DATA_RESERVED0_SHIFT 7 704 }; 705 706 struct rdma_eqe_destroy_qp { 707 __le32 cid; 708 u8 reserved[4]; 709 }; 710 711 union rdma_eqe_data { 712 struct regpair async_handle; 713 struct rdma_eqe_destroy_qp rdma_destroy_qp_data; 714 }; 715 716 struct malicious_vf_eqe_data { 717 u8 vf_id; 718 u8 err_id; 719 __le16 reserved[3]; 720 }; 721 722 struct initial_cleanup_eqe_data { 723 u8 vf_id; 724 u8 reserved[7]; 725 }; 726 727 /* Event Data Union */ 728 union event_ring_data { 729 u8 bytes[8]; 730 struct vf_pf_channel_eqe_data vf_pf_channel; 731 struct iscsi_eqe_data iscsi_info; 732 union rdma_eqe_data rdma_data; 733 struct malicious_vf_eqe_data malicious_vf; 734 struct initial_cleanup_eqe_data vf_init_cleanup; 735 }; 736 737 /* Event Ring Entry */ 738 struct event_ring_entry { 739 u8 protocol_id; 740 u8 opcode; 741 __le16 reserved0; 742 __le16 echo; 743 u8 fw_return_code; 744 u8 flags; 745 #define EVENT_RING_ENTRY_ASYNC_MASK 0x1 746 #define EVENT_RING_ENTRY_ASYNC_SHIFT 0 747 #define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F 748 #define EVENT_RING_ENTRY_RESERVED1_SHIFT 1 749 union event_ring_data data; 750 }; 751 752 /* Multi function mode */ 753 enum mf_mode { 754 ERROR_MODE /* Unsupported mode */, 755 MF_OVLAN, 756 MF_NPAR, 757 MAX_MF_MODE 758 }; 759 760 /* Per-protocol connection types */ 761 enum protocol_type { 762 PROTOCOLID_ISCSI, 763 PROTOCOLID_FCOE, 764 PROTOCOLID_ROCE, 765 PROTOCOLID_CORE, 766 PROTOCOLID_ETH, 767 PROTOCOLID_RESERVED4, 768 PROTOCOLID_RESERVED5, 769 PROTOCOLID_PREROCE, 770 PROTOCOLID_COMMON, 771 PROTOCOLID_RESERVED6, 772 MAX_PROTOCOL_TYPE 773 }; 774 775 struct ustorm_eth_queue_zone { 776 struct coalescing_timeset int_coalescing_timeset; 777 u8 reserved[3]; 778 }; 779 780 struct ustorm_queue_zone { 781 struct ustorm_eth_queue_zone eth; 782 struct common_queue_zone common; 783 }; 784 785 /* status block structure */ 786 struct cau_pi_entry { 787 u32 prod; 788 #define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF 789 #define CAU_PI_ENTRY_PROD_VAL_SHIFT 0 790 #define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F 791 #define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16 792 #define CAU_PI_ENTRY_FSM_SEL_MASK 0x1 793 #define CAU_PI_ENTRY_FSM_SEL_SHIFT 23 794 #define CAU_PI_ENTRY_RESERVED_MASK 0xFF 795 #define CAU_PI_ENTRY_RESERVED_SHIFT 24 796 }; 797 798 /* status block structure */ 799 struct cau_sb_entry { 800 u32 data; 801 #define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF 802 #define CAU_SB_ENTRY_SB_PROD_SHIFT 0 803 #define CAU_SB_ENTRY_STATE0_MASK 0xF 804 #define CAU_SB_ENTRY_STATE0_SHIFT 24 805 #define CAU_SB_ENTRY_STATE1_MASK 0xF 806 #define CAU_SB_ENTRY_STATE1_SHIFT 28 807 u32 params; 808 #define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F 809 #define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0 810 #define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F 811 #define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7 812 #define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3 813 #define CAU_SB_ENTRY_TIMER_RES0_SHIFT 14 814 #define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3 815 #define CAU_SB_ENTRY_TIMER_RES1_SHIFT 16 816 #define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF 817 #define CAU_SB_ENTRY_VF_NUMBER_SHIFT 18 818 #define CAU_SB_ENTRY_VF_VALID_MASK 0x1 819 #define CAU_SB_ENTRY_VF_VALID_SHIFT 26 820 #define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF 821 #define CAU_SB_ENTRY_PF_NUMBER_SHIFT 27 822 #define CAU_SB_ENTRY_TPH_MASK 0x1 823 #define CAU_SB_ENTRY_TPH_SHIFT 31 824 }; 825 826 /* core doorbell data */ 827 struct core_db_data { 828 u8 params; 829 #define CORE_DB_DATA_DEST_MASK 0x3 830 #define CORE_DB_DATA_DEST_SHIFT 0 831 #define CORE_DB_DATA_AGG_CMD_MASK 0x3 832 #define CORE_DB_DATA_AGG_CMD_SHIFT 2 833 #define CORE_DB_DATA_BYPASS_EN_MASK 0x1 834 #define CORE_DB_DATA_BYPASS_EN_SHIFT 4 835 #define CORE_DB_DATA_RESERVED_MASK 0x1 836 #define CORE_DB_DATA_RESERVED_SHIFT 5 837 #define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3 838 #define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6 839 u8 agg_flags; 840 __le16 spq_prod; 841 }; 842 843 /* Enum of doorbell aggregative command selection */ 844 enum db_agg_cmd_sel { 845 DB_AGG_CMD_NOP, 846 DB_AGG_CMD_SET, 847 DB_AGG_CMD_ADD, 848 DB_AGG_CMD_MAX, 849 MAX_DB_AGG_CMD_SEL 850 }; 851 852 /* Enum of doorbell destination */ 853 enum db_dest { 854 DB_DEST_XCM, 855 DB_DEST_UCM, 856 DB_DEST_TCM, 857 DB_NUM_DESTINATIONS, 858 MAX_DB_DEST 859 }; 860 861 /* Enum of doorbell DPM types */ 862 enum db_dpm_type { 863 DPM_LEGACY, 864 DPM_ROCE, 865 DPM_L2_INLINE, 866 DPM_L2_BD, 867 MAX_DB_DPM_TYPE 868 }; 869 870 /* Structure for doorbell data, in L2 DPM mode, for 1st db in a DPM burst */ 871 struct db_l2_dpm_data { 872 __le16 icid; 873 __le16 bd_prod; 874 __le32 params; 875 #define DB_L2_DPM_DATA_SIZE_MASK 0x3F 876 #define DB_L2_DPM_DATA_SIZE_SHIFT 0 877 #define DB_L2_DPM_DATA_DPM_TYPE_MASK 0x3 878 #define DB_L2_DPM_DATA_DPM_TYPE_SHIFT 6 879 #define DB_L2_DPM_DATA_NUM_BDS_MASK 0xFF 880 #define DB_L2_DPM_DATA_NUM_BDS_SHIFT 8 881 #define DB_L2_DPM_DATA_PKT_SIZE_MASK 0x7FF 882 #define DB_L2_DPM_DATA_PKT_SIZE_SHIFT 16 883 #define DB_L2_DPM_DATA_RESERVED0_MASK 0x1 884 #define DB_L2_DPM_DATA_RESERVED0_SHIFT 27 885 #define DB_L2_DPM_DATA_SGE_NUM_MASK 0x7 886 #define DB_L2_DPM_DATA_SGE_NUM_SHIFT 28 887 #define DB_L2_DPM_DATA_RESERVED1_MASK 0x1 888 #define DB_L2_DPM_DATA_RESERVED1_SHIFT 31 889 }; 890 891 /* Structure for SGE in a DPM doorbell of type DPM_L2_BD */ 892 struct db_l2_dpm_sge { 893 struct regpair addr; 894 __le16 nbytes; 895 __le16 bitfields; 896 #define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF 897 #define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0 898 #define DB_L2_DPM_SGE_RESERVED0_MASK 0x3 899 #define DB_L2_DPM_SGE_RESERVED0_SHIFT 9 900 #define DB_L2_DPM_SGE_ST_VALID_MASK 0x1 901 #define DB_L2_DPM_SGE_ST_VALID_SHIFT 11 902 #define DB_L2_DPM_SGE_RESERVED1_MASK 0xF 903 #define DB_L2_DPM_SGE_RESERVED1_SHIFT 12 904 __le32 reserved2; 905 }; 906 907 /* Structure for doorbell address, in legacy mode */ 908 struct db_legacy_addr { 909 __le32 addr; 910 #define DB_LEGACY_ADDR_RESERVED0_MASK 0x3 911 #define DB_LEGACY_ADDR_RESERVED0_SHIFT 0 912 #define DB_LEGACY_ADDR_DEMS_MASK 0x7 913 #define DB_LEGACY_ADDR_DEMS_SHIFT 2 914 #define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF 915 #define DB_LEGACY_ADDR_ICID_SHIFT 5 916 }; 917 918 /* Structure for doorbell address, in PWM mode */ 919 struct db_pwm_addr { 920 __le32 addr; 921 #define DB_PWM_ADDR_RESERVED0_MASK 0x7 922 #define DB_PWM_ADDR_RESERVED0_SHIFT 0 923 #define DB_PWM_ADDR_OFFSET_MASK 0x7F 924 #define DB_PWM_ADDR_OFFSET_SHIFT 3 925 #define DB_PWM_ADDR_WID_MASK 0x3 926 #define DB_PWM_ADDR_WID_SHIFT 10 927 #define DB_PWM_ADDR_DPI_MASK 0xFFFF 928 #define DB_PWM_ADDR_DPI_SHIFT 12 929 #define DB_PWM_ADDR_RESERVED1_MASK 0xF 930 #define DB_PWM_ADDR_RESERVED1_SHIFT 28 931 }; 932 933 /* Parameters to RoCE firmware, passed in EDPM doorbell */ 934 struct db_roce_dpm_params { 935 __le32 params; 936 #define DB_ROCE_DPM_PARAMS_SIZE_MASK 0x3F 937 #define DB_ROCE_DPM_PARAMS_SIZE_SHIFT 0 938 #define DB_ROCE_DPM_PARAMS_DPM_TYPE_MASK 0x3 939 #define DB_ROCE_DPM_PARAMS_DPM_TYPE_SHIFT 6 940 #define DB_ROCE_DPM_PARAMS_OPCODE_MASK 0xFF 941 #define DB_ROCE_DPM_PARAMS_OPCODE_SHIFT 8 942 #define DB_ROCE_DPM_PARAMS_WQE_SIZE_MASK 0x7FF 943 #define DB_ROCE_DPM_PARAMS_WQE_SIZE_SHIFT 16 944 #define DB_ROCE_DPM_PARAMS_RESERVED0_MASK 0x1 945 #define DB_ROCE_DPM_PARAMS_RESERVED0_SHIFT 27 946 #define DB_ROCE_DPM_PARAMS_COMPLETION_FLG_MASK 0x1 947 #define DB_ROCE_DPM_PARAMS_COMPLETION_FLG_SHIFT 28 948 #define DB_ROCE_DPM_PARAMS_S_FLG_MASK 0x1 949 #define DB_ROCE_DPM_PARAMS_S_FLG_SHIFT 29 950 #define DB_ROCE_DPM_PARAMS_RESERVED1_MASK 0x3 951 #define DB_ROCE_DPM_PARAMS_RESERVED1_SHIFT 30 952 }; 953 954 /* Structure for doorbell data, in ROCE DPM mode, for 1st db in a DPM burst */ 955 struct db_roce_dpm_data { 956 __le16 icid; 957 __le16 prod_val; 958 struct db_roce_dpm_params params; 959 }; 960 961 /* Igu interrupt command */ 962 enum igu_int_cmd { 963 IGU_INT_ENABLE = 0, 964 IGU_INT_DISABLE = 1, 965 IGU_INT_NOP = 2, 966 IGU_INT_NOP2 = 3, 967 MAX_IGU_INT_CMD 968 }; 969 970 /* IGU producer or consumer update command */ 971 struct igu_prod_cons_update { 972 u32 sb_id_and_flags; 973 #define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF 974 #define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0 975 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1 976 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT 24 977 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3 978 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT 25 979 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1 980 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27 981 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1 982 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT 28 983 #define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3 984 #define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT 29 985 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1 986 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT 31 987 u32 reserved1; 988 }; 989 990 /* Igu segments access for default status block only */ 991 enum igu_seg_access { 992 IGU_SEG_ACCESS_REG = 0, 993 IGU_SEG_ACCESS_ATTN = 1, 994 MAX_IGU_SEG_ACCESS 995 }; 996 997 struct parsing_and_err_flags { 998 __le16 flags; 999 #define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3 1000 #define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0 1001 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3 1002 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2 1003 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1 1004 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4 1005 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1 1006 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5 1007 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1 1008 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6 1009 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1 1010 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7 1011 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1 1012 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT 8 1013 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1 1014 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT 9 1015 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1 1016 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10 1017 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1 1018 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11 1019 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1 1020 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12 1021 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1 1022 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13 1023 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1 1024 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14 1025 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1 1026 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15 1027 }; 1028 1029 struct pb_context { 1030 __le32 crc[4]; 1031 }; 1032 1033 struct pxp_concrete_fid { 1034 __le16 fid; 1035 #define PXP_CONCRETE_FID_PFID_MASK 0xF 1036 #define PXP_CONCRETE_FID_PFID_SHIFT 0 1037 #define PXP_CONCRETE_FID_PORT_MASK 0x3 1038 #define PXP_CONCRETE_FID_PORT_SHIFT 4 1039 #define PXP_CONCRETE_FID_PATH_MASK 0x1 1040 #define PXP_CONCRETE_FID_PATH_SHIFT 6 1041 #define PXP_CONCRETE_FID_VFVALID_MASK 0x1 1042 #define PXP_CONCRETE_FID_VFVALID_SHIFT 7 1043 #define PXP_CONCRETE_FID_VFID_MASK 0xFF 1044 #define PXP_CONCRETE_FID_VFID_SHIFT 8 1045 }; 1046 1047 struct pxp_pretend_concrete_fid { 1048 __le16 fid; 1049 #define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF 1050 #define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0 1051 #define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7 1052 #define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4 1053 #define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1 1054 #define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT 7 1055 #define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF 1056 #define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8 1057 }; 1058 1059 union pxp_pretend_fid { 1060 struct pxp_pretend_concrete_fid concrete_fid; 1061 __le16 opaque_fid; 1062 }; 1063 1064 /* Pxp Pretend Command Register. */ 1065 struct pxp_pretend_cmd { 1066 union pxp_pretend_fid fid; 1067 __le16 control; 1068 #define PXP_PRETEND_CMD_PATH_MASK 0x1 1069 #define PXP_PRETEND_CMD_PATH_SHIFT 0 1070 #define PXP_PRETEND_CMD_USE_PORT_MASK 0x1 1071 #define PXP_PRETEND_CMD_USE_PORT_SHIFT 1 1072 #define PXP_PRETEND_CMD_PORT_MASK 0x3 1073 #define PXP_PRETEND_CMD_PORT_SHIFT 2 1074 #define PXP_PRETEND_CMD_RESERVED0_MASK 0xF 1075 #define PXP_PRETEND_CMD_RESERVED0_SHIFT 4 1076 #define PXP_PRETEND_CMD_RESERVED1_MASK 0xF 1077 #define PXP_PRETEND_CMD_RESERVED1_SHIFT 8 1078 #define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1 1079 #define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT 12 1080 #define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1 1081 #define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT 13 1082 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1 1083 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14 1084 #define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1 1085 #define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15 1086 }; 1087 1088 /* PTT Record in PXP Admin Window. */ 1089 struct pxp_ptt_entry { 1090 __le32 offset; 1091 #define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF 1092 #define PXP_PTT_ENTRY_OFFSET_SHIFT 0 1093 #define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF 1094 #define PXP_PTT_ENTRY_RESERVED0_SHIFT 23 1095 struct pxp_pretend_cmd pretend; 1096 }; 1097 1098 /* VF Zone A Permission Register. */ 1099 struct pxp_vf_zone_a_permission { 1100 __le32 control; 1101 #define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF 1102 #define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0 1103 #define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1 1104 #define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT 8 1105 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F 1106 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT 9 1107 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF 1108 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16 1109 }; 1110 1111 /* RSS hash type */ 1112 struct rdif_task_context { 1113 __le32 initial_ref_tag; 1114 __le16 app_tag_value; 1115 __le16 app_tag_mask; 1116 u8 flags0; 1117 #define RDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1 1118 #define RDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0 1119 #define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1 1120 #define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1 1121 #define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1 1122 #define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2 1123 #define RDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1 1124 #define RDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3 1125 #define RDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3 1126 #define RDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4 1127 #define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 1128 #define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 1129 #define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1 1130 #define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 7 1131 u8 partial_dif_data[7]; 1132 __le16 partial_crc_value; 1133 __le16 partial_checksum_value; 1134 __le32 offset_in_io; 1135 __le16 flags1; 1136 #define RDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1 1137 #define RDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0 1138 #define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1 1139 #define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1 1140 #define RDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1 1141 #define RDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2 1142 #define RDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1 1143 #define RDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3 1144 #define RDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1 1145 #define RDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4 1146 #define RDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1 1147 #define RDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5 1148 #define RDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7 1149 #define RDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6 1150 #define RDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3 1151 #define RDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9 1152 #define RDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1 1153 #define RDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11 1154 #define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1 1155 #define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12 1156 #define RDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1 1157 #define RDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13 1158 #define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1 1159 #define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 14 1160 #define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1 1161 #define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 15 1162 __le16 state; 1163 #define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_MASK 0xF 1164 #define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_SHIFT 0 1165 #define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_MASK 0xF 1166 #define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_SHIFT 4 1167 #define RDIF_TASK_CONTEXT_ERRORINIO_MASK 0x1 1168 #define RDIF_TASK_CONTEXT_ERRORINIO_SHIFT 8 1169 #define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1 1170 #define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9 1171 #define RDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF 1172 #define RDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 10 1173 #define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3 1174 #define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14 1175 __le32 reserved2; 1176 }; 1177 1178 /* RSS hash type */ 1179 enum rss_hash_type { 1180 RSS_HASH_TYPE_DEFAULT = 0, 1181 RSS_HASH_TYPE_IPV4 = 1, 1182 RSS_HASH_TYPE_TCP_IPV4 = 2, 1183 RSS_HASH_TYPE_IPV6 = 3, 1184 RSS_HASH_TYPE_TCP_IPV6 = 4, 1185 RSS_HASH_TYPE_UDP_IPV4 = 5, 1186 RSS_HASH_TYPE_UDP_IPV6 = 6, 1187 MAX_RSS_HASH_TYPE 1188 }; 1189 1190 /* status block structure */ 1191 struct status_block { 1192 __le16 pi_array[PIS_PER_SB]; 1193 __le32 sb_num; 1194 #define STATUS_BLOCK_SB_NUM_MASK 0x1FF 1195 #define STATUS_BLOCK_SB_NUM_SHIFT 0 1196 #define STATUS_BLOCK_ZERO_PAD_MASK 0x7F 1197 #define STATUS_BLOCK_ZERO_PAD_SHIFT 9 1198 #define STATUS_BLOCK_ZERO_PAD2_MASK 0xFFFF 1199 #define STATUS_BLOCK_ZERO_PAD2_SHIFT 16 1200 __le32 prod_index; 1201 #define STATUS_BLOCK_PROD_INDEX_MASK 0xFFFFFF 1202 #define STATUS_BLOCK_PROD_INDEX_SHIFT 0 1203 #define STATUS_BLOCK_ZERO_PAD3_MASK 0xFF 1204 #define STATUS_BLOCK_ZERO_PAD3_SHIFT 24 1205 }; 1206 1207 struct tdif_task_context { 1208 __le32 initial_ref_tag; 1209 __le16 app_tag_value; 1210 __le16 app_tag_mask; 1211 __le16 partial_crc_valueB; 1212 __le16 partial_checksum_valueB; 1213 __le16 stateB; 1214 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_MASK 0xF 1215 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_SHIFT 0 1216 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_MASK 0xF 1217 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_SHIFT 4 1218 #define TDIF_TASK_CONTEXT_ERRORINIOB_MASK 0x1 1219 #define TDIF_TASK_CONTEXT_ERRORINIOB_SHIFT 8 1220 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1 1221 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9 1222 #define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F 1223 #define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10 1224 u8 reserved1; 1225 u8 flags0; 1226 #define TDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1 1227 #define TDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0 1228 #define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1 1229 #define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1 1230 #define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1 1231 #define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2 1232 #define TDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1 1233 #define TDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3 1234 #define TDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3 1235 #define TDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4 1236 #define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 1237 #define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 1238 #define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1 1239 #define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7 1240 __le32 flags1; 1241 #define TDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1 1242 #define TDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0 1243 #define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1 1244 #define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1 1245 #define TDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1 1246 #define TDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2 1247 #define TDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1 1248 #define TDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3 1249 #define TDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1 1250 #define TDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4 1251 #define TDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1 1252 #define TDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5 1253 #define TDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7 1254 #define TDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6 1255 #define TDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3 1256 #define TDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9 1257 #define TDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1 1258 #define TDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11 1259 #define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1 1260 #define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12 1261 #define TDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1 1262 #define TDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13 1263 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_MASK 0xF 1264 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_SHIFT 14 1265 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_MASK 0xF 1266 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_SHIFT 18 1267 #define TDIF_TASK_CONTEXT_ERRORINIOA_MASK 0x1 1268 #define TDIF_TASK_CONTEXT_ERRORINIOA_SHIFT 22 1269 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_MASK 0x1 1270 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_SHIFT 23 1271 #define TDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF 1272 #define TDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 24 1273 #define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1 1274 #define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 28 1275 #define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1 1276 #define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 29 1277 #define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1 1278 #define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 30 1279 #define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1 1280 #define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31 1281 __le32 offset_in_iob; 1282 __le16 partial_crc_value_a; 1283 __le16 partial_checksum_valuea_; 1284 __le32 offset_in_ioa; 1285 u8 partial_dif_data_a[8]; 1286 u8 partial_dif_data_b[8]; 1287 }; 1288 1289 struct timers_context { 1290 __le32 logical_client_0; 1291 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0xFFFFFFF 1292 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT 0 1293 #define TIMERS_CONTEXT_VALIDLC0_MASK 0x1 1294 #define TIMERS_CONTEXT_VALIDLC0_SHIFT 28 1295 #define TIMERS_CONTEXT_ACTIVELC0_MASK 0x1 1296 #define TIMERS_CONTEXT_ACTIVELC0_SHIFT 29 1297 #define TIMERS_CONTEXT_RESERVED0_MASK 0x3 1298 #define TIMERS_CONTEXT_RESERVED0_SHIFT 30 1299 __le32 logical_client_1; 1300 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK 0xFFFFFFF 1301 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT 0 1302 #define TIMERS_CONTEXT_VALIDLC1_MASK 0x1 1303 #define TIMERS_CONTEXT_VALIDLC1_SHIFT 28 1304 #define TIMERS_CONTEXT_ACTIVELC1_MASK 0x1 1305 #define TIMERS_CONTEXT_ACTIVELC1_SHIFT 29 1306 #define TIMERS_CONTEXT_RESERVED1_MASK 0x3 1307 #define TIMERS_CONTEXT_RESERVED1_SHIFT 30 1308 __le32 logical_client_2; 1309 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK 0xFFFFFFF 1310 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT 0 1311 #define TIMERS_CONTEXT_VALIDLC2_MASK 0x1 1312 #define TIMERS_CONTEXT_VALIDLC2_SHIFT 28 1313 #define TIMERS_CONTEXT_ACTIVELC2_MASK 0x1 1314 #define TIMERS_CONTEXT_ACTIVELC2_SHIFT 29 1315 #define TIMERS_CONTEXT_RESERVED2_MASK 0x3 1316 #define TIMERS_CONTEXT_RESERVED2_SHIFT 30 1317 __le32 host_expiration_fields; 1318 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_MASK 0xFFFFFFF 1319 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_SHIFT 0 1320 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_MASK 0x1 1321 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_SHIFT 28 1322 #define TIMERS_CONTEXT_RESERVED3_MASK 0x7 1323 #define TIMERS_CONTEXT_RESERVED3_SHIFT 29 1324 }; 1325 #endif /* __COMMON_HSI__ */ 1326 #endif 1327