1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2016 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _COMMON_HSI_H 34 #define _COMMON_HSI_H 35 #include <linux/types.h> 36 #include <asm/byteorder.h> 37 #include <linux/bitops.h> 38 #include <linux/slab.h> 39 40 /* dma_addr_t manip */ 41 #define DMA_LO_LE(x) cpu_to_le32(lower_32_bits(x)) 42 #define DMA_HI_LE(x) cpu_to_le32(upper_32_bits(x)) 43 #define DMA_REGPAIR_LE(x, val) do { \ 44 (x).hi = DMA_HI_LE((val)); \ 45 (x).lo = DMA_LO_LE((val)); \ 46 } while (0) 47 48 #define HILO_GEN(hi, lo, type) ((((type)(hi)) << 32) + (lo)) 49 #define HILO_64(hi, lo) HILO_GEN((le32_to_cpu(hi)), (le32_to_cpu(lo)), u64) 50 #define HILO_64_REGPAIR(regpair) (HILO_64(regpair.hi, regpair.lo)) 51 #define HILO_DMA_REGPAIR(regpair) ((dma_addr_t)HILO_64_REGPAIR(regpair)) 52 53 #ifndef __COMMON_HSI__ 54 #define __COMMON_HSI__ 55 56 57 #define X_FINAL_CLEANUP_AGG_INT 1 58 59 #define EVENT_RING_PAGE_SIZE_BYTES 4096 60 61 #define NUM_OF_GLOBAL_QUEUES 128 62 #define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64 63 64 #define ISCSI_CDU_TASK_SEG_TYPE 0 65 #define FCOE_CDU_TASK_SEG_TYPE 0 66 #define RDMA_CDU_TASK_SEG_TYPE 1 67 68 #define FW_ASSERT_GENERAL_ATTN_IDX 32 69 70 #define MAX_PINNED_CCFC 32 71 72 /* Queue Zone sizes in bytes */ 73 #define TSTORM_QZONE_SIZE 8 74 #define MSTORM_QZONE_SIZE 16 75 #define USTORM_QZONE_SIZE 8 76 #define XSTORM_QZONE_SIZE 8 77 #define YSTORM_QZONE_SIZE 0 78 #define PSTORM_QZONE_SIZE 0 79 80 #define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7 81 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT 16 82 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE 48 83 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD 112 84 85 /********************************/ 86 /* CORE (LIGHT L2) FW CONSTANTS */ 87 /********************************/ 88 89 #define CORE_LL2_MAX_RAMROD_PER_CON 8 90 #define CORE_LL2_TX_BD_PAGE_SIZE_BYTES 4096 91 #define CORE_LL2_RX_BD_PAGE_SIZE_BYTES 4096 92 #define CORE_LL2_RX_CQE_PAGE_SIZE_BYTES 4096 93 #define CORE_LL2_RX_NUM_NEXT_PAGE_BDS 1 94 95 #define CORE_LL2_TX_MAX_BDS_PER_PACKET 12 96 97 #define CORE_SPQE_PAGE_SIZE_BYTES 4096 98 99 #define MAX_NUM_LL2_RX_QUEUES 32 100 #define MAX_NUM_LL2_TX_STATS_COUNTERS 32 101 102 #define FW_MAJOR_VERSION 8 103 #define FW_MINOR_VERSION 10 104 #define FW_REVISION_VERSION 10 105 #define FW_ENGINEERING_VERSION 0 106 107 /***********************/ 108 /* COMMON HW CONSTANTS */ 109 /***********************/ 110 111 /* PCI functions */ 112 #define MAX_NUM_PORTS_K2 (4) 113 #define MAX_NUM_PORTS_BB (2) 114 #define MAX_NUM_PORTS (MAX_NUM_PORTS_K2) 115 116 #define MAX_NUM_PFS_K2 (16) 117 #define MAX_NUM_PFS_BB (8) 118 #define MAX_NUM_PFS (MAX_NUM_PFS_K2) 119 #define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */ 120 121 #define MAX_NUM_VFS_K2 (192) 122 #define MAX_NUM_VFS_BB (120) 123 #define MAX_NUM_VFS (MAX_NUM_VFS_K2) 124 125 #define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB) 126 #define MAX_NUM_FUNCTIONS (MAX_NUM_PFS + MAX_NUM_VFS) 127 128 #define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB) 129 #define MAX_FUNCTION_NUMBER (MAX_NUM_PFS + MAX_NUM_VFS) 130 131 #define MAX_NUM_VPORTS_K2 (208) 132 #define MAX_NUM_VPORTS_BB (160) 133 #define MAX_NUM_VPORTS (MAX_NUM_VPORTS_K2) 134 135 #define MAX_NUM_L2_QUEUES_K2 (320) 136 #define MAX_NUM_L2_QUEUES_BB (256) 137 #define MAX_NUM_L2_QUEUES (MAX_NUM_L2_QUEUES_K2) 138 139 /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */ 140 #define NUM_PHYS_TCS_4PORT_K2 (4) 141 #define NUM_OF_PHYS_TCS (8) 142 143 #define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1) 144 #define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1) 145 146 #define LB_TC (NUM_OF_PHYS_TCS) 147 148 /* Num of possible traffic priority values */ 149 #define NUM_OF_PRIO (8) 150 151 #define MAX_NUM_VOQS_K2 (NUM_TCS_4PORT_K2 * MAX_NUM_PORTS_K2) 152 #define MAX_NUM_VOQS_BB (NUM_OF_TCS * MAX_NUM_PORTS_BB) 153 #define MAX_NUM_VOQS (MAX_NUM_VOQS_K2) 154 #define MAX_PHYS_VOQS (NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB) 155 156 /* CIDs */ 157 #define NUM_OF_CONNECTION_TYPES (8) 158 #define NUM_OF_LCIDS (320) 159 #define NUM_OF_LTIDS (320) 160 161 /* Clock values */ 162 #define MASTER_CLK_FREQ_E4 (375e6) 163 #define STORM_CLK_FREQ_E4 (1000e6) 164 #define CLK25M_CLK_FREQ_E4 (25e6) 165 166 /* Global PXP windows (GTT) */ 167 #define NUM_OF_GTT 19 168 #define GTT_DWORD_SIZE_BITS 10 169 #define GTT_BYTE_SIZE_BITS (GTT_DWORD_SIZE_BITS + 2) 170 #define GTT_DWORD_SIZE BIT(GTT_DWORD_SIZE_BITS) 171 172 /* Tools Version */ 173 #define TOOLS_VERSION 10 174 175 /*****************/ 176 /* CDU CONSTANTS */ 177 /*****************/ 178 179 #define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17) 180 #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff) 181 182 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12) 183 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff) 184 /*****************/ 185 /* DQ CONSTANTS */ 186 /*****************/ 187 188 /* DEMS */ 189 #define DQ_DEMS_LEGACY 0 190 191 /* XCM agg val selection */ 192 #define DQ_XCM_AGG_VAL_SEL_WORD2 0 193 #define DQ_XCM_AGG_VAL_SEL_WORD3 1 194 #define DQ_XCM_AGG_VAL_SEL_WORD4 2 195 #define DQ_XCM_AGG_VAL_SEL_WORD5 3 196 #define DQ_XCM_AGG_VAL_SEL_REG3 4 197 #define DQ_XCM_AGG_VAL_SEL_REG4 5 198 #define DQ_XCM_AGG_VAL_SEL_REG5 6 199 #define DQ_XCM_AGG_VAL_SEL_REG6 7 200 201 /* XCM agg val selection */ 202 #define DQ_XCM_CORE_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 203 #define DQ_XCM_CORE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 204 #define DQ_XCM_CORE_SPQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 205 #define DQ_XCM_ETH_EDPM_NUM_BDS_CMD DQ_XCM_AGG_VAL_SEL_WORD2 206 #define DQ_XCM_ETH_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 207 #define DQ_XCM_ETH_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 208 #define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5 209 #define DQ_XCM_FCOE_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 210 #define DQ_XCM_FCOE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 211 #define DQ_XCM_FCOE_X_FERQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD5 212 #define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 213 #define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 214 #define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 215 #define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6 216 #define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 217 218 /* UCM agg val selection (HW) */ 219 #define DQ_UCM_AGG_VAL_SEL_WORD0 0 220 #define DQ_UCM_AGG_VAL_SEL_WORD1 1 221 #define DQ_UCM_AGG_VAL_SEL_WORD2 2 222 #define DQ_UCM_AGG_VAL_SEL_WORD3 3 223 #define DQ_UCM_AGG_VAL_SEL_REG0 4 224 #define DQ_UCM_AGG_VAL_SEL_REG1 5 225 #define DQ_UCM_AGG_VAL_SEL_REG2 6 226 #define DQ_UCM_AGG_VAL_SEL_REG3 7 227 228 /* UCM agg val selection (FW) */ 229 #define DQ_UCM_ETH_PMD_TX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD2 230 #define DQ_UCM_ETH_PMD_RX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD3 231 #define DQ_UCM_ROCE_CQ_CONS_CMD DQ_UCM_AGG_VAL_SEL_REG0 232 #define DQ_UCM_ROCE_CQ_PROD_CMD DQ_UCM_AGG_VAL_SEL_REG2 233 234 /* TCM agg val selection (HW) */ 235 #define DQ_TCM_AGG_VAL_SEL_WORD0 0 236 #define DQ_TCM_AGG_VAL_SEL_WORD1 1 237 #define DQ_TCM_AGG_VAL_SEL_WORD2 2 238 #define DQ_TCM_AGG_VAL_SEL_WORD3 3 239 #define DQ_TCM_AGG_VAL_SEL_REG1 4 240 #define DQ_TCM_AGG_VAL_SEL_REG2 5 241 #define DQ_TCM_AGG_VAL_SEL_REG6 6 242 #define DQ_TCM_AGG_VAL_SEL_REG9 7 243 244 /* TCM agg val selection (FW) */ 245 #define DQ_TCM_L2B_BD_PROD_CMD \ 246 DQ_TCM_AGG_VAL_SEL_WORD1 247 #define DQ_TCM_ROCE_RQ_PROD_CMD \ 248 DQ_TCM_AGG_VAL_SEL_WORD0 249 250 /* XCM agg counter flag selection */ 251 #define DQ_XCM_AGG_FLG_SHIFT_BIT14 0 252 #define DQ_XCM_AGG_FLG_SHIFT_BIT15 1 253 #define DQ_XCM_AGG_FLG_SHIFT_CF12 2 254 #define DQ_XCM_AGG_FLG_SHIFT_CF13 3 255 #define DQ_XCM_AGG_FLG_SHIFT_CF18 4 256 #define DQ_XCM_AGG_FLG_SHIFT_CF19 5 257 #define DQ_XCM_AGG_FLG_SHIFT_CF22 6 258 #define DQ_XCM_AGG_FLG_SHIFT_CF23 7 259 260 /* XCM agg counter flag selection */ 261 #define DQ_XCM_CORE_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18) 262 #define DQ_XCM_CORE_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19) 263 #define DQ_XCM_CORE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) 264 #define DQ_XCM_ETH_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18) 265 #define DQ_XCM_ETH_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19) 266 #define DQ_XCM_ETH_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) 267 #define DQ_XCM_ETH_TPH_EN_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23) 268 #define DQ_XCM_FCOE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) 269 #define DQ_XCM_ISCSI_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19) 270 #define DQ_XCM_ISCSI_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) 271 #define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23) 272 273 /* UCM agg counter flag selection (HW) */ 274 #define DQ_UCM_AGG_FLG_SHIFT_CF0 0 275 #define DQ_UCM_AGG_FLG_SHIFT_CF1 1 276 #define DQ_UCM_AGG_FLG_SHIFT_CF3 2 277 #define DQ_UCM_AGG_FLG_SHIFT_CF4 3 278 #define DQ_UCM_AGG_FLG_SHIFT_CF5 4 279 #define DQ_UCM_AGG_FLG_SHIFT_CF6 5 280 #define DQ_UCM_AGG_FLG_SHIFT_RULE0EN 6 281 #define DQ_UCM_AGG_FLG_SHIFT_RULE1EN 7 282 283 /* UCM agg counter flag selection (FW) */ 284 #define DQ_UCM_ETH_PMD_TX_ARM_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF4) 285 #define DQ_UCM_ETH_PMD_RX_ARM_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF5) 286 #define DQ_UCM_ROCE_CQ_ARM_SE_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF4) 287 #define DQ_UCM_ROCE_CQ_ARM_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF5) 288 289 /* TCM agg counter flag selection (HW) */ 290 #define DQ_TCM_AGG_FLG_SHIFT_CF0 0 291 #define DQ_TCM_AGG_FLG_SHIFT_CF1 1 292 #define DQ_TCM_AGG_FLG_SHIFT_CF2 2 293 #define DQ_TCM_AGG_FLG_SHIFT_CF3 3 294 #define DQ_TCM_AGG_FLG_SHIFT_CF4 4 295 #define DQ_TCM_AGG_FLG_SHIFT_CF5 5 296 #define DQ_TCM_AGG_FLG_SHIFT_CF6 6 297 #define DQ_TCM_AGG_FLG_SHIFT_CF7 7 298 /* TCM agg counter flag selection (FW) */ 299 #define DQ_TCM_FCOE_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1) 300 #define DQ_TCM_FCOE_DUMMY_TIMER_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF2) 301 #define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3) 302 #define DQ_TCM_ISCSI_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1) 303 #define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3) 304 305 /* PWM address mapping */ 306 #define DQ_PWM_OFFSET_DPM_BASE 0x0 307 #define DQ_PWM_OFFSET_DPM_END 0x27 308 #define DQ_PWM_OFFSET_XCM16_BASE 0x40 309 #define DQ_PWM_OFFSET_XCM32_BASE 0x44 310 #define DQ_PWM_OFFSET_UCM16_BASE 0x48 311 #define DQ_PWM_OFFSET_UCM32_BASE 0x4C 312 #define DQ_PWM_OFFSET_UCM16_4 0x50 313 #define DQ_PWM_OFFSET_TCM16_BASE 0x58 314 #define DQ_PWM_OFFSET_TCM32_BASE 0x5C 315 #define DQ_PWM_OFFSET_XCM_FLAGS 0x68 316 #define DQ_PWM_OFFSET_UCM_FLAGS 0x69 317 #define DQ_PWM_OFFSET_TCM_FLAGS 0x6B 318 319 #define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD (DQ_PWM_OFFSET_XCM16_BASE + 2) 320 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT (DQ_PWM_OFFSET_UCM32_BASE) 321 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_16BIT (DQ_PWM_OFFSET_UCM16_4) 322 #define DQ_PWM_OFFSET_UCM_RDMA_INT_TIMEOUT (DQ_PWM_OFFSET_UCM16_BASE + 2) 323 #define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS (DQ_PWM_OFFSET_UCM_FLAGS) 324 #define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 1) 325 #define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 3) 326 #define DQ_REGION_SHIFT (12) 327 328 /* DPM */ 329 #define DQ_DPM_WQE_BUFF_SIZE (320) 330 331 /* Conn type ranges */ 332 #define DQ_CONN_TYPE_RANGE_SHIFT (4) 333 334 /*****************/ 335 /* QM CONSTANTS */ 336 /*****************/ 337 338 /* number of TX queues in the QM */ 339 #define MAX_QM_TX_QUEUES_K2 512 340 #define MAX_QM_TX_QUEUES_BB 448 341 #define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2 342 343 /* number of Other queues in the QM */ 344 #define MAX_QM_OTHER_QUEUES_BB 64 345 #define MAX_QM_OTHER_QUEUES_K2 128 346 #define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2 347 348 /* number of queues in a PF queue group */ 349 #define QM_PF_QUEUE_GROUP_SIZE 8 350 351 /* the size of a single queue element in bytes */ 352 #define QM_PQ_ELEMENT_SIZE 4 353 354 /* base number of Tx PQs in the CM PQ representation. 355 * should be used when storing PQ IDs in CM PQ registers and context 356 */ 357 #define CM_TX_PQ_BASE 0x200 358 359 /* number of global Vport/QCN rate limiters */ 360 #define MAX_QM_GLOBAL_RLS 256 361 /* QM registers data */ 362 #define QM_LINE_CRD_REG_WIDTH 16 363 #define QM_LINE_CRD_REG_SIGN_BIT BIT((QM_LINE_CRD_REG_WIDTH - 1)) 364 #define QM_BYTE_CRD_REG_WIDTH 24 365 #define QM_BYTE_CRD_REG_SIGN_BIT BIT((QM_BYTE_CRD_REG_WIDTH - 1)) 366 #define QM_WFQ_CRD_REG_WIDTH 32 367 #define QM_WFQ_CRD_REG_SIGN_BIT BIT((QM_WFQ_CRD_REG_WIDTH - 1)) 368 #define QM_RL_CRD_REG_WIDTH 32 369 #define QM_RL_CRD_REG_SIGN_BIT BIT((QM_RL_CRD_REG_WIDTH - 1)) 370 371 /*****************/ 372 /* CAU CONSTANTS */ 373 /*****************/ 374 375 #define CAU_FSM_ETH_RX 0 376 #define CAU_FSM_ETH_TX 1 377 378 /* Number of Protocol Indices per Status Block */ 379 #define PIS_PER_SB 12 380 381 #define CAU_HC_STOPPED_STATE 3 382 #define CAU_HC_DISABLE_STATE 4 383 #define CAU_HC_ENABLE_STATE 0 384 385 /*****************/ 386 /* IGU CONSTANTS */ 387 /*****************/ 388 389 #define MAX_SB_PER_PATH_K2 (368) 390 #define MAX_SB_PER_PATH_BB (288) 391 #define MAX_TOT_SB_PER_PATH \ 392 MAX_SB_PER_PATH_K2 393 394 #define MAX_SB_PER_PF_MIMD 129 395 #define MAX_SB_PER_PF_SIMD 64 396 #define MAX_SB_PER_VF 64 397 398 /* Memory addresses on the BAR for the IGU Sub Block */ 399 #define IGU_MEM_BASE 0x0000 400 401 #define IGU_MEM_MSIX_BASE 0x0000 402 #define IGU_MEM_MSIX_UPPER 0x0101 403 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff 404 405 #define IGU_MEM_PBA_MSIX_BASE 0x0200 406 #define IGU_MEM_PBA_MSIX_UPPER 0x0202 407 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff 408 409 #define IGU_CMD_INT_ACK_BASE 0x0400 410 #define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + \ 411 MAX_TOT_SB_PER_PATH - \ 412 1) 413 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff 414 415 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0 416 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05f1 417 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05f2 418 419 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05f3 420 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05f4 421 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05f5 422 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05f6 423 424 #define IGU_CMD_PROD_UPD_BASE 0x0600 425 #define IGU_CMD_PROD_UPD_UPPER (IGU_CMD_PROD_UPD_BASE +\ 426 MAX_TOT_SB_PER_PATH - \ 427 1) 428 #define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff 429 430 /*****************/ 431 /* PXP CONSTANTS */ 432 /*****************/ 433 434 /* Bars for Blocks */ 435 #define PXP_BAR_GRC 0 436 #define PXP_BAR_TSDM 0 437 #define PXP_BAR_USDM 0 438 #define PXP_BAR_XSDM 0 439 #define PXP_BAR_MSDM 0 440 #define PXP_BAR_YSDM 0 441 #define PXP_BAR_PSDM 0 442 #define PXP_BAR_IGU 0 443 #define PXP_BAR_DQ 1 444 445 /* PTT and GTT */ 446 #define PXP_NUM_PF_WINDOWS 12 447 #define PXP_PER_PF_ENTRY_SIZE 8 448 #define PXP_NUM_GLOBAL_WINDOWS 243 449 #define PXP_GLOBAL_ENTRY_SIZE 4 450 #define PXP_ADMIN_WINDOW_ALLOWED_LENGTH 4 451 #define PXP_PF_WINDOW_ADMIN_START 0 452 #define PXP_PF_WINDOW_ADMIN_LENGTH 0x1000 453 #define PXP_PF_WINDOW_ADMIN_END (PXP_PF_WINDOW_ADMIN_START + \ 454 PXP_PF_WINDOW_ADMIN_LENGTH - 1) 455 #define PXP_PF_WINDOW_ADMIN_PER_PF_START 0 456 #define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH (PXP_NUM_PF_WINDOWS * \ 457 PXP_PER_PF_ENTRY_SIZE) 458 #define PXP_PF_WINDOW_ADMIN_PER_PF_END (PXP_PF_WINDOW_ADMIN_PER_PF_START + \ 459 PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1) 460 #define PXP_PF_WINDOW_ADMIN_GLOBAL_START 0x200 461 #define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH (PXP_NUM_GLOBAL_WINDOWS * \ 462 PXP_GLOBAL_ENTRY_SIZE) 463 #define PXP_PF_WINDOW_ADMIN_GLOBAL_END \ 464 (PXP_PF_WINDOW_ADMIN_GLOBAL_START + \ 465 PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1) 466 #define PXP_PF_GLOBAL_PRETEND_ADDR 0x1f0 467 #define PXP_PF_ME_OPAQUE_MASK_ADDR 0xf4 468 #define PXP_PF_ME_OPAQUE_ADDR 0x1f8 469 #define PXP_PF_ME_CONCRETE_ADDR 0x1fc 470 471 #define PXP_EXTERNAL_BAR_PF_WINDOW_START 0x1000 472 #define PXP_EXTERNAL_BAR_PF_WINDOW_NUM PXP_NUM_PF_WINDOWS 473 #define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE 0x1000 474 #define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH \ 475 (PXP_EXTERNAL_BAR_PF_WINDOW_NUM * \ 476 PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) 477 #define PXP_EXTERNAL_BAR_PF_WINDOW_END \ 478 (PXP_EXTERNAL_BAR_PF_WINDOW_START + \ 479 PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH - 1) 480 481 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START \ 482 (PXP_EXTERNAL_BAR_PF_WINDOW_END + 1) 483 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM PXP_NUM_GLOBAL_WINDOWS 484 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE 0x1000 485 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH \ 486 (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM * \ 487 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE) 488 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END \ 489 (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + \ 490 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1) 491 492 /* PF BAR */ 493 #define PXP_BAR0_START_GRC 0x0000 494 #define PXP_BAR0_GRC_LENGTH 0x1C00000 495 #define PXP_BAR0_END_GRC (PXP_BAR0_START_GRC + \ 496 PXP_BAR0_GRC_LENGTH - 1) 497 498 #define PXP_BAR0_START_IGU 0x1C00000 499 #define PXP_BAR0_IGU_LENGTH 0x10000 500 #define PXP_BAR0_END_IGU (PXP_BAR0_START_IGU + \ 501 PXP_BAR0_IGU_LENGTH - 1) 502 503 #define PXP_BAR0_START_TSDM 0x1C80000 504 #define PXP_BAR0_SDM_LENGTH 0x40000 505 #define PXP_BAR0_SDM_RESERVED_LENGTH 0x40000 506 #define PXP_BAR0_END_TSDM (PXP_BAR0_START_TSDM + \ 507 PXP_BAR0_SDM_LENGTH - 1) 508 509 #define PXP_BAR0_START_MSDM 0x1D00000 510 #define PXP_BAR0_END_MSDM (PXP_BAR0_START_MSDM + \ 511 PXP_BAR0_SDM_LENGTH - 1) 512 513 #define PXP_BAR0_START_USDM 0x1D80000 514 #define PXP_BAR0_END_USDM (PXP_BAR0_START_USDM + \ 515 PXP_BAR0_SDM_LENGTH - 1) 516 517 #define PXP_BAR0_START_XSDM 0x1E00000 518 #define PXP_BAR0_END_XSDM (PXP_BAR0_START_XSDM + \ 519 PXP_BAR0_SDM_LENGTH - 1) 520 521 #define PXP_BAR0_START_YSDM 0x1E80000 522 #define PXP_BAR0_END_YSDM (PXP_BAR0_START_YSDM + \ 523 PXP_BAR0_SDM_LENGTH - 1) 524 525 #define PXP_BAR0_START_PSDM 0x1F00000 526 #define PXP_BAR0_END_PSDM (PXP_BAR0_START_PSDM + \ 527 PXP_BAR0_SDM_LENGTH - 1) 528 529 #define PXP_BAR0_FIRST_INVALID_ADDRESS (PXP_BAR0_END_PSDM + 1) 530 531 /* VF BAR */ 532 #define PXP_VF_BAR0 0 533 534 #define PXP_VF_BAR0_START_GRC 0x3E00 535 #define PXP_VF_BAR0_GRC_LENGTH 0x200 536 #define PXP_VF_BAR0_END_GRC (PXP_VF_BAR0_START_GRC + \ 537 PXP_VF_BAR0_GRC_LENGTH - 1) 538 539 #define PXP_VF_BAR0_START_IGU 0 540 #define PXP_VF_BAR0_IGU_LENGTH 0x3000 541 #define PXP_VF_BAR0_END_IGU (PXP_VF_BAR0_START_IGU + \ 542 PXP_VF_BAR0_IGU_LENGTH - 1) 543 544 #define PXP_VF_BAR0_START_DQ 0x3000 545 #define PXP_VF_BAR0_DQ_LENGTH 0x200 546 #define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0 547 #define PXP_VF_BAR0_ME_OPAQUE_ADDRESS (PXP_VF_BAR0_START_DQ + \ 548 PXP_VF_BAR0_DQ_OPAQUE_OFFSET) 549 #define PXP_VF_BAR0_ME_CONCRETE_ADDRESS (PXP_VF_BAR0_ME_OPAQUE_ADDRESS \ 550 + 4) 551 #define PXP_VF_BAR0_END_DQ (PXP_VF_BAR0_START_DQ + \ 552 PXP_VF_BAR0_DQ_LENGTH - 1) 553 554 #define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200 555 #define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200 556 #define PXP_VF_BAR0_END_TSDM_ZONE_B (PXP_VF_BAR0_START_TSDM_ZONE_B \ 557 + \ 558 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 559 - 1) 560 561 #define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400 562 #define PXP_VF_BAR0_END_MSDM_ZONE_B (PXP_VF_BAR0_START_MSDM_ZONE_B \ 563 + \ 564 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 565 - 1) 566 567 #define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600 568 #define PXP_VF_BAR0_END_USDM_ZONE_B (PXP_VF_BAR0_START_USDM_ZONE_B \ 569 + \ 570 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 571 - 1) 572 573 #define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800 574 #define PXP_VF_BAR0_END_XSDM_ZONE_B (PXP_VF_BAR0_START_XSDM_ZONE_B \ 575 + \ 576 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 577 - 1) 578 579 #define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00 580 #define PXP_VF_BAR0_END_YSDM_ZONE_B (PXP_VF_BAR0_START_YSDM_ZONE_B \ 581 + \ 582 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 583 - 1) 584 585 #define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00 586 #define PXP_VF_BAR0_END_PSDM_ZONE_B (PXP_VF_BAR0_START_PSDM_ZONE_B \ 587 + \ 588 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 589 - 1) 590 591 #define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000 592 #define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000 593 594 #define PXP_VF_BAR0_GRC_WINDOW_LENGTH 32 595 596 #define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12 597 #define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024 598 599 /* ILT Records */ 600 #define PXP_NUM_ILT_RECORDS_BB 7600 601 #define PXP_NUM_ILT_RECORDS_K2 11000 602 #define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2) 603 #define PXP_QUEUES_ZONE_MAX_NUM 320 604 /*****************/ 605 /* PRM CONSTANTS */ 606 /*****************/ 607 #define PRM_DMA_PAD_BYTES_NUM 2 608 /******************/ 609 /* SDMs CONSTANTS */ 610 /******************/ 611 #define SDM_OP_GEN_TRIG_NONE 0 612 #define SDM_OP_GEN_TRIG_WAKE_THREAD 1 613 #define SDM_OP_GEN_TRIG_AGG_INT 2 614 #define SDM_OP_GEN_TRIG_LOADER 4 615 #define SDM_OP_GEN_TRIG_INDICATE_ERROR 6 616 #define SDM_OP_GEN_TRIG_RELEASE_THREAD 7 617 618 #define SDM_COMP_TYPE_NONE 0 619 #define SDM_COMP_TYPE_WAKE_THREAD 1 620 #define SDM_COMP_TYPE_AGG_INT 2 621 #define SDM_COMP_TYPE_CM 3 622 #define SDM_COMP_TYPE_LOADER 4 623 #define SDM_COMP_TYPE_PXP 5 624 #define SDM_COMP_TYPE_INDICATE_ERROR 6 625 #define SDM_COMP_TYPE_RELEASE_THREAD 7 626 #define SDM_COMP_TYPE_RAM 8 627 628 /******************/ 629 /* PBF CONSTANTS */ 630 /******************/ 631 632 /* Number of PBF command queue lines. Each line is 32B. */ 633 #define PBF_MAX_CMD_LINES 3328 634 635 /* Number of BTB blocks. Each block is 256B. */ 636 #define BTB_MAX_BLOCKS 1440 637 638 /*****************/ 639 /* PRS CONSTANTS */ 640 /*****************/ 641 642 #define PRS_GFT_CAM_LINES_NO_MATCH 31 643 644 /* Async data KCQ CQE */ 645 struct async_data { 646 __le32 cid; 647 __le16 itid; 648 u8 error_code; 649 u8 fw_debug_param; 650 }; 651 652 struct coalescing_timeset { 653 u8 value; 654 #define COALESCING_TIMESET_TIMESET_MASK 0x7F 655 #define COALESCING_TIMESET_TIMESET_SHIFT 0 656 #define COALESCING_TIMESET_VALID_MASK 0x1 657 #define COALESCING_TIMESET_VALID_SHIFT 7 658 }; 659 660 struct common_queue_zone { 661 __le16 ring_drv_data_consumer; 662 __le16 reserved; 663 }; 664 665 struct eth_rx_prod_data { 666 __le16 bd_prod; 667 __le16 cqe_prod; 668 }; 669 670 struct regpair { 671 __le32 lo; 672 __le32 hi; 673 }; 674 675 struct vf_pf_channel_eqe_data { 676 struct regpair msg_addr; 677 }; 678 679 struct iscsi_eqe_data { 680 __le32 cid; 681 __le16 conn_id; 682 u8 error_code; 683 u8 error_pdu_opcode_reserved; 684 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK 0x3F 685 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_SHIFT 0 686 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_MASK 0x1 687 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_SHIFT 6 688 #define ISCSI_EQE_DATA_RESERVED0_MASK 0x1 689 #define ISCSI_EQE_DATA_RESERVED0_SHIFT 7 690 }; 691 692 struct malicious_vf_eqe_data { 693 u8 vf_id; 694 u8 err_id; 695 __le16 reserved[3]; 696 }; 697 698 struct initial_cleanup_eqe_data { 699 u8 vf_id; 700 u8 reserved[7]; 701 }; 702 703 /* Event Data Union */ 704 union event_ring_data { 705 u8 bytes[8]; 706 struct vf_pf_channel_eqe_data vf_pf_channel; 707 struct iscsi_eqe_data iscsi_info; 708 struct malicious_vf_eqe_data malicious_vf; 709 struct initial_cleanup_eqe_data vf_init_cleanup; 710 struct regpair roce_handle; 711 }; 712 713 /* Event Ring Entry */ 714 struct event_ring_entry { 715 u8 protocol_id; 716 u8 opcode; 717 __le16 reserved0; 718 __le16 echo; 719 u8 fw_return_code; 720 u8 flags; 721 #define EVENT_RING_ENTRY_ASYNC_MASK 0x1 722 #define EVENT_RING_ENTRY_ASYNC_SHIFT 0 723 #define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F 724 #define EVENT_RING_ENTRY_RESERVED1_SHIFT 1 725 union event_ring_data data; 726 }; 727 728 /* Multi function mode */ 729 enum mf_mode { 730 ERROR_MODE /* Unsupported mode */, 731 MF_OVLAN, 732 MF_NPAR, 733 MAX_MF_MODE 734 }; 735 736 /* Per-protocol connection types */ 737 enum protocol_type { 738 PROTOCOLID_ISCSI, 739 PROTOCOLID_FCOE, 740 PROTOCOLID_ROCE, 741 PROTOCOLID_CORE, 742 PROTOCOLID_ETH, 743 PROTOCOLID_RESERVED4, 744 PROTOCOLID_RESERVED5, 745 PROTOCOLID_PREROCE, 746 PROTOCOLID_COMMON, 747 PROTOCOLID_RESERVED6, 748 MAX_PROTOCOL_TYPE 749 }; 750 751 struct ustorm_eth_queue_zone { 752 struct coalescing_timeset int_coalescing_timeset; 753 u8 reserved[3]; 754 }; 755 756 struct ustorm_queue_zone { 757 struct ustorm_eth_queue_zone eth; 758 struct common_queue_zone common; 759 }; 760 761 /* status block structure */ 762 struct cau_pi_entry { 763 u32 prod; 764 #define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF 765 #define CAU_PI_ENTRY_PROD_VAL_SHIFT 0 766 #define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F 767 #define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16 768 #define CAU_PI_ENTRY_FSM_SEL_MASK 0x1 769 #define CAU_PI_ENTRY_FSM_SEL_SHIFT 23 770 #define CAU_PI_ENTRY_RESERVED_MASK 0xFF 771 #define CAU_PI_ENTRY_RESERVED_SHIFT 24 772 }; 773 774 /* status block structure */ 775 struct cau_sb_entry { 776 u32 data; 777 #define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF 778 #define CAU_SB_ENTRY_SB_PROD_SHIFT 0 779 #define CAU_SB_ENTRY_STATE0_MASK 0xF 780 #define CAU_SB_ENTRY_STATE0_SHIFT 24 781 #define CAU_SB_ENTRY_STATE1_MASK 0xF 782 #define CAU_SB_ENTRY_STATE1_SHIFT 28 783 u32 params; 784 #define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F 785 #define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0 786 #define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F 787 #define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7 788 #define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3 789 #define CAU_SB_ENTRY_TIMER_RES0_SHIFT 14 790 #define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3 791 #define CAU_SB_ENTRY_TIMER_RES1_SHIFT 16 792 #define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF 793 #define CAU_SB_ENTRY_VF_NUMBER_SHIFT 18 794 #define CAU_SB_ENTRY_VF_VALID_MASK 0x1 795 #define CAU_SB_ENTRY_VF_VALID_SHIFT 26 796 #define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF 797 #define CAU_SB_ENTRY_PF_NUMBER_SHIFT 27 798 #define CAU_SB_ENTRY_TPH_MASK 0x1 799 #define CAU_SB_ENTRY_TPH_SHIFT 31 800 }; 801 802 /* core doorbell data */ 803 struct core_db_data { 804 u8 params; 805 #define CORE_DB_DATA_DEST_MASK 0x3 806 #define CORE_DB_DATA_DEST_SHIFT 0 807 #define CORE_DB_DATA_AGG_CMD_MASK 0x3 808 #define CORE_DB_DATA_AGG_CMD_SHIFT 2 809 #define CORE_DB_DATA_BYPASS_EN_MASK 0x1 810 #define CORE_DB_DATA_BYPASS_EN_SHIFT 4 811 #define CORE_DB_DATA_RESERVED_MASK 0x1 812 #define CORE_DB_DATA_RESERVED_SHIFT 5 813 #define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3 814 #define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6 815 u8 agg_flags; 816 __le16 spq_prod; 817 }; 818 819 /* Enum of doorbell aggregative command selection */ 820 enum db_agg_cmd_sel { 821 DB_AGG_CMD_NOP, 822 DB_AGG_CMD_SET, 823 DB_AGG_CMD_ADD, 824 DB_AGG_CMD_MAX, 825 MAX_DB_AGG_CMD_SEL 826 }; 827 828 /* Enum of doorbell destination */ 829 enum db_dest { 830 DB_DEST_XCM, 831 DB_DEST_UCM, 832 DB_DEST_TCM, 833 DB_NUM_DESTINATIONS, 834 MAX_DB_DEST 835 }; 836 837 /* Enum of doorbell DPM types */ 838 enum db_dpm_type { 839 DPM_LEGACY, 840 DPM_ROCE, 841 DPM_L2_INLINE, 842 DPM_L2_BD, 843 MAX_DB_DPM_TYPE 844 }; 845 846 /* Structure for doorbell data, in L2 DPM mode, for 1st db in a DPM burst */ 847 struct db_l2_dpm_data { 848 __le16 icid; 849 __le16 bd_prod; 850 __le32 params; 851 #define DB_L2_DPM_DATA_SIZE_MASK 0x3F 852 #define DB_L2_DPM_DATA_SIZE_SHIFT 0 853 #define DB_L2_DPM_DATA_DPM_TYPE_MASK 0x3 854 #define DB_L2_DPM_DATA_DPM_TYPE_SHIFT 6 855 #define DB_L2_DPM_DATA_NUM_BDS_MASK 0xFF 856 #define DB_L2_DPM_DATA_NUM_BDS_SHIFT 8 857 #define DB_L2_DPM_DATA_PKT_SIZE_MASK 0x7FF 858 #define DB_L2_DPM_DATA_PKT_SIZE_SHIFT 16 859 #define DB_L2_DPM_DATA_RESERVED0_MASK 0x1 860 #define DB_L2_DPM_DATA_RESERVED0_SHIFT 27 861 #define DB_L2_DPM_DATA_SGE_NUM_MASK 0x7 862 #define DB_L2_DPM_DATA_SGE_NUM_SHIFT 28 863 #define DB_L2_DPM_DATA_RESERVED1_MASK 0x1 864 #define DB_L2_DPM_DATA_RESERVED1_SHIFT 31 865 }; 866 867 /* Structure for SGE in a DPM doorbell of type DPM_L2_BD */ 868 struct db_l2_dpm_sge { 869 struct regpair addr; 870 __le16 nbytes; 871 __le16 bitfields; 872 #define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF 873 #define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0 874 #define DB_L2_DPM_SGE_RESERVED0_MASK 0x3 875 #define DB_L2_DPM_SGE_RESERVED0_SHIFT 9 876 #define DB_L2_DPM_SGE_ST_VALID_MASK 0x1 877 #define DB_L2_DPM_SGE_ST_VALID_SHIFT 11 878 #define DB_L2_DPM_SGE_RESERVED1_MASK 0xF 879 #define DB_L2_DPM_SGE_RESERVED1_SHIFT 12 880 __le32 reserved2; 881 }; 882 883 /* Structure for doorbell address, in legacy mode */ 884 struct db_legacy_addr { 885 __le32 addr; 886 #define DB_LEGACY_ADDR_RESERVED0_MASK 0x3 887 #define DB_LEGACY_ADDR_RESERVED0_SHIFT 0 888 #define DB_LEGACY_ADDR_DEMS_MASK 0x7 889 #define DB_LEGACY_ADDR_DEMS_SHIFT 2 890 #define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF 891 #define DB_LEGACY_ADDR_ICID_SHIFT 5 892 }; 893 894 /* Structure for doorbell address, in PWM mode */ 895 struct db_pwm_addr { 896 __le32 addr; 897 #define DB_PWM_ADDR_RESERVED0_MASK 0x7 898 #define DB_PWM_ADDR_RESERVED0_SHIFT 0 899 #define DB_PWM_ADDR_OFFSET_MASK 0x7F 900 #define DB_PWM_ADDR_OFFSET_SHIFT 3 901 #define DB_PWM_ADDR_WID_MASK 0x3 902 #define DB_PWM_ADDR_WID_SHIFT 10 903 #define DB_PWM_ADDR_DPI_MASK 0xFFFF 904 #define DB_PWM_ADDR_DPI_SHIFT 12 905 #define DB_PWM_ADDR_RESERVED1_MASK 0xF 906 #define DB_PWM_ADDR_RESERVED1_SHIFT 28 907 }; 908 909 /* Parameters to RoCE firmware, passed in EDPM doorbell */ 910 struct db_roce_dpm_params { 911 __le32 params; 912 #define DB_ROCE_DPM_PARAMS_SIZE_MASK 0x3F 913 #define DB_ROCE_DPM_PARAMS_SIZE_SHIFT 0 914 #define DB_ROCE_DPM_PARAMS_DPM_TYPE_MASK 0x3 915 #define DB_ROCE_DPM_PARAMS_DPM_TYPE_SHIFT 6 916 #define DB_ROCE_DPM_PARAMS_OPCODE_MASK 0xFF 917 #define DB_ROCE_DPM_PARAMS_OPCODE_SHIFT 8 918 #define DB_ROCE_DPM_PARAMS_WQE_SIZE_MASK 0x7FF 919 #define DB_ROCE_DPM_PARAMS_WQE_SIZE_SHIFT 16 920 #define DB_ROCE_DPM_PARAMS_RESERVED0_MASK 0x1 921 #define DB_ROCE_DPM_PARAMS_RESERVED0_SHIFT 27 922 #define DB_ROCE_DPM_PARAMS_COMPLETION_FLG_MASK 0x1 923 #define DB_ROCE_DPM_PARAMS_COMPLETION_FLG_SHIFT 28 924 #define DB_ROCE_DPM_PARAMS_S_FLG_MASK 0x1 925 #define DB_ROCE_DPM_PARAMS_S_FLG_SHIFT 29 926 #define DB_ROCE_DPM_PARAMS_RESERVED1_MASK 0x3 927 #define DB_ROCE_DPM_PARAMS_RESERVED1_SHIFT 30 928 }; 929 930 /* Structure for doorbell data, in ROCE DPM mode, for 1st db in a DPM burst */ 931 struct db_roce_dpm_data { 932 __le16 icid; 933 __le16 prod_val; 934 struct db_roce_dpm_params params; 935 }; 936 937 /* Igu interrupt command */ 938 enum igu_int_cmd { 939 IGU_INT_ENABLE = 0, 940 IGU_INT_DISABLE = 1, 941 IGU_INT_NOP = 2, 942 IGU_INT_NOP2 = 3, 943 MAX_IGU_INT_CMD 944 }; 945 946 /* IGU producer or consumer update command */ 947 struct igu_prod_cons_update { 948 u32 sb_id_and_flags; 949 #define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF 950 #define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0 951 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1 952 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT 24 953 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3 954 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT 25 955 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1 956 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27 957 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1 958 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT 28 959 #define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3 960 #define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT 29 961 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1 962 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT 31 963 u32 reserved1; 964 }; 965 966 /* Igu segments access for default status block only */ 967 enum igu_seg_access { 968 IGU_SEG_ACCESS_REG = 0, 969 IGU_SEG_ACCESS_ATTN = 1, 970 MAX_IGU_SEG_ACCESS 971 }; 972 973 struct parsing_and_err_flags { 974 __le16 flags; 975 #define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3 976 #define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0 977 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3 978 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2 979 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1 980 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4 981 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1 982 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5 983 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1 984 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6 985 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1 986 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7 987 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1 988 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT 8 989 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1 990 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT 9 991 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1 992 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10 993 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1 994 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11 995 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1 996 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12 997 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1 998 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13 999 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1 1000 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14 1001 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1 1002 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15 1003 }; 1004 1005 struct pb_context { 1006 __le32 crc[4]; 1007 }; 1008 1009 struct pxp_concrete_fid { 1010 __le16 fid; 1011 #define PXP_CONCRETE_FID_PFID_MASK 0xF 1012 #define PXP_CONCRETE_FID_PFID_SHIFT 0 1013 #define PXP_CONCRETE_FID_PORT_MASK 0x3 1014 #define PXP_CONCRETE_FID_PORT_SHIFT 4 1015 #define PXP_CONCRETE_FID_PATH_MASK 0x1 1016 #define PXP_CONCRETE_FID_PATH_SHIFT 6 1017 #define PXP_CONCRETE_FID_VFVALID_MASK 0x1 1018 #define PXP_CONCRETE_FID_VFVALID_SHIFT 7 1019 #define PXP_CONCRETE_FID_VFID_MASK 0xFF 1020 #define PXP_CONCRETE_FID_VFID_SHIFT 8 1021 }; 1022 1023 struct pxp_pretend_concrete_fid { 1024 __le16 fid; 1025 #define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF 1026 #define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0 1027 #define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7 1028 #define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4 1029 #define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1 1030 #define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT 7 1031 #define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF 1032 #define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8 1033 }; 1034 1035 union pxp_pretend_fid { 1036 struct pxp_pretend_concrete_fid concrete_fid; 1037 __le16 opaque_fid; 1038 }; 1039 1040 /* Pxp Pretend Command Register. */ 1041 struct pxp_pretend_cmd { 1042 union pxp_pretend_fid fid; 1043 __le16 control; 1044 #define PXP_PRETEND_CMD_PATH_MASK 0x1 1045 #define PXP_PRETEND_CMD_PATH_SHIFT 0 1046 #define PXP_PRETEND_CMD_USE_PORT_MASK 0x1 1047 #define PXP_PRETEND_CMD_USE_PORT_SHIFT 1 1048 #define PXP_PRETEND_CMD_PORT_MASK 0x3 1049 #define PXP_PRETEND_CMD_PORT_SHIFT 2 1050 #define PXP_PRETEND_CMD_RESERVED0_MASK 0xF 1051 #define PXP_PRETEND_CMD_RESERVED0_SHIFT 4 1052 #define PXP_PRETEND_CMD_RESERVED1_MASK 0xF 1053 #define PXP_PRETEND_CMD_RESERVED1_SHIFT 8 1054 #define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1 1055 #define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT 12 1056 #define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1 1057 #define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT 13 1058 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1 1059 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14 1060 #define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1 1061 #define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15 1062 }; 1063 1064 /* PTT Record in PXP Admin Window. */ 1065 struct pxp_ptt_entry { 1066 __le32 offset; 1067 #define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF 1068 #define PXP_PTT_ENTRY_OFFSET_SHIFT 0 1069 #define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF 1070 #define PXP_PTT_ENTRY_RESERVED0_SHIFT 23 1071 struct pxp_pretend_cmd pretend; 1072 }; 1073 1074 /* VF Zone A Permission Register. */ 1075 struct pxp_vf_zone_a_permission { 1076 __le32 control; 1077 #define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF 1078 #define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0 1079 #define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1 1080 #define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT 8 1081 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F 1082 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT 9 1083 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF 1084 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16 1085 }; 1086 1087 /* RSS hash type */ 1088 struct rdif_task_context { 1089 __le32 initial_ref_tag; 1090 __le16 app_tag_value; 1091 __le16 app_tag_mask; 1092 u8 flags0; 1093 #define RDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1 1094 #define RDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0 1095 #define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1 1096 #define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1 1097 #define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1 1098 #define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2 1099 #define RDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1 1100 #define RDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3 1101 #define RDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3 1102 #define RDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4 1103 #define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 1104 #define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 1105 #define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1 1106 #define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 7 1107 u8 partial_dif_data[7]; 1108 __le16 partial_crc_value; 1109 __le16 partial_checksum_value; 1110 __le32 offset_in_io; 1111 __le16 flags1; 1112 #define RDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1 1113 #define RDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0 1114 #define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1 1115 #define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1 1116 #define RDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1 1117 #define RDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2 1118 #define RDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1 1119 #define RDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3 1120 #define RDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1 1121 #define RDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4 1122 #define RDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1 1123 #define RDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5 1124 #define RDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7 1125 #define RDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6 1126 #define RDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3 1127 #define RDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9 1128 #define RDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1 1129 #define RDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11 1130 #define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1 1131 #define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12 1132 #define RDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1 1133 #define RDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13 1134 #define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1 1135 #define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 14 1136 #define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1 1137 #define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 15 1138 __le16 state; 1139 #define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_MASK 0xF 1140 #define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_SHIFT 0 1141 #define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_MASK 0xF 1142 #define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_SHIFT 4 1143 #define RDIF_TASK_CONTEXT_ERRORINIO_MASK 0x1 1144 #define RDIF_TASK_CONTEXT_ERRORINIO_SHIFT 8 1145 #define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1 1146 #define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9 1147 #define RDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF 1148 #define RDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 10 1149 #define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3 1150 #define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14 1151 __le32 reserved2; 1152 }; 1153 1154 /* RSS hash type */ 1155 enum rss_hash_type { 1156 RSS_HASH_TYPE_DEFAULT = 0, 1157 RSS_HASH_TYPE_IPV4 = 1, 1158 RSS_HASH_TYPE_TCP_IPV4 = 2, 1159 RSS_HASH_TYPE_IPV6 = 3, 1160 RSS_HASH_TYPE_TCP_IPV6 = 4, 1161 RSS_HASH_TYPE_UDP_IPV4 = 5, 1162 RSS_HASH_TYPE_UDP_IPV6 = 6, 1163 MAX_RSS_HASH_TYPE 1164 }; 1165 1166 /* status block structure */ 1167 struct status_block { 1168 __le16 pi_array[PIS_PER_SB]; 1169 __le32 sb_num; 1170 #define STATUS_BLOCK_SB_NUM_MASK 0x1FF 1171 #define STATUS_BLOCK_SB_NUM_SHIFT 0 1172 #define STATUS_BLOCK_ZERO_PAD_MASK 0x7F 1173 #define STATUS_BLOCK_ZERO_PAD_SHIFT 9 1174 #define STATUS_BLOCK_ZERO_PAD2_MASK 0xFFFF 1175 #define STATUS_BLOCK_ZERO_PAD2_SHIFT 16 1176 __le32 prod_index; 1177 #define STATUS_BLOCK_PROD_INDEX_MASK 0xFFFFFF 1178 #define STATUS_BLOCK_PROD_INDEX_SHIFT 0 1179 #define STATUS_BLOCK_ZERO_PAD3_MASK 0xFF 1180 #define STATUS_BLOCK_ZERO_PAD3_SHIFT 24 1181 }; 1182 1183 struct tdif_task_context { 1184 __le32 initial_ref_tag; 1185 __le16 app_tag_value; 1186 __le16 app_tag_mask; 1187 __le16 partial_crc_valueB; 1188 __le16 partial_checksum_valueB; 1189 __le16 stateB; 1190 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_MASK 0xF 1191 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_SHIFT 0 1192 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_MASK 0xF 1193 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_SHIFT 4 1194 #define TDIF_TASK_CONTEXT_ERRORINIOB_MASK 0x1 1195 #define TDIF_TASK_CONTEXT_ERRORINIOB_SHIFT 8 1196 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1 1197 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9 1198 #define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F 1199 #define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10 1200 u8 reserved1; 1201 u8 flags0; 1202 #define TDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1 1203 #define TDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0 1204 #define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1 1205 #define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1 1206 #define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1 1207 #define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2 1208 #define TDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1 1209 #define TDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3 1210 #define TDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3 1211 #define TDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4 1212 #define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 1213 #define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 1214 #define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1 1215 #define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7 1216 __le32 flags1; 1217 #define TDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1 1218 #define TDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0 1219 #define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1 1220 #define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1 1221 #define TDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1 1222 #define TDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2 1223 #define TDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1 1224 #define TDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3 1225 #define TDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1 1226 #define TDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4 1227 #define TDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1 1228 #define TDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5 1229 #define TDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7 1230 #define TDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6 1231 #define TDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3 1232 #define TDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9 1233 #define TDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1 1234 #define TDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11 1235 #define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1 1236 #define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12 1237 #define TDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1 1238 #define TDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13 1239 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_MASK 0xF 1240 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_SHIFT 14 1241 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_MASK 0xF 1242 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_SHIFT 18 1243 #define TDIF_TASK_CONTEXT_ERRORINIOA_MASK 0x1 1244 #define TDIF_TASK_CONTEXT_ERRORINIOA_SHIFT 22 1245 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_MASK 0x1 1246 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_SHIFT 23 1247 #define TDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF 1248 #define TDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 24 1249 #define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1 1250 #define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 28 1251 #define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1 1252 #define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 29 1253 #define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1 1254 #define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 30 1255 #define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1 1256 #define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31 1257 __le32 offset_in_iob; 1258 __le16 partial_crc_value_a; 1259 __le16 partial_checksum_valuea_; 1260 __le32 offset_in_ioa; 1261 u8 partial_dif_data_a[8]; 1262 u8 partial_dif_data_b[8]; 1263 }; 1264 1265 struct timers_context { 1266 __le32 logical_client_0; 1267 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0xFFFFFFF 1268 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT 0 1269 #define TIMERS_CONTEXT_VALIDLC0_MASK 0x1 1270 #define TIMERS_CONTEXT_VALIDLC0_SHIFT 28 1271 #define TIMERS_CONTEXT_ACTIVELC0_MASK 0x1 1272 #define TIMERS_CONTEXT_ACTIVELC0_SHIFT 29 1273 #define TIMERS_CONTEXT_RESERVED0_MASK 0x3 1274 #define TIMERS_CONTEXT_RESERVED0_SHIFT 30 1275 __le32 logical_client_1; 1276 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK 0xFFFFFFF 1277 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT 0 1278 #define TIMERS_CONTEXT_VALIDLC1_MASK 0x1 1279 #define TIMERS_CONTEXT_VALIDLC1_SHIFT 28 1280 #define TIMERS_CONTEXT_ACTIVELC1_MASK 0x1 1281 #define TIMERS_CONTEXT_ACTIVELC1_SHIFT 29 1282 #define TIMERS_CONTEXT_RESERVED1_MASK 0x3 1283 #define TIMERS_CONTEXT_RESERVED1_SHIFT 30 1284 __le32 logical_client_2; 1285 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK 0xFFFFFFF 1286 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT 0 1287 #define TIMERS_CONTEXT_VALIDLC2_MASK 0x1 1288 #define TIMERS_CONTEXT_VALIDLC2_SHIFT 28 1289 #define TIMERS_CONTEXT_ACTIVELC2_MASK 0x1 1290 #define TIMERS_CONTEXT_ACTIVELC2_SHIFT 29 1291 #define TIMERS_CONTEXT_RESERVED2_MASK 0x3 1292 #define TIMERS_CONTEXT_RESERVED2_SHIFT 30 1293 __le32 host_expiration_fields; 1294 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_MASK 0xFFFFFFF 1295 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_SHIFT 0 1296 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_MASK 0x1 1297 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_SHIFT 28 1298 #define TIMERS_CONTEXT_RESERVED3_MASK 0x7 1299 #define TIMERS_CONTEXT_RESERVED3_SHIFT 29 1300 }; 1301 #endif /* __COMMON_HSI__ */ 1302 #endif 1303