1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015 QLogic Corporation 3 * 4 * This software is available under the terms of the GNU General Public License 5 * (GPL) Version 2, available from the file COPYING in the main directory of 6 * this source tree. 7 */ 8 #ifndef _COMMON_HSI_H 9 #define _COMMON_HSI_H 10 #include <linux/types.h> 11 #include <asm/byteorder.h> 12 #include <linux/bitops.h> 13 #include <linux/slab.h> 14 15 /* dma_addr_t manip */ 16 #define DMA_LO_LE(x) cpu_to_le32(lower_32_bits(x)) 17 #define DMA_HI_LE(x) cpu_to_le32(upper_32_bits(x)) 18 #define DMA_REGPAIR_LE(x, val) do { \ 19 (x).hi = DMA_HI_LE((val)); \ 20 (x).lo = DMA_LO_LE((val)); \ 21 } while (0) 22 23 #define HILO_GEN(hi, lo, type) ((((type)(hi)) << 32) + (lo)) 24 #define HILO_64(hi, lo) HILO_GEN((le32_to_cpu(hi)), (le32_to_cpu(lo)), u64) 25 #define HILO_64_REGPAIR(regpair) (HILO_64(regpair.hi, regpair.lo)) 26 #define HILO_DMA_REGPAIR(regpair) ((dma_addr_t)HILO_64_REGPAIR(regpair)) 27 28 #ifndef __COMMON_HSI__ 29 #define __COMMON_HSI__ 30 31 32 #define X_FINAL_CLEANUP_AGG_INT 1 33 34 #define EVENT_RING_PAGE_SIZE_BYTES 4096 35 36 #define NUM_OF_GLOBAL_QUEUES 128 37 #define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64 38 39 #define ISCSI_CDU_TASK_SEG_TYPE 0 40 #define RDMA_CDU_TASK_SEG_TYPE 1 41 42 #define FW_ASSERT_GENERAL_ATTN_IDX 32 43 44 #define MAX_PINNED_CCFC 32 45 46 /* Queue Zone sizes in bytes */ 47 #define TSTORM_QZONE_SIZE 8 48 #define MSTORM_QZONE_SIZE 16 49 #define USTORM_QZONE_SIZE 8 50 #define XSTORM_QZONE_SIZE 8 51 #define YSTORM_QZONE_SIZE 0 52 #define PSTORM_QZONE_SIZE 0 53 54 #define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7 55 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT 16 56 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE 48 57 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD 112 58 59 /********************************/ 60 /* CORE (LIGHT L2) FW CONSTANTS */ 61 /********************************/ 62 63 #define CORE_LL2_MAX_RAMROD_PER_CON 8 64 #define CORE_LL2_TX_BD_PAGE_SIZE_BYTES 4096 65 #define CORE_LL2_RX_BD_PAGE_SIZE_BYTES 4096 66 #define CORE_LL2_RX_CQE_PAGE_SIZE_BYTES 4096 67 #define CORE_LL2_RX_NUM_NEXT_PAGE_BDS 1 68 69 #define CORE_LL2_TX_MAX_BDS_PER_PACKET 12 70 71 #define CORE_SPQE_PAGE_SIZE_BYTES 4096 72 73 #define MAX_NUM_LL2_RX_QUEUES 32 74 #define MAX_NUM_LL2_TX_STATS_COUNTERS 32 75 76 #define FW_MAJOR_VERSION 8 77 #define FW_MINOR_VERSION 10 78 #define FW_REVISION_VERSION 10 79 #define FW_ENGINEERING_VERSION 0 80 81 /***********************/ 82 /* COMMON HW CONSTANTS */ 83 /***********************/ 84 85 /* PCI functions */ 86 #define MAX_NUM_PORTS_K2 (4) 87 #define MAX_NUM_PORTS_BB (2) 88 #define MAX_NUM_PORTS (MAX_NUM_PORTS_K2) 89 90 #define MAX_NUM_PFS_K2 (16) 91 #define MAX_NUM_PFS_BB (8) 92 #define MAX_NUM_PFS (MAX_NUM_PFS_K2) 93 #define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */ 94 95 #define MAX_NUM_VFS_K2 (192) 96 #define MAX_NUM_VFS_BB (120) 97 #define MAX_NUM_VFS (MAX_NUM_VFS_K2) 98 99 #define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB) 100 #define MAX_NUM_FUNCTIONS (MAX_NUM_PFS + MAX_NUM_VFS) 101 102 #define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB) 103 #define MAX_FUNCTION_NUMBER (MAX_NUM_PFS + MAX_NUM_VFS) 104 105 #define MAX_NUM_VPORTS_K2 (208) 106 #define MAX_NUM_VPORTS_BB (160) 107 #define MAX_NUM_VPORTS (MAX_NUM_VPORTS_K2) 108 109 #define MAX_NUM_L2_QUEUES_K2 (320) 110 #define MAX_NUM_L2_QUEUES_BB (256) 111 #define MAX_NUM_L2_QUEUES (MAX_NUM_L2_QUEUES_K2) 112 113 /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */ 114 #define NUM_PHYS_TCS_4PORT_K2 (4) 115 #define NUM_OF_PHYS_TCS (8) 116 117 #define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1) 118 #define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1) 119 120 #define LB_TC (NUM_OF_PHYS_TCS) 121 122 /* Num of possible traffic priority values */ 123 #define NUM_OF_PRIO (8) 124 125 #define MAX_NUM_VOQS_K2 (NUM_TCS_4PORT_K2 * MAX_NUM_PORTS_K2) 126 #define MAX_NUM_VOQS_BB (NUM_OF_TCS * MAX_NUM_PORTS_BB) 127 #define MAX_NUM_VOQS (MAX_NUM_VOQS_K2) 128 #define MAX_PHYS_VOQS (NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB) 129 130 /* CIDs */ 131 #define NUM_OF_CONNECTION_TYPES (8) 132 #define NUM_OF_LCIDS (320) 133 #define NUM_OF_LTIDS (320) 134 135 /* Clock values */ 136 #define MASTER_CLK_FREQ_E4 (375e6) 137 #define STORM_CLK_FREQ_E4 (1000e6) 138 #define CLK25M_CLK_FREQ_E4 (25e6) 139 140 /* Global PXP windows (GTT) */ 141 #define NUM_OF_GTT 19 142 #define GTT_DWORD_SIZE_BITS 10 143 #define GTT_BYTE_SIZE_BITS (GTT_DWORD_SIZE_BITS + 2) 144 #define GTT_DWORD_SIZE BIT(GTT_DWORD_SIZE_BITS) 145 146 /* Tools Version */ 147 #define TOOLS_VERSION 10 148 149 /*****************/ 150 /* CDU CONSTANTS */ 151 /*****************/ 152 153 #define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17) 154 #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff) 155 156 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12) 157 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff) 158 /*****************/ 159 /* DQ CONSTANTS */ 160 /*****************/ 161 162 /* DEMS */ 163 #define DQ_DEMS_LEGACY 0 164 165 /* XCM agg val selection */ 166 #define DQ_XCM_AGG_VAL_SEL_WORD2 0 167 #define DQ_XCM_AGG_VAL_SEL_WORD3 1 168 #define DQ_XCM_AGG_VAL_SEL_WORD4 2 169 #define DQ_XCM_AGG_VAL_SEL_WORD5 3 170 #define DQ_XCM_AGG_VAL_SEL_REG3 4 171 #define DQ_XCM_AGG_VAL_SEL_REG4 5 172 #define DQ_XCM_AGG_VAL_SEL_REG5 6 173 #define DQ_XCM_AGG_VAL_SEL_REG6 7 174 175 /* XCM agg val selection */ 176 #define DQ_XCM_CORE_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 177 #define DQ_XCM_CORE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 178 #define DQ_XCM_CORE_SPQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 179 #define DQ_XCM_ETH_EDPM_NUM_BDS_CMD DQ_XCM_AGG_VAL_SEL_WORD2 180 #define DQ_XCM_ETH_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 181 #define DQ_XCM_ETH_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 182 #define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5 183 #define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 184 #define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 185 #define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 186 #define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6 187 #define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 188 189 /* UCM agg val selection (HW) */ 190 #define DQ_UCM_AGG_VAL_SEL_WORD0 0 191 #define DQ_UCM_AGG_VAL_SEL_WORD1 1 192 #define DQ_UCM_AGG_VAL_SEL_WORD2 2 193 #define DQ_UCM_AGG_VAL_SEL_WORD3 3 194 #define DQ_UCM_AGG_VAL_SEL_REG0 4 195 #define DQ_UCM_AGG_VAL_SEL_REG1 5 196 #define DQ_UCM_AGG_VAL_SEL_REG2 6 197 #define DQ_UCM_AGG_VAL_SEL_REG3 7 198 199 /* UCM agg val selection (FW) */ 200 #define DQ_UCM_ETH_PMD_TX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD2 201 #define DQ_UCM_ETH_PMD_RX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD3 202 #define DQ_UCM_ROCE_CQ_CONS_CMD DQ_UCM_AGG_VAL_SEL_REG0 203 #define DQ_UCM_ROCE_CQ_PROD_CMD DQ_UCM_AGG_VAL_SEL_REG2 204 205 /* TCM agg val selection (HW) */ 206 #define DQ_TCM_AGG_VAL_SEL_WORD0 0 207 #define DQ_TCM_AGG_VAL_SEL_WORD1 1 208 #define DQ_TCM_AGG_VAL_SEL_WORD2 2 209 #define DQ_TCM_AGG_VAL_SEL_WORD3 3 210 #define DQ_TCM_AGG_VAL_SEL_REG1 4 211 #define DQ_TCM_AGG_VAL_SEL_REG2 5 212 #define DQ_TCM_AGG_VAL_SEL_REG6 6 213 #define DQ_TCM_AGG_VAL_SEL_REG9 7 214 215 /* TCM agg val selection (FW) */ 216 #define DQ_TCM_L2B_BD_PROD_CMD \ 217 DQ_TCM_AGG_VAL_SEL_WORD1 218 #define DQ_TCM_ROCE_RQ_PROD_CMD \ 219 DQ_TCM_AGG_VAL_SEL_WORD0 220 221 /* XCM agg counter flag selection */ 222 #define DQ_XCM_AGG_FLG_SHIFT_BIT14 0 223 #define DQ_XCM_AGG_FLG_SHIFT_BIT15 1 224 #define DQ_XCM_AGG_FLG_SHIFT_CF12 2 225 #define DQ_XCM_AGG_FLG_SHIFT_CF13 3 226 #define DQ_XCM_AGG_FLG_SHIFT_CF18 4 227 #define DQ_XCM_AGG_FLG_SHIFT_CF19 5 228 #define DQ_XCM_AGG_FLG_SHIFT_CF22 6 229 #define DQ_XCM_AGG_FLG_SHIFT_CF23 7 230 231 /* XCM agg counter flag selection */ 232 #define DQ_XCM_CORE_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18) 233 #define DQ_XCM_CORE_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19) 234 #define DQ_XCM_CORE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) 235 #define DQ_XCM_ETH_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18) 236 #define DQ_XCM_ETH_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19) 237 #define DQ_XCM_ETH_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) 238 #define DQ_XCM_ETH_TPH_EN_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23) 239 #define DQ_XCM_ISCSI_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19) 240 #define DQ_XCM_ISCSI_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) 241 #define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23) 242 243 /* UCM agg counter flag selection (HW) */ 244 #define DQ_UCM_AGG_FLG_SHIFT_CF0 0 245 #define DQ_UCM_AGG_FLG_SHIFT_CF1 1 246 #define DQ_UCM_AGG_FLG_SHIFT_CF3 2 247 #define DQ_UCM_AGG_FLG_SHIFT_CF4 3 248 #define DQ_UCM_AGG_FLG_SHIFT_CF5 4 249 #define DQ_UCM_AGG_FLG_SHIFT_CF6 5 250 #define DQ_UCM_AGG_FLG_SHIFT_RULE0EN 6 251 #define DQ_UCM_AGG_FLG_SHIFT_RULE1EN 7 252 253 /* UCM agg counter flag selection (FW) */ 254 #define DQ_UCM_ETH_PMD_TX_ARM_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF4) 255 #define DQ_UCM_ETH_PMD_RX_ARM_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF5) 256 #define DQ_UCM_ROCE_CQ_ARM_SE_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF4) 257 #define DQ_UCM_ROCE_CQ_ARM_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF5) 258 259 /* TCM agg counter flag selection (HW) */ 260 #define DQ_TCM_AGG_FLG_SHIFT_CF0 0 261 #define DQ_TCM_AGG_FLG_SHIFT_CF1 1 262 #define DQ_TCM_AGG_FLG_SHIFT_CF2 2 263 #define DQ_TCM_AGG_FLG_SHIFT_CF3 3 264 #define DQ_TCM_AGG_FLG_SHIFT_CF4 4 265 #define DQ_TCM_AGG_FLG_SHIFT_CF5 5 266 #define DQ_TCM_AGG_FLG_SHIFT_CF6 6 267 #define DQ_TCM_AGG_FLG_SHIFT_CF7 7 268 /* TCM agg counter flag selection (FW) */ 269 #define DQ_TCM_ISCSI_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1) 270 #define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3) 271 272 /* PWM address mapping */ 273 #define DQ_PWM_OFFSET_DPM_BASE 0x0 274 #define DQ_PWM_OFFSET_DPM_END 0x27 275 #define DQ_PWM_OFFSET_XCM16_BASE 0x40 276 #define DQ_PWM_OFFSET_XCM32_BASE 0x44 277 #define DQ_PWM_OFFSET_UCM16_BASE 0x48 278 #define DQ_PWM_OFFSET_UCM32_BASE 0x4C 279 #define DQ_PWM_OFFSET_UCM16_4 0x50 280 #define DQ_PWM_OFFSET_TCM16_BASE 0x58 281 #define DQ_PWM_OFFSET_TCM32_BASE 0x5C 282 #define DQ_PWM_OFFSET_XCM_FLAGS 0x68 283 #define DQ_PWM_OFFSET_UCM_FLAGS 0x69 284 #define DQ_PWM_OFFSET_TCM_FLAGS 0x6B 285 286 #define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD (DQ_PWM_OFFSET_XCM16_BASE + 2) 287 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT (DQ_PWM_OFFSET_UCM32_BASE) 288 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_16BIT (DQ_PWM_OFFSET_UCM16_4) 289 #define DQ_PWM_OFFSET_UCM_RDMA_INT_TIMEOUT (DQ_PWM_OFFSET_UCM16_BASE + 2) 290 #define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS (DQ_PWM_OFFSET_UCM_FLAGS) 291 #define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 1) 292 #define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 3) 293 #define DQ_REGION_SHIFT (12) 294 295 /* DPM */ 296 #define DQ_DPM_WQE_BUFF_SIZE (320) 297 298 /* Conn type ranges */ 299 #define DQ_CONN_TYPE_RANGE_SHIFT (4) 300 301 /*****************/ 302 /* QM CONSTANTS */ 303 /*****************/ 304 305 /* number of TX queues in the QM */ 306 #define MAX_QM_TX_QUEUES_K2 512 307 #define MAX_QM_TX_QUEUES_BB 448 308 #define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2 309 310 /* number of Other queues in the QM */ 311 #define MAX_QM_OTHER_QUEUES_BB 64 312 #define MAX_QM_OTHER_QUEUES_K2 128 313 #define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2 314 315 /* number of queues in a PF queue group */ 316 #define QM_PF_QUEUE_GROUP_SIZE 8 317 318 /* the size of a single queue element in bytes */ 319 #define QM_PQ_ELEMENT_SIZE 4 320 321 /* base number of Tx PQs in the CM PQ representation. 322 * should be used when storing PQ IDs in CM PQ registers and context 323 */ 324 #define CM_TX_PQ_BASE 0x200 325 326 /* number of global Vport/QCN rate limiters */ 327 #define MAX_QM_GLOBAL_RLS 256 328 /* QM registers data */ 329 #define QM_LINE_CRD_REG_WIDTH 16 330 #define QM_LINE_CRD_REG_SIGN_BIT BIT((QM_LINE_CRD_REG_WIDTH - 1)) 331 #define QM_BYTE_CRD_REG_WIDTH 24 332 #define QM_BYTE_CRD_REG_SIGN_BIT BIT((QM_BYTE_CRD_REG_WIDTH - 1)) 333 #define QM_WFQ_CRD_REG_WIDTH 32 334 #define QM_WFQ_CRD_REG_SIGN_BIT BIT((QM_WFQ_CRD_REG_WIDTH - 1)) 335 #define QM_RL_CRD_REG_WIDTH 32 336 #define QM_RL_CRD_REG_SIGN_BIT BIT((QM_RL_CRD_REG_WIDTH - 1)) 337 338 /*****************/ 339 /* CAU CONSTANTS */ 340 /*****************/ 341 342 #define CAU_FSM_ETH_RX 0 343 #define CAU_FSM_ETH_TX 1 344 345 /* Number of Protocol Indices per Status Block */ 346 #define PIS_PER_SB 12 347 348 #define CAU_HC_STOPPED_STATE 3 349 #define CAU_HC_DISABLE_STATE 4 350 #define CAU_HC_ENABLE_STATE 0 351 352 /*****************/ 353 /* IGU CONSTANTS */ 354 /*****************/ 355 356 #define MAX_SB_PER_PATH_K2 (368) 357 #define MAX_SB_PER_PATH_BB (288) 358 #define MAX_TOT_SB_PER_PATH \ 359 MAX_SB_PER_PATH_K2 360 361 #define MAX_SB_PER_PF_MIMD 129 362 #define MAX_SB_PER_PF_SIMD 64 363 #define MAX_SB_PER_VF 64 364 365 /* Memory addresses on the BAR for the IGU Sub Block */ 366 #define IGU_MEM_BASE 0x0000 367 368 #define IGU_MEM_MSIX_BASE 0x0000 369 #define IGU_MEM_MSIX_UPPER 0x0101 370 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff 371 372 #define IGU_MEM_PBA_MSIX_BASE 0x0200 373 #define IGU_MEM_PBA_MSIX_UPPER 0x0202 374 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff 375 376 #define IGU_CMD_INT_ACK_BASE 0x0400 377 #define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + \ 378 MAX_TOT_SB_PER_PATH - \ 379 1) 380 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff 381 382 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0 383 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05f1 384 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05f2 385 386 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05f3 387 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05f4 388 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05f5 389 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05f6 390 391 #define IGU_CMD_PROD_UPD_BASE 0x0600 392 #define IGU_CMD_PROD_UPD_UPPER (IGU_CMD_PROD_UPD_BASE +\ 393 MAX_TOT_SB_PER_PATH - \ 394 1) 395 #define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff 396 397 /*****************/ 398 /* PXP CONSTANTS */ 399 /*****************/ 400 401 /* Bars for Blocks */ 402 #define PXP_BAR_GRC 0 403 #define PXP_BAR_TSDM 0 404 #define PXP_BAR_USDM 0 405 #define PXP_BAR_XSDM 0 406 #define PXP_BAR_MSDM 0 407 #define PXP_BAR_YSDM 0 408 #define PXP_BAR_PSDM 0 409 #define PXP_BAR_IGU 0 410 #define PXP_BAR_DQ 1 411 412 /* PTT and GTT */ 413 #define PXP_NUM_PF_WINDOWS 12 414 #define PXP_PER_PF_ENTRY_SIZE 8 415 #define PXP_NUM_GLOBAL_WINDOWS 243 416 #define PXP_GLOBAL_ENTRY_SIZE 4 417 #define PXP_ADMIN_WINDOW_ALLOWED_LENGTH 4 418 #define PXP_PF_WINDOW_ADMIN_START 0 419 #define PXP_PF_WINDOW_ADMIN_LENGTH 0x1000 420 #define PXP_PF_WINDOW_ADMIN_END (PXP_PF_WINDOW_ADMIN_START + \ 421 PXP_PF_WINDOW_ADMIN_LENGTH - 1) 422 #define PXP_PF_WINDOW_ADMIN_PER_PF_START 0 423 #define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH (PXP_NUM_PF_WINDOWS * \ 424 PXP_PER_PF_ENTRY_SIZE) 425 #define PXP_PF_WINDOW_ADMIN_PER_PF_END (PXP_PF_WINDOW_ADMIN_PER_PF_START + \ 426 PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1) 427 #define PXP_PF_WINDOW_ADMIN_GLOBAL_START 0x200 428 #define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH (PXP_NUM_GLOBAL_WINDOWS * \ 429 PXP_GLOBAL_ENTRY_SIZE) 430 #define PXP_PF_WINDOW_ADMIN_GLOBAL_END \ 431 (PXP_PF_WINDOW_ADMIN_GLOBAL_START + \ 432 PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1) 433 #define PXP_PF_GLOBAL_PRETEND_ADDR 0x1f0 434 #define PXP_PF_ME_OPAQUE_MASK_ADDR 0xf4 435 #define PXP_PF_ME_OPAQUE_ADDR 0x1f8 436 #define PXP_PF_ME_CONCRETE_ADDR 0x1fc 437 438 #define PXP_EXTERNAL_BAR_PF_WINDOW_START 0x1000 439 #define PXP_EXTERNAL_BAR_PF_WINDOW_NUM PXP_NUM_PF_WINDOWS 440 #define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE 0x1000 441 #define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH \ 442 (PXP_EXTERNAL_BAR_PF_WINDOW_NUM * \ 443 PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) 444 #define PXP_EXTERNAL_BAR_PF_WINDOW_END \ 445 (PXP_EXTERNAL_BAR_PF_WINDOW_START + \ 446 PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH - 1) 447 448 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START \ 449 (PXP_EXTERNAL_BAR_PF_WINDOW_END + 1) 450 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM PXP_NUM_GLOBAL_WINDOWS 451 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE 0x1000 452 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH \ 453 (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM * \ 454 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE) 455 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END \ 456 (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + \ 457 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1) 458 459 /* PF BAR */ 460 #define PXP_BAR0_START_GRC 0x0000 461 #define PXP_BAR0_GRC_LENGTH 0x1C00000 462 #define PXP_BAR0_END_GRC (PXP_BAR0_START_GRC + \ 463 PXP_BAR0_GRC_LENGTH - 1) 464 465 #define PXP_BAR0_START_IGU 0x1C00000 466 #define PXP_BAR0_IGU_LENGTH 0x10000 467 #define PXP_BAR0_END_IGU (PXP_BAR0_START_IGU + \ 468 PXP_BAR0_IGU_LENGTH - 1) 469 470 #define PXP_BAR0_START_TSDM 0x1C80000 471 #define PXP_BAR0_SDM_LENGTH 0x40000 472 #define PXP_BAR0_SDM_RESERVED_LENGTH 0x40000 473 #define PXP_BAR0_END_TSDM (PXP_BAR0_START_TSDM + \ 474 PXP_BAR0_SDM_LENGTH - 1) 475 476 #define PXP_BAR0_START_MSDM 0x1D00000 477 #define PXP_BAR0_END_MSDM (PXP_BAR0_START_MSDM + \ 478 PXP_BAR0_SDM_LENGTH - 1) 479 480 #define PXP_BAR0_START_USDM 0x1D80000 481 #define PXP_BAR0_END_USDM (PXP_BAR0_START_USDM + \ 482 PXP_BAR0_SDM_LENGTH - 1) 483 484 #define PXP_BAR0_START_XSDM 0x1E00000 485 #define PXP_BAR0_END_XSDM (PXP_BAR0_START_XSDM + \ 486 PXP_BAR0_SDM_LENGTH - 1) 487 488 #define PXP_BAR0_START_YSDM 0x1E80000 489 #define PXP_BAR0_END_YSDM (PXP_BAR0_START_YSDM + \ 490 PXP_BAR0_SDM_LENGTH - 1) 491 492 #define PXP_BAR0_START_PSDM 0x1F00000 493 #define PXP_BAR0_END_PSDM (PXP_BAR0_START_PSDM + \ 494 PXP_BAR0_SDM_LENGTH - 1) 495 496 #define PXP_BAR0_FIRST_INVALID_ADDRESS (PXP_BAR0_END_PSDM + 1) 497 498 /* VF BAR */ 499 #define PXP_VF_BAR0 0 500 501 #define PXP_VF_BAR0_START_GRC 0x3E00 502 #define PXP_VF_BAR0_GRC_LENGTH 0x200 503 #define PXP_VF_BAR0_END_GRC (PXP_VF_BAR0_START_GRC + \ 504 PXP_VF_BAR0_GRC_LENGTH - 1) 505 506 #define PXP_VF_BAR0_START_IGU 0 507 #define PXP_VF_BAR0_IGU_LENGTH 0x3000 508 #define PXP_VF_BAR0_END_IGU (PXP_VF_BAR0_START_IGU + \ 509 PXP_VF_BAR0_IGU_LENGTH - 1) 510 511 #define PXP_VF_BAR0_START_DQ 0x3000 512 #define PXP_VF_BAR0_DQ_LENGTH 0x200 513 #define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0 514 #define PXP_VF_BAR0_ME_OPAQUE_ADDRESS (PXP_VF_BAR0_START_DQ + \ 515 PXP_VF_BAR0_DQ_OPAQUE_OFFSET) 516 #define PXP_VF_BAR0_ME_CONCRETE_ADDRESS (PXP_VF_BAR0_ME_OPAQUE_ADDRESS \ 517 + 4) 518 #define PXP_VF_BAR0_END_DQ (PXP_VF_BAR0_START_DQ + \ 519 PXP_VF_BAR0_DQ_LENGTH - 1) 520 521 #define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200 522 #define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200 523 #define PXP_VF_BAR0_END_TSDM_ZONE_B (PXP_VF_BAR0_START_TSDM_ZONE_B \ 524 + \ 525 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 526 - 1) 527 528 #define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400 529 #define PXP_VF_BAR0_END_MSDM_ZONE_B (PXP_VF_BAR0_START_MSDM_ZONE_B \ 530 + \ 531 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 532 - 1) 533 534 #define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600 535 #define PXP_VF_BAR0_END_USDM_ZONE_B (PXP_VF_BAR0_START_USDM_ZONE_B \ 536 + \ 537 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 538 - 1) 539 540 #define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800 541 #define PXP_VF_BAR0_END_XSDM_ZONE_B (PXP_VF_BAR0_START_XSDM_ZONE_B \ 542 + \ 543 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 544 - 1) 545 546 #define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00 547 #define PXP_VF_BAR0_END_YSDM_ZONE_B (PXP_VF_BAR0_START_YSDM_ZONE_B \ 548 + \ 549 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 550 - 1) 551 552 #define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00 553 #define PXP_VF_BAR0_END_PSDM_ZONE_B (PXP_VF_BAR0_START_PSDM_ZONE_B \ 554 + \ 555 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 556 - 1) 557 558 #define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000 559 #define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000 560 561 #define PXP_VF_BAR0_GRC_WINDOW_LENGTH 32 562 563 #define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12 564 #define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024 565 566 /* ILT Records */ 567 #define PXP_NUM_ILT_RECORDS_BB 7600 568 #define PXP_NUM_ILT_RECORDS_K2 11000 569 #define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2) 570 #define PXP_QUEUES_ZONE_MAX_NUM 320 571 /*****************/ 572 /* PRM CONSTANTS */ 573 /*****************/ 574 #define PRM_DMA_PAD_BYTES_NUM 2 575 /******************/ 576 /* SDMs CONSTANTS */ 577 /******************/ 578 #define SDM_OP_GEN_TRIG_NONE 0 579 #define SDM_OP_GEN_TRIG_WAKE_THREAD 1 580 #define SDM_OP_GEN_TRIG_AGG_INT 2 581 #define SDM_OP_GEN_TRIG_LOADER 4 582 #define SDM_OP_GEN_TRIG_INDICATE_ERROR 6 583 #define SDM_OP_GEN_TRIG_RELEASE_THREAD 7 584 585 #define SDM_COMP_TYPE_NONE 0 586 #define SDM_COMP_TYPE_WAKE_THREAD 1 587 #define SDM_COMP_TYPE_AGG_INT 2 588 #define SDM_COMP_TYPE_CM 3 589 #define SDM_COMP_TYPE_LOADER 4 590 #define SDM_COMP_TYPE_PXP 5 591 #define SDM_COMP_TYPE_INDICATE_ERROR 6 592 #define SDM_COMP_TYPE_RELEASE_THREAD 7 593 #define SDM_COMP_TYPE_RAM 8 594 595 /******************/ 596 /* PBF CONSTANTS */ 597 /******************/ 598 599 /* Number of PBF command queue lines. Each line is 32B. */ 600 #define PBF_MAX_CMD_LINES 3328 601 602 /* Number of BTB blocks. Each block is 256B. */ 603 #define BTB_MAX_BLOCKS 1440 604 605 /*****************/ 606 /* PRS CONSTANTS */ 607 /*****************/ 608 609 #define PRS_GFT_CAM_LINES_NO_MATCH 31 610 611 /* Async data KCQ CQE */ 612 struct async_data { 613 __le32 cid; 614 __le16 itid; 615 u8 error_code; 616 u8 fw_debug_param; 617 }; 618 619 struct coalescing_timeset { 620 u8 value; 621 #define COALESCING_TIMESET_TIMESET_MASK 0x7F 622 #define COALESCING_TIMESET_TIMESET_SHIFT 0 623 #define COALESCING_TIMESET_VALID_MASK 0x1 624 #define COALESCING_TIMESET_VALID_SHIFT 7 625 }; 626 627 struct common_queue_zone { 628 __le16 ring_drv_data_consumer; 629 __le16 reserved; 630 }; 631 632 struct eth_rx_prod_data { 633 __le16 bd_prod; 634 __le16 cqe_prod; 635 }; 636 637 struct regpair { 638 __le32 lo; 639 __le32 hi; 640 }; 641 642 struct vf_pf_channel_eqe_data { 643 struct regpair msg_addr; 644 }; 645 646 struct iscsi_eqe_data { 647 __le32 cid; 648 __le16 conn_id; 649 u8 error_code; 650 u8 error_pdu_opcode_reserved; 651 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK 0x3F 652 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_SHIFT 0 653 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_MASK 0x1 654 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_SHIFT 6 655 #define ISCSI_EQE_DATA_RESERVED0_MASK 0x1 656 #define ISCSI_EQE_DATA_RESERVED0_SHIFT 7 657 }; 658 659 struct malicious_vf_eqe_data { 660 u8 vf_id; 661 u8 err_id; 662 __le16 reserved[3]; 663 }; 664 665 struct initial_cleanup_eqe_data { 666 u8 vf_id; 667 u8 reserved[7]; 668 }; 669 670 /* Event Data Union */ 671 union event_ring_data { 672 u8 bytes[8]; 673 struct vf_pf_channel_eqe_data vf_pf_channel; 674 struct iscsi_eqe_data iscsi_info; 675 struct malicious_vf_eqe_data malicious_vf; 676 struct initial_cleanup_eqe_data vf_init_cleanup; 677 struct regpair roce_handle; 678 }; 679 680 /* Event Ring Entry */ 681 struct event_ring_entry { 682 u8 protocol_id; 683 u8 opcode; 684 __le16 reserved0; 685 __le16 echo; 686 u8 fw_return_code; 687 u8 flags; 688 #define EVENT_RING_ENTRY_ASYNC_MASK 0x1 689 #define EVENT_RING_ENTRY_ASYNC_SHIFT 0 690 #define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F 691 #define EVENT_RING_ENTRY_RESERVED1_SHIFT 1 692 union event_ring_data data; 693 }; 694 695 /* Multi function mode */ 696 enum mf_mode { 697 ERROR_MODE /* Unsupported mode */, 698 MF_OVLAN, 699 MF_NPAR, 700 MAX_MF_MODE 701 }; 702 703 /* Per-protocol connection types */ 704 enum protocol_type { 705 PROTOCOLID_ISCSI, 706 PROTOCOLID_RESERVED2, 707 PROTOCOLID_ROCE, 708 PROTOCOLID_CORE, 709 PROTOCOLID_ETH, 710 PROTOCOLID_RESERVED4, 711 PROTOCOLID_RESERVED5, 712 PROTOCOLID_PREROCE, 713 PROTOCOLID_COMMON, 714 PROTOCOLID_RESERVED6, 715 MAX_PROTOCOL_TYPE 716 }; 717 718 struct ustorm_eth_queue_zone { 719 struct coalescing_timeset int_coalescing_timeset; 720 u8 reserved[3]; 721 }; 722 723 struct ustorm_queue_zone { 724 struct ustorm_eth_queue_zone eth; 725 struct common_queue_zone common; 726 }; 727 728 /* status block structure */ 729 struct cau_pi_entry { 730 u32 prod; 731 #define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF 732 #define CAU_PI_ENTRY_PROD_VAL_SHIFT 0 733 #define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F 734 #define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16 735 #define CAU_PI_ENTRY_FSM_SEL_MASK 0x1 736 #define CAU_PI_ENTRY_FSM_SEL_SHIFT 23 737 #define CAU_PI_ENTRY_RESERVED_MASK 0xFF 738 #define CAU_PI_ENTRY_RESERVED_SHIFT 24 739 }; 740 741 /* status block structure */ 742 struct cau_sb_entry { 743 u32 data; 744 #define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF 745 #define CAU_SB_ENTRY_SB_PROD_SHIFT 0 746 #define CAU_SB_ENTRY_STATE0_MASK 0xF 747 #define CAU_SB_ENTRY_STATE0_SHIFT 24 748 #define CAU_SB_ENTRY_STATE1_MASK 0xF 749 #define CAU_SB_ENTRY_STATE1_SHIFT 28 750 u32 params; 751 #define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F 752 #define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0 753 #define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F 754 #define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7 755 #define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3 756 #define CAU_SB_ENTRY_TIMER_RES0_SHIFT 14 757 #define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3 758 #define CAU_SB_ENTRY_TIMER_RES1_SHIFT 16 759 #define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF 760 #define CAU_SB_ENTRY_VF_NUMBER_SHIFT 18 761 #define CAU_SB_ENTRY_VF_VALID_MASK 0x1 762 #define CAU_SB_ENTRY_VF_VALID_SHIFT 26 763 #define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF 764 #define CAU_SB_ENTRY_PF_NUMBER_SHIFT 27 765 #define CAU_SB_ENTRY_TPH_MASK 0x1 766 #define CAU_SB_ENTRY_TPH_SHIFT 31 767 }; 768 769 /* core doorbell data */ 770 struct core_db_data { 771 u8 params; 772 #define CORE_DB_DATA_DEST_MASK 0x3 773 #define CORE_DB_DATA_DEST_SHIFT 0 774 #define CORE_DB_DATA_AGG_CMD_MASK 0x3 775 #define CORE_DB_DATA_AGG_CMD_SHIFT 2 776 #define CORE_DB_DATA_BYPASS_EN_MASK 0x1 777 #define CORE_DB_DATA_BYPASS_EN_SHIFT 4 778 #define CORE_DB_DATA_RESERVED_MASK 0x1 779 #define CORE_DB_DATA_RESERVED_SHIFT 5 780 #define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3 781 #define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6 782 u8 agg_flags; 783 __le16 spq_prod; 784 }; 785 786 /* Enum of doorbell aggregative command selection */ 787 enum db_agg_cmd_sel { 788 DB_AGG_CMD_NOP, 789 DB_AGG_CMD_SET, 790 DB_AGG_CMD_ADD, 791 DB_AGG_CMD_MAX, 792 MAX_DB_AGG_CMD_SEL 793 }; 794 795 /* Enum of doorbell destination */ 796 enum db_dest { 797 DB_DEST_XCM, 798 DB_DEST_UCM, 799 DB_DEST_TCM, 800 DB_NUM_DESTINATIONS, 801 MAX_DB_DEST 802 }; 803 804 /* Enum of doorbell DPM types */ 805 enum db_dpm_type { 806 DPM_LEGACY, 807 DPM_ROCE, 808 DPM_L2_INLINE, 809 DPM_L2_BD, 810 MAX_DB_DPM_TYPE 811 }; 812 813 /* Structure for doorbell data, in L2 DPM mode, for 1st db in a DPM burst */ 814 struct db_l2_dpm_data { 815 __le16 icid; 816 __le16 bd_prod; 817 __le32 params; 818 #define DB_L2_DPM_DATA_SIZE_MASK 0x3F 819 #define DB_L2_DPM_DATA_SIZE_SHIFT 0 820 #define DB_L2_DPM_DATA_DPM_TYPE_MASK 0x3 821 #define DB_L2_DPM_DATA_DPM_TYPE_SHIFT 6 822 #define DB_L2_DPM_DATA_NUM_BDS_MASK 0xFF 823 #define DB_L2_DPM_DATA_NUM_BDS_SHIFT 8 824 #define DB_L2_DPM_DATA_PKT_SIZE_MASK 0x7FF 825 #define DB_L2_DPM_DATA_PKT_SIZE_SHIFT 16 826 #define DB_L2_DPM_DATA_RESERVED0_MASK 0x1 827 #define DB_L2_DPM_DATA_RESERVED0_SHIFT 27 828 #define DB_L2_DPM_DATA_SGE_NUM_MASK 0x7 829 #define DB_L2_DPM_DATA_SGE_NUM_SHIFT 28 830 #define DB_L2_DPM_DATA_RESERVED1_MASK 0x1 831 #define DB_L2_DPM_DATA_RESERVED1_SHIFT 31 832 }; 833 834 /* Structure for SGE in a DPM doorbell of type DPM_L2_BD */ 835 struct db_l2_dpm_sge { 836 struct regpair addr; 837 __le16 nbytes; 838 __le16 bitfields; 839 #define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF 840 #define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0 841 #define DB_L2_DPM_SGE_RESERVED0_MASK 0x3 842 #define DB_L2_DPM_SGE_RESERVED0_SHIFT 9 843 #define DB_L2_DPM_SGE_ST_VALID_MASK 0x1 844 #define DB_L2_DPM_SGE_ST_VALID_SHIFT 11 845 #define DB_L2_DPM_SGE_RESERVED1_MASK 0xF 846 #define DB_L2_DPM_SGE_RESERVED1_SHIFT 12 847 __le32 reserved2; 848 }; 849 850 /* Structure for doorbell address, in legacy mode */ 851 struct db_legacy_addr { 852 __le32 addr; 853 #define DB_LEGACY_ADDR_RESERVED0_MASK 0x3 854 #define DB_LEGACY_ADDR_RESERVED0_SHIFT 0 855 #define DB_LEGACY_ADDR_DEMS_MASK 0x7 856 #define DB_LEGACY_ADDR_DEMS_SHIFT 2 857 #define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF 858 #define DB_LEGACY_ADDR_ICID_SHIFT 5 859 }; 860 861 /* Structure for doorbell address, in PWM mode */ 862 struct db_pwm_addr { 863 __le32 addr; 864 #define DB_PWM_ADDR_RESERVED0_MASK 0x7 865 #define DB_PWM_ADDR_RESERVED0_SHIFT 0 866 #define DB_PWM_ADDR_OFFSET_MASK 0x7F 867 #define DB_PWM_ADDR_OFFSET_SHIFT 3 868 #define DB_PWM_ADDR_WID_MASK 0x3 869 #define DB_PWM_ADDR_WID_SHIFT 10 870 #define DB_PWM_ADDR_DPI_MASK 0xFFFF 871 #define DB_PWM_ADDR_DPI_SHIFT 12 872 #define DB_PWM_ADDR_RESERVED1_MASK 0xF 873 #define DB_PWM_ADDR_RESERVED1_SHIFT 28 874 }; 875 876 /* Parameters to RoCE firmware, passed in EDPM doorbell */ 877 struct db_roce_dpm_params { 878 __le32 params; 879 #define DB_ROCE_DPM_PARAMS_SIZE_MASK 0x3F 880 #define DB_ROCE_DPM_PARAMS_SIZE_SHIFT 0 881 #define DB_ROCE_DPM_PARAMS_DPM_TYPE_MASK 0x3 882 #define DB_ROCE_DPM_PARAMS_DPM_TYPE_SHIFT 6 883 #define DB_ROCE_DPM_PARAMS_OPCODE_MASK 0xFF 884 #define DB_ROCE_DPM_PARAMS_OPCODE_SHIFT 8 885 #define DB_ROCE_DPM_PARAMS_WQE_SIZE_MASK 0x7FF 886 #define DB_ROCE_DPM_PARAMS_WQE_SIZE_SHIFT 16 887 #define DB_ROCE_DPM_PARAMS_RESERVED0_MASK 0x1 888 #define DB_ROCE_DPM_PARAMS_RESERVED0_SHIFT 27 889 #define DB_ROCE_DPM_PARAMS_COMPLETION_FLG_MASK 0x1 890 #define DB_ROCE_DPM_PARAMS_COMPLETION_FLG_SHIFT 28 891 #define DB_ROCE_DPM_PARAMS_S_FLG_MASK 0x1 892 #define DB_ROCE_DPM_PARAMS_S_FLG_SHIFT 29 893 #define DB_ROCE_DPM_PARAMS_RESERVED1_MASK 0x3 894 #define DB_ROCE_DPM_PARAMS_RESERVED1_SHIFT 30 895 }; 896 897 /* Structure for doorbell data, in ROCE DPM mode, for 1st db in a DPM burst */ 898 struct db_roce_dpm_data { 899 __le16 icid; 900 __le16 prod_val; 901 struct db_roce_dpm_params params; 902 }; 903 904 /* Igu interrupt command */ 905 enum igu_int_cmd { 906 IGU_INT_ENABLE = 0, 907 IGU_INT_DISABLE = 1, 908 IGU_INT_NOP = 2, 909 IGU_INT_NOP2 = 3, 910 MAX_IGU_INT_CMD 911 }; 912 913 /* IGU producer or consumer update command */ 914 struct igu_prod_cons_update { 915 u32 sb_id_and_flags; 916 #define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF 917 #define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0 918 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1 919 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT 24 920 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3 921 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT 25 922 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1 923 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27 924 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1 925 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT 28 926 #define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3 927 #define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT 29 928 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1 929 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT 31 930 u32 reserved1; 931 }; 932 933 /* Igu segments access for default status block only */ 934 enum igu_seg_access { 935 IGU_SEG_ACCESS_REG = 0, 936 IGU_SEG_ACCESS_ATTN = 1, 937 MAX_IGU_SEG_ACCESS 938 }; 939 940 struct parsing_and_err_flags { 941 __le16 flags; 942 #define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3 943 #define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0 944 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3 945 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2 946 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1 947 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4 948 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1 949 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5 950 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1 951 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6 952 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1 953 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7 954 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1 955 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT 8 956 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1 957 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT 9 958 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1 959 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10 960 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1 961 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11 962 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1 963 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12 964 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1 965 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13 966 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1 967 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14 968 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1 969 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15 970 }; 971 972 struct pb_context { 973 __le32 crc[4]; 974 }; 975 976 struct pxp_concrete_fid { 977 __le16 fid; 978 #define PXP_CONCRETE_FID_PFID_MASK 0xF 979 #define PXP_CONCRETE_FID_PFID_SHIFT 0 980 #define PXP_CONCRETE_FID_PORT_MASK 0x3 981 #define PXP_CONCRETE_FID_PORT_SHIFT 4 982 #define PXP_CONCRETE_FID_PATH_MASK 0x1 983 #define PXP_CONCRETE_FID_PATH_SHIFT 6 984 #define PXP_CONCRETE_FID_VFVALID_MASK 0x1 985 #define PXP_CONCRETE_FID_VFVALID_SHIFT 7 986 #define PXP_CONCRETE_FID_VFID_MASK 0xFF 987 #define PXP_CONCRETE_FID_VFID_SHIFT 8 988 }; 989 990 struct pxp_pretend_concrete_fid { 991 __le16 fid; 992 #define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF 993 #define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0 994 #define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7 995 #define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4 996 #define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1 997 #define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT 7 998 #define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF 999 #define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8 1000 }; 1001 1002 union pxp_pretend_fid { 1003 struct pxp_pretend_concrete_fid concrete_fid; 1004 __le16 opaque_fid; 1005 }; 1006 1007 /* Pxp Pretend Command Register. */ 1008 struct pxp_pretend_cmd { 1009 union pxp_pretend_fid fid; 1010 __le16 control; 1011 #define PXP_PRETEND_CMD_PATH_MASK 0x1 1012 #define PXP_PRETEND_CMD_PATH_SHIFT 0 1013 #define PXP_PRETEND_CMD_USE_PORT_MASK 0x1 1014 #define PXP_PRETEND_CMD_USE_PORT_SHIFT 1 1015 #define PXP_PRETEND_CMD_PORT_MASK 0x3 1016 #define PXP_PRETEND_CMD_PORT_SHIFT 2 1017 #define PXP_PRETEND_CMD_RESERVED0_MASK 0xF 1018 #define PXP_PRETEND_CMD_RESERVED0_SHIFT 4 1019 #define PXP_PRETEND_CMD_RESERVED1_MASK 0xF 1020 #define PXP_PRETEND_CMD_RESERVED1_SHIFT 8 1021 #define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1 1022 #define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT 12 1023 #define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1 1024 #define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT 13 1025 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1 1026 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14 1027 #define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1 1028 #define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15 1029 }; 1030 1031 /* PTT Record in PXP Admin Window. */ 1032 struct pxp_ptt_entry { 1033 __le32 offset; 1034 #define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF 1035 #define PXP_PTT_ENTRY_OFFSET_SHIFT 0 1036 #define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF 1037 #define PXP_PTT_ENTRY_RESERVED0_SHIFT 23 1038 struct pxp_pretend_cmd pretend; 1039 }; 1040 1041 /* VF Zone A Permission Register. */ 1042 struct pxp_vf_zone_a_permission { 1043 __le32 control; 1044 #define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF 1045 #define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0 1046 #define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1 1047 #define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT 8 1048 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F 1049 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT 9 1050 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF 1051 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16 1052 }; 1053 1054 /* RSS hash type */ 1055 struct rdif_task_context { 1056 __le32 initial_ref_tag; 1057 __le16 app_tag_value; 1058 __le16 app_tag_mask; 1059 u8 flags0; 1060 #define RDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1 1061 #define RDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0 1062 #define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1 1063 #define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1 1064 #define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1 1065 #define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2 1066 #define RDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1 1067 #define RDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3 1068 #define RDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3 1069 #define RDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4 1070 #define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 1071 #define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 1072 #define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1 1073 #define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 7 1074 u8 partial_dif_data[7]; 1075 __le16 partial_crc_value; 1076 __le16 partial_checksum_value; 1077 __le32 offset_in_io; 1078 __le16 flags1; 1079 #define RDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1 1080 #define RDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0 1081 #define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1 1082 #define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1 1083 #define RDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1 1084 #define RDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2 1085 #define RDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1 1086 #define RDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3 1087 #define RDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1 1088 #define RDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4 1089 #define RDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1 1090 #define RDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5 1091 #define RDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7 1092 #define RDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6 1093 #define RDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3 1094 #define RDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9 1095 #define RDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1 1096 #define RDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11 1097 #define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1 1098 #define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12 1099 #define RDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1 1100 #define RDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13 1101 #define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1 1102 #define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 14 1103 #define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1 1104 #define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 15 1105 __le16 state; 1106 #define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_MASK 0xF 1107 #define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_SHIFT 0 1108 #define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_MASK 0xF 1109 #define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_SHIFT 4 1110 #define RDIF_TASK_CONTEXT_ERRORINIO_MASK 0x1 1111 #define RDIF_TASK_CONTEXT_ERRORINIO_SHIFT 8 1112 #define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1 1113 #define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9 1114 #define RDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF 1115 #define RDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 10 1116 #define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3 1117 #define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14 1118 __le32 reserved2; 1119 }; 1120 1121 /* RSS hash type */ 1122 enum rss_hash_type { 1123 RSS_HASH_TYPE_DEFAULT = 0, 1124 RSS_HASH_TYPE_IPV4 = 1, 1125 RSS_HASH_TYPE_TCP_IPV4 = 2, 1126 RSS_HASH_TYPE_IPV6 = 3, 1127 RSS_HASH_TYPE_TCP_IPV6 = 4, 1128 RSS_HASH_TYPE_UDP_IPV4 = 5, 1129 RSS_HASH_TYPE_UDP_IPV6 = 6, 1130 MAX_RSS_HASH_TYPE 1131 }; 1132 1133 /* status block structure */ 1134 struct status_block { 1135 __le16 pi_array[PIS_PER_SB]; 1136 __le32 sb_num; 1137 #define STATUS_BLOCK_SB_NUM_MASK 0x1FF 1138 #define STATUS_BLOCK_SB_NUM_SHIFT 0 1139 #define STATUS_BLOCK_ZERO_PAD_MASK 0x7F 1140 #define STATUS_BLOCK_ZERO_PAD_SHIFT 9 1141 #define STATUS_BLOCK_ZERO_PAD2_MASK 0xFFFF 1142 #define STATUS_BLOCK_ZERO_PAD2_SHIFT 16 1143 __le32 prod_index; 1144 #define STATUS_BLOCK_PROD_INDEX_MASK 0xFFFFFF 1145 #define STATUS_BLOCK_PROD_INDEX_SHIFT 0 1146 #define STATUS_BLOCK_ZERO_PAD3_MASK 0xFF 1147 #define STATUS_BLOCK_ZERO_PAD3_SHIFT 24 1148 }; 1149 1150 struct tdif_task_context { 1151 __le32 initial_ref_tag; 1152 __le16 app_tag_value; 1153 __le16 app_tag_mask; 1154 __le16 partial_crc_valueB; 1155 __le16 partial_checksum_valueB; 1156 __le16 stateB; 1157 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_MASK 0xF 1158 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_SHIFT 0 1159 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_MASK 0xF 1160 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_SHIFT 4 1161 #define TDIF_TASK_CONTEXT_ERRORINIOB_MASK 0x1 1162 #define TDIF_TASK_CONTEXT_ERRORINIOB_SHIFT 8 1163 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1 1164 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9 1165 #define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F 1166 #define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10 1167 u8 reserved1; 1168 u8 flags0; 1169 #define TDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1 1170 #define TDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0 1171 #define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1 1172 #define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1 1173 #define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1 1174 #define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2 1175 #define TDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1 1176 #define TDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3 1177 #define TDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3 1178 #define TDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4 1179 #define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 1180 #define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 1181 #define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1 1182 #define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7 1183 __le32 flags1; 1184 #define TDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1 1185 #define TDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0 1186 #define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1 1187 #define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1 1188 #define TDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1 1189 #define TDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2 1190 #define TDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1 1191 #define TDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3 1192 #define TDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1 1193 #define TDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4 1194 #define TDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1 1195 #define TDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5 1196 #define TDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7 1197 #define TDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6 1198 #define TDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3 1199 #define TDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9 1200 #define TDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1 1201 #define TDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11 1202 #define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1 1203 #define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12 1204 #define TDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1 1205 #define TDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13 1206 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_MASK 0xF 1207 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_SHIFT 14 1208 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_MASK 0xF 1209 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_SHIFT 18 1210 #define TDIF_TASK_CONTEXT_ERRORINIOA_MASK 0x1 1211 #define TDIF_TASK_CONTEXT_ERRORINIOA_SHIFT 22 1212 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_MASK 0x1 1213 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_SHIFT 23 1214 #define TDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF 1215 #define TDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 24 1216 #define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1 1217 #define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 28 1218 #define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1 1219 #define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 29 1220 #define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1 1221 #define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 30 1222 #define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1 1223 #define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31 1224 __le32 offset_in_iob; 1225 __le16 partial_crc_value_a; 1226 __le16 partial_checksum_valuea_; 1227 __le32 offset_in_ioa; 1228 u8 partial_dif_data_a[8]; 1229 u8 partial_dif_data_b[8]; 1230 }; 1231 1232 struct timers_context { 1233 __le32 logical_client_0; 1234 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0xFFFFFFF 1235 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT 0 1236 #define TIMERS_CONTEXT_VALIDLC0_MASK 0x1 1237 #define TIMERS_CONTEXT_VALIDLC0_SHIFT 28 1238 #define TIMERS_CONTEXT_ACTIVELC0_MASK 0x1 1239 #define TIMERS_CONTEXT_ACTIVELC0_SHIFT 29 1240 #define TIMERS_CONTEXT_RESERVED0_MASK 0x3 1241 #define TIMERS_CONTEXT_RESERVED0_SHIFT 30 1242 __le32 logical_client_1; 1243 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK 0xFFFFFFF 1244 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT 0 1245 #define TIMERS_CONTEXT_VALIDLC1_MASK 0x1 1246 #define TIMERS_CONTEXT_VALIDLC1_SHIFT 28 1247 #define TIMERS_CONTEXT_ACTIVELC1_MASK 0x1 1248 #define TIMERS_CONTEXT_ACTIVELC1_SHIFT 29 1249 #define TIMERS_CONTEXT_RESERVED1_MASK 0x3 1250 #define TIMERS_CONTEXT_RESERVED1_SHIFT 30 1251 __le32 logical_client_2; 1252 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK 0xFFFFFFF 1253 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT 0 1254 #define TIMERS_CONTEXT_VALIDLC2_MASK 0x1 1255 #define TIMERS_CONTEXT_VALIDLC2_SHIFT 28 1256 #define TIMERS_CONTEXT_ACTIVELC2_MASK 0x1 1257 #define TIMERS_CONTEXT_ACTIVELC2_SHIFT 29 1258 #define TIMERS_CONTEXT_RESERVED2_MASK 0x3 1259 #define TIMERS_CONTEXT_RESERVED2_SHIFT 30 1260 __le32 host_expiration_fields; 1261 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_MASK 0xFFFFFFF 1262 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_SHIFT 0 1263 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_MASK 0x1 1264 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_SHIFT 28 1265 #define TIMERS_CONTEXT_RESERVED3_MASK 0x7 1266 #define TIMERS_CONTEXT_RESERVED3_SHIFT 29 1267 }; 1268 #endif /* __COMMON_HSI__ */ 1269 #endif 1270