1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 // Copyright (c) 2022 Pengutronix, Oleksij Rempel <[email protected]> 4 */ 5 #ifndef _LINUX_PSE_CONTROLLER_H 6 #define _LINUX_PSE_CONTROLLER_H 7 8 #include <linux/ethtool.h> 9 #include <linux/list.h> 10 #include <uapi/linux/ethtool.h> 11 12 /* Maximum current in uA according to IEEE 802.3-2022 Table 145-1 */ 13 #define MAX_PI_CURRENT 1920000 14 /* Maximum power in mW according to IEEE 802.3-2022 Table 145-16 */ 15 #define MAX_PI_PW 99900 16 17 struct phy_device; 18 struct pse_controller_dev; 19 20 /** 21 * struct pse_control_config - PSE control/channel configuration. 22 * 23 * @podl_admin_control: set PoDL PSE admin control as described in 24 * IEEE 802.3-2018 30.15.1.2.1 acPoDLPSEAdminControl 25 * @c33_admin_control: set PSE admin control as described in 26 * IEEE 802.3-2022 30.9.1.2.1 acPSEAdminControl 27 */ 28 struct pse_control_config { 29 enum ethtool_podl_pse_admin_state podl_admin_control; 30 enum ethtool_c33_pse_admin_state c33_admin_control; 31 }; 32 33 /** 34 * struct pse_control_status - PSE control/channel status. 35 * 36 * @podl_admin_state: operational state of the PoDL PSE 37 * functions. IEEE 802.3-2018 30.15.1.1.2 aPoDLPSEAdminState 38 * @podl_pw_status: power detection status of the PoDL PSE. 39 * IEEE 802.3-2018 30.15.1.1.3 aPoDLPSEPowerDetectionStatus: 40 * @c33_admin_state: operational state of the PSE 41 * functions. IEEE 802.3-2022 30.9.1.1.2 aPSEAdminState 42 * @c33_pw_status: power detection status of the PSE. 43 * IEEE 802.3-2022 30.9.1.1.5 aPSEPowerDetectionStatus: 44 * @c33_pw_class: detected class of a powered PD 45 * IEEE 802.3-2022 30.9.1.1.8 aPSEPowerClassification 46 * @c33_actual_pw: power currently delivered by the PSE in mW 47 * IEEE 802.3-2022 30.9.1.1.23 aPSEActualPower 48 * @c33_ext_state_info: extended state information of the PSE 49 * @c33_avail_pw_limit: available power limit of the PSE in mW 50 * IEEE 802.3-2022 145.2.5.4 pse_avail_pwr 51 * @c33_pw_limit_ranges: supported power limit configuration range. The driver 52 * is in charge of the memory allocation. 53 * @c33_pw_limit_nb_ranges: number of supported power limit configuration 54 * ranges 55 */ 56 struct pse_control_status { 57 enum ethtool_podl_pse_admin_state podl_admin_state; 58 enum ethtool_podl_pse_pw_d_status podl_pw_status; 59 enum ethtool_c33_pse_admin_state c33_admin_state; 60 enum ethtool_c33_pse_pw_d_status c33_pw_status; 61 u32 c33_pw_class; 62 u32 c33_actual_pw; 63 struct ethtool_c33_pse_ext_state_info c33_ext_state_info; 64 u32 c33_avail_pw_limit; 65 struct ethtool_c33_pse_pw_limit_range *c33_pw_limit_ranges; 66 u32 c33_pw_limit_nb_ranges; 67 }; 68 69 /** 70 * struct pse_controller_ops - PSE controller driver callbacks 71 * 72 * @ethtool_get_status: get PSE control status for ethtool interface 73 * @setup_pi_matrix: setup PI matrix of the PSE controller 74 * @pi_is_enabled: Return 1 if the PSE PI is enabled, 0 if not. 75 * May also return negative errno. 76 * @pi_enable: Configure the PSE PI as enabled. 77 * @pi_disable: Configure the PSE PI as disabled. 78 * @pi_get_voltage: Return voltage similarly to get_voltage regulator 79 * callback. 80 * @pi_get_pw_limit: Get the configured power limit of the PSE PI. 81 * @pi_set_pw_limit: Configure the power limit of the PSE PI. 82 */ 83 struct pse_controller_ops { 84 int (*ethtool_get_status)(struct pse_controller_dev *pcdev, 85 unsigned long id, struct netlink_ext_ack *extack, 86 struct pse_control_status *status); 87 int (*setup_pi_matrix)(struct pse_controller_dev *pcdev); 88 int (*pi_is_enabled)(struct pse_controller_dev *pcdev, int id); 89 int (*pi_enable)(struct pse_controller_dev *pcdev, int id); 90 int (*pi_disable)(struct pse_controller_dev *pcdev, int id); 91 int (*pi_get_voltage)(struct pse_controller_dev *pcdev, int id); 92 int (*pi_get_pw_limit)(struct pse_controller_dev *pcdev, 93 int id); 94 int (*pi_set_pw_limit)(struct pse_controller_dev *pcdev, 95 int id, int max_mW); 96 }; 97 98 struct module; 99 struct device_node; 100 struct of_phandle_args; 101 struct pse_control; 102 103 /* PSE PI pairset pinout can either be Alternative A or Alternative B */ 104 enum pse_pi_pairset_pinout { 105 ALTERNATIVE_A, 106 ALTERNATIVE_B, 107 }; 108 109 /** 110 * struct pse_pi_pairset - PSE PI pairset entity describing the pinout 111 * alternative ant its phandle 112 * 113 * @pinout: description of the pinout alternative 114 * @np: device node pointer describing the pairset phandle 115 */ 116 struct pse_pi_pairset { 117 enum pse_pi_pairset_pinout pinout; 118 struct device_node *np; 119 }; 120 121 /** 122 * struct pse_pi - PSE PI (Power Interface) entity as described in 123 * IEEE 802.3-2022 145.2.4 124 * 125 * @pairset: table of the PSE PI pinout alternative for the two pairset 126 * @np: device node pointer of the PSE PI node 127 * @rdev: regulator represented by the PSE PI 128 * @admin_state_enabled: PI enabled state 129 */ 130 struct pse_pi { 131 struct pse_pi_pairset pairset[2]; 132 struct device_node *np; 133 struct regulator_dev *rdev; 134 bool admin_state_enabled; 135 }; 136 137 /** 138 * struct pse_controller_dev - PSE controller entity that might 139 * provide multiple PSE controls 140 * @ops: a pointer to device specific struct pse_controller_ops 141 * @owner: kernel module of the PSE controller driver 142 * @list: internal list of PSE controller devices 143 * @pse_control_head: head of internal list of requested PSE controls 144 * @dev: corresponding driver model device struct 145 * @of_pse_n_cells: number of cells in PSE line specifiers 146 * @nr_lines: number of PSE controls in this controller device 147 * @lock: Mutex for serialization access to the PSE controller 148 * @types: types of the PSE controller 149 * @pi: table of PSE PIs described in this controller device 150 * @no_of_pse_pi: flag set if the pse_pis devicetree node is not used 151 */ 152 struct pse_controller_dev { 153 const struct pse_controller_ops *ops; 154 struct module *owner; 155 struct list_head list; 156 struct list_head pse_control_head; 157 struct device *dev; 158 int of_pse_n_cells; 159 unsigned int nr_lines; 160 struct mutex lock; 161 enum ethtool_pse_types types; 162 struct pse_pi *pi; 163 bool no_of_pse_pi; 164 }; 165 166 #if IS_ENABLED(CONFIG_PSE_CONTROLLER) 167 int pse_controller_register(struct pse_controller_dev *pcdev); 168 void pse_controller_unregister(struct pse_controller_dev *pcdev); 169 struct device; 170 int devm_pse_controller_register(struct device *dev, 171 struct pse_controller_dev *pcdev); 172 173 struct pse_control *of_pse_control_get(struct device_node *node); 174 void pse_control_put(struct pse_control *psec); 175 176 int pse_ethtool_get_status(struct pse_control *psec, 177 struct netlink_ext_ack *extack, 178 struct pse_control_status *status); 179 int pse_ethtool_set_config(struct pse_control *psec, 180 struct netlink_ext_ack *extack, 181 const struct pse_control_config *config); 182 int pse_ethtool_set_pw_limit(struct pse_control *psec, 183 struct netlink_ext_ack *extack, 184 const unsigned int pw_limit); 185 186 bool pse_has_podl(struct pse_control *psec); 187 bool pse_has_c33(struct pse_control *psec); 188 189 #else 190 191 static inline struct pse_control *of_pse_control_get(struct device_node *node) 192 { 193 return ERR_PTR(-ENOENT); 194 } 195 196 static inline void pse_control_put(struct pse_control *psec) 197 { 198 } 199 200 static inline int pse_ethtool_get_status(struct pse_control *psec, 201 struct netlink_ext_ack *extack, 202 struct pse_control_status *status) 203 { 204 return -EOPNOTSUPP; 205 } 206 207 static inline int pse_ethtool_set_config(struct pse_control *psec, 208 struct netlink_ext_ack *extack, 209 const struct pse_control_config *config) 210 { 211 return -EOPNOTSUPP; 212 } 213 214 static inline int pse_ethtool_set_pw_limit(struct pse_control *psec, 215 struct netlink_ext_ack *extack, 216 const unsigned int pw_limit) 217 { 218 return -EOPNOTSUPP; 219 } 220 221 static inline bool pse_has_podl(struct pse_control *psec) 222 { 223 return false; 224 } 225 226 static inline bool pse_has_c33(struct pse_control *psec) 227 { 228 return false; 229 } 230 231 #endif 232 233 #endif 234