1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 // Copyright (c) 2022 Pengutronix, Oleksij Rempel <[email protected]> 4 */ 5 #ifndef _LINUX_PSE_CONTROLLER_H 6 #define _LINUX_PSE_CONTROLLER_H 7 8 #include <linux/ethtool.h> 9 #include <linux/list.h> 10 #include <uapi/linux/ethtool.h> 11 12 /* Maximum current in uA according to IEEE 802.3-2022 Table 145-1 */ 13 #define MAX_PI_CURRENT 1920000 14 /* Maximum power in mW according to IEEE 802.3-2022 Table 145-16 */ 15 #define MAX_PI_PW 99900 16 17 struct phy_device; 18 struct pse_controller_dev; 19 20 /** 21 * struct pse_control_config - PSE control/channel configuration. 22 * 23 * @podl_admin_control: set PoDL PSE admin control as described in 24 * IEEE 802.3-2018 30.15.1.2.1 acPoDLPSEAdminControl 25 * @c33_admin_control: set PSE admin control as described in 26 * IEEE 802.3-2022 30.9.1.2.1 acPSEAdminControl 27 */ 28 struct pse_control_config { 29 enum ethtool_podl_pse_admin_state podl_admin_control; 30 enum ethtool_c33_pse_admin_state c33_admin_control; 31 }; 32 33 /** 34 * struct pse_control_status - PSE control/channel status. 35 * 36 * @podl_admin_state: operational state of the PoDL PSE 37 * functions. IEEE 802.3-2018 30.15.1.1.2 aPoDLPSEAdminState 38 * @podl_pw_status: power detection status of the PoDL PSE. 39 * IEEE 802.3-2018 30.15.1.1.3 aPoDLPSEPowerDetectionStatus: 40 * @c33_admin_state: operational state of the PSE 41 * functions. IEEE 802.3-2022 30.9.1.1.2 aPSEAdminState 42 * @c33_pw_status: power detection status of the PSE. 43 * IEEE 802.3-2022 30.9.1.1.5 aPSEPowerDetectionStatus: 44 * @c33_pw_class: detected class of a powered PD 45 * IEEE 802.3-2022 30.9.1.1.8 aPSEPowerClassification 46 * @c33_actual_pw: power currently delivered by the PSE in mW 47 * IEEE 802.3-2022 30.9.1.1.23 aPSEActualPower 48 * @c33_ext_state_info: extended state information of the PSE 49 * @c33_avail_pw_limit: available power limit of the PSE in mW 50 * IEEE 802.3-2022 145.2.5.4 pse_avail_pwr 51 * @c33_pw_limit_ranges: supported power limit configuration range. The driver 52 * is in charge of the memory allocation. 53 * @c33_pw_limit_nb_ranges: number of supported power limit configuration 54 * ranges 55 */ 56 struct pse_control_status { 57 enum ethtool_podl_pse_admin_state podl_admin_state; 58 enum ethtool_podl_pse_pw_d_status podl_pw_status; 59 enum ethtool_c33_pse_admin_state c33_admin_state; 60 enum ethtool_c33_pse_pw_d_status c33_pw_status; 61 u32 c33_pw_class; 62 u32 c33_actual_pw; 63 struct ethtool_c33_pse_ext_state_info c33_ext_state_info; 64 u32 c33_avail_pw_limit; 65 struct ethtool_c33_pse_pw_limit_range *c33_pw_limit_ranges; 66 u32 c33_pw_limit_nb_ranges; 67 }; 68 69 /** 70 * struct pse_controller_ops - PSE controller driver callbacks 71 * 72 * @ethtool_get_status: get PSE control status for ethtool interface 73 * @setup_pi_matrix: setup PI matrix of the PSE controller 74 * @pi_is_enabled: Return 1 if the PSE PI is enabled, 0 if not. 75 * May also return negative errno. 76 * @pi_enable: Configure the PSE PI as enabled. 77 * @pi_disable: Configure the PSE PI as disabled. 78 * @pi_get_voltage: Return voltage similarly to get_voltage regulator 79 * callback. 80 * @pi_get_current_limit: Get the configured current limit similarly to 81 * get_current_limit regulator callback. 82 * @pi_set_current_limit: Configure the current limit similarly to 83 * set_current_limit regulator callback. 84 * Should not return an error in case of MAX_PI_CURRENT 85 * current value set. 86 */ 87 struct pse_controller_ops { 88 int (*ethtool_get_status)(struct pse_controller_dev *pcdev, 89 unsigned long id, struct netlink_ext_ack *extack, 90 struct pse_control_status *status); 91 int (*setup_pi_matrix)(struct pse_controller_dev *pcdev); 92 int (*pi_is_enabled)(struct pse_controller_dev *pcdev, int id); 93 int (*pi_enable)(struct pse_controller_dev *pcdev, int id); 94 int (*pi_disable)(struct pse_controller_dev *pcdev, int id); 95 int (*pi_get_voltage)(struct pse_controller_dev *pcdev, int id); 96 int (*pi_get_current_limit)(struct pse_controller_dev *pcdev, 97 int id); 98 int (*pi_set_current_limit)(struct pse_controller_dev *pcdev, 99 int id, int max_uA); 100 }; 101 102 struct module; 103 struct device_node; 104 struct of_phandle_args; 105 struct pse_control; 106 107 /* PSE PI pairset pinout can either be Alternative A or Alternative B */ 108 enum pse_pi_pairset_pinout { 109 ALTERNATIVE_A, 110 ALTERNATIVE_B, 111 }; 112 113 /** 114 * struct pse_pi_pairset - PSE PI pairset entity describing the pinout 115 * alternative ant its phandle 116 * 117 * @pinout: description of the pinout alternative 118 * @np: device node pointer describing the pairset phandle 119 */ 120 struct pse_pi_pairset { 121 enum pse_pi_pairset_pinout pinout; 122 struct device_node *np; 123 }; 124 125 /** 126 * struct pse_pi - PSE PI (Power Interface) entity as described in 127 * IEEE 802.3-2022 145.2.4 128 * 129 * @pairset: table of the PSE PI pinout alternative for the two pairset 130 * @np: device node pointer of the PSE PI node 131 * @rdev: regulator represented by the PSE PI 132 * @admin_state_enabled: PI enabled state 133 */ 134 struct pse_pi { 135 struct pse_pi_pairset pairset[2]; 136 struct device_node *np; 137 struct regulator_dev *rdev; 138 bool admin_state_enabled; 139 }; 140 141 /** 142 * struct pse_controller_dev - PSE controller entity that might 143 * provide multiple PSE controls 144 * @ops: a pointer to device specific struct pse_controller_ops 145 * @owner: kernel module of the PSE controller driver 146 * @list: internal list of PSE controller devices 147 * @pse_control_head: head of internal list of requested PSE controls 148 * @dev: corresponding driver model device struct 149 * @of_pse_n_cells: number of cells in PSE line specifiers 150 * @nr_lines: number of PSE controls in this controller device 151 * @lock: Mutex for serialization access to the PSE controller 152 * @types: types of the PSE controller 153 * @pi: table of PSE PIs described in this controller device 154 * @no_of_pse_pi: flag set if the pse_pis devicetree node is not used 155 */ 156 struct pse_controller_dev { 157 const struct pse_controller_ops *ops; 158 struct module *owner; 159 struct list_head list; 160 struct list_head pse_control_head; 161 struct device *dev; 162 int of_pse_n_cells; 163 unsigned int nr_lines; 164 struct mutex lock; 165 enum ethtool_pse_types types; 166 struct pse_pi *pi; 167 bool no_of_pse_pi; 168 }; 169 170 #if IS_ENABLED(CONFIG_PSE_CONTROLLER) 171 int pse_controller_register(struct pse_controller_dev *pcdev); 172 void pse_controller_unregister(struct pse_controller_dev *pcdev); 173 struct device; 174 int devm_pse_controller_register(struct device *dev, 175 struct pse_controller_dev *pcdev); 176 177 struct pse_control *of_pse_control_get(struct device_node *node); 178 void pse_control_put(struct pse_control *psec); 179 180 int pse_ethtool_get_status(struct pse_control *psec, 181 struct netlink_ext_ack *extack, 182 struct pse_control_status *status); 183 int pse_ethtool_set_config(struct pse_control *psec, 184 struct netlink_ext_ack *extack, 185 const struct pse_control_config *config); 186 int pse_ethtool_set_pw_limit(struct pse_control *psec, 187 struct netlink_ext_ack *extack, 188 const unsigned int pw_limit); 189 190 bool pse_has_podl(struct pse_control *psec); 191 bool pse_has_c33(struct pse_control *psec); 192 193 #else 194 195 static inline struct pse_control *of_pse_control_get(struct device_node *node) 196 { 197 return ERR_PTR(-ENOENT); 198 } 199 200 static inline void pse_control_put(struct pse_control *psec) 201 { 202 } 203 204 static inline int pse_ethtool_get_status(struct pse_control *psec, 205 struct netlink_ext_ack *extack, 206 struct pse_control_status *status) 207 { 208 return -EOPNOTSUPP; 209 } 210 211 static inline int pse_ethtool_set_config(struct pse_control *psec, 212 struct netlink_ext_ack *extack, 213 const struct pse_control_config *config) 214 { 215 return -EOPNOTSUPP; 216 } 217 218 static inline int pse_ethtool_set_pw_limit(struct pse_control *psec, 219 struct netlink_ext_ack *extack, 220 const unsigned int pw_limit) 221 { 222 return -EOPNOTSUPP; 223 } 224 225 static inline bool pse_has_podl(struct pse_control *psec) 226 { 227 return false; 228 } 229 230 static inline bool pse_has_c33(struct pse_control *psec) 231 { 232 return false; 233 } 234 235 #endif 236 237 #endif 238