1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 // Copyright (c) 2022 Pengutronix, Oleksij Rempel <[email protected]> 4 */ 5 #ifndef _LINUX_PSE_CONTROLLER_H 6 #define _LINUX_PSE_CONTROLLER_H 7 8 #include <linux/ethtool.h> 9 #include <linux/list.h> 10 #include <uapi/linux/ethtool.h> 11 12 /* Maximum current in uA according to IEEE 802.3-2022 Table 145-1 */ 13 #define MAX_PI_CURRENT 1920000 14 /* Maximum power in mW according to IEEE 802.3-2022 Table 145-16 */ 15 #define MAX_PI_PW 99900 16 17 struct phy_device; 18 struct pse_controller_dev; 19 20 /** 21 * struct pse_control_config - PSE control/channel configuration. 22 * 23 * @podl_admin_control: set PoDL PSE admin control as described in 24 * IEEE 802.3-2018 30.15.1.2.1 acPoDLPSEAdminControl 25 * @c33_admin_control: set PSE admin control as described in 26 * IEEE 802.3-2022 30.9.1.2.1 acPSEAdminControl 27 */ 28 struct pse_control_config { 29 enum ethtool_podl_pse_admin_state podl_admin_control; 30 enum ethtool_c33_pse_admin_state c33_admin_control; 31 }; 32 33 /** 34 * struct pse_admin_state - PSE operational state 35 * 36 * @podl_admin_state: operational state of the PoDL PSE 37 * functions. IEEE 802.3-2018 30.15.1.1.2 aPoDLPSEAdminState 38 * @c33_admin_state: operational state of the PSE 39 * functions. IEEE 802.3-2022 30.9.1.1.2 aPSEAdminState 40 */ 41 struct pse_admin_state { 42 enum ethtool_podl_pse_admin_state podl_admin_state; 43 enum ethtool_c33_pse_admin_state c33_admin_state; 44 }; 45 46 /** 47 * struct pse_pw_status - PSE power detection status 48 * 49 * @podl_pw_status: power detection status of the PoDL PSE. 50 * IEEE 802.3-2018 30.15.1.1.3 aPoDLPSEPowerDetectionStatus: 51 * @c33_pw_status: power detection status of the PSE. 52 * IEEE 802.3-2022 30.9.1.1.5 aPSEPowerDetectionStatus: 53 */ 54 struct pse_pw_status { 55 enum ethtool_podl_pse_pw_d_status podl_pw_status; 56 enum ethtool_c33_pse_pw_d_status c33_pw_status; 57 }; 58 59 /** 60 * struct pse_ext_state_info - PSE extended state information 61 * 62 * @c33_ext_state_info: extended state information of the PSE 63 */ 64 struct pse_ext_state_info { 65 struct ethtool_c33_pse_ext_state_info c33_ext_state_info; 66 }; 67 68 /** 69 * struct pse_pw_limit_ranges - PSE power limit configuration range 70 * 71 * @c33_pw_limit_ranges: supported power limit configuration range. The driver 72 * is in charge of the memory allocation. 73 */ 74 struct pse_pw_limit_ranges { 75 struct ethtool_c33_pse_pw_limit_range *c33_pw_limit_ranges; 76 }; 77 78 /** 79 * struct ethtool_pse_control_status - PSE control/channel status. 80 * 81 * @podl_admin_state: operational state of the PoDL PSE 82 * functions. IEEE 802.3-2018 30.15.1.1.2 aPoDLPSEAdminState 83 * @podl_pw_status: power detection status of the PoDL PSE. 84 * IEEE 802.3-2018 30.15.1.1.3 aPoDLPSEPowerDetectionStatus: 85 * @c33_admin_state: operational state of the PSE 86 * functions. IEEE 802.3-2022 30.9.1.1.2 aPSEAdminState 87 * @c33_pw_status: power detection status of the PSE. 88 * IEEE 802.3-2022 30.9.1.1.5 aPSEPowerDetectionStatus: 89 * @c33_pw_class: detected class of a powered PD 90 * IEEE 802.3-2022 30.9.1.1.8 aPSEPowerClassification 91 * @c33_actual_pw: power currently delivered by the PSE in mW 92 * IEEE 802.3-2022 30.9.1.1.23 aPSEActualPower 93 * @c33_ext_state_info: extended state information of the PSE 94 * @c33_avail_pw_limit: available power limit of the PSE in mW 95 * IEEE 802.3-2022 145.2.5.4 pse_avail_pwr 96 * @c33_pw_limit_ranges: supported power limit configuration range. The driver 97 * is in charge of the memory allocation 98 * @c33_pw_limit_nb_ranges: number of supported power limit configuration 99 * ranges 100 */ 101 struct ethtool_pse_control_status { 102 enum ethtool_podl_pse_admin_state podl_admin_state; 103 enum ethtool_podl_pse_pw_d_status podl_pw_status; 104 enum ethtool_c33_pse_admin_state c33_admin_state; 105 enum ethtool_c33_pse_pw_d_status c33_pw_status; 106 u32 c33_pw_class; 107 u32 c33_actual_pw; 108 struct ethtool_c33_pse_ext_state_info c33_ext_state_info; 109 u32 c33_avail_pw_limit; 110 struct ethtool_c33_pse_pw_limit_range *c33_pw_limit_ranges; 111 u32 c33_pw_limit_nb_ranges; 112 }; 113 114 /** 115 * struct pse_controller_ops - PSE controller driver callbacks 116 * 117 * @setup_pi_matrix: setup PI matrix of the PSE controller 118 * @pi_get_admin_state: Get the operational state of the PSE PI. This ops 119 * is mandatory. 120 * @pi_get_pw_status: Get the power detection status of the PSE PI. This 121 * ops is mandatory. 122 * @pi_get_ext_state: Get the extended state of the PSE PI. 123 * @pi_get_pw_class: Get the power class of the PSE PI. 124 * @pi_get_actual_pw: Get actual power of the PSE PI in mW. 125 * @pi_is_enabled: Return 1 if the PSE PI is enabled, 0 if not. 126 * May also return negative errno. 127 * @pi_enable: Configure the PSE PI as enabled. 128 * @pi_disable: Configure the PSE PI as disabled. 129 * @pi_get_voltage: Return voltage similarly to get_voltage regulator 130 * callback in uV. 131 * @pi_get_pw_limit: Get the configured power limit of the PSE PI in mW. 132 * @pi_set_pw_limit: Configure the power limit of the PSE PI in mW. 133 * @pi_get_pw_limit_ranges: Get the supported power limit configuration 134 * range. The driver is in charge of the memory 135 * allocation and should return the number of 136 * ranges. 137 */ 138 struct pse_controller_ops { 139 int (*setup_pi_matrix)(struct pse_controller_dev *pcdev); 140 int (*pi_get_admin_state)(struct pse_controller_dev *pcdev, int id, 141 struct pse_admin_state *admin_state); 142 int (*pi_get_pw_status)(struct pse_controller_dev *pcdev, int id, 143 struct pse_pw_status *pw_status); 144 int (*pi_get_ext_state)(struct pse_controller_dev *pcdev, int id, 145 struct pse_ext_state_info *ext_state_info); 146 int (*pi_get_pw_class)(struct pse_controller_dev *pcdev, int id); 147 int (*pi_get_actual_pw)(struct pse_controller_dev *pcdev, int id); 148 int (*pi_is_enabled)(struct pse_controller_dev *pcdev, int id); 149 int (*pi_enable)(struct pse_controller_dev *pcdev, int id); 150 int (*pi_disable)(struct pse_controller_dev *pcdev, int id); 151 int (*pi_get_voltage)(struct pse_controller_dev *pcdev, int id); 152 int (*pi_get_pw_limit)(struct pse_controller_dev *pcdev, 153 int id); 154 int (*pi_set_pw_limit)(struct pse_controller_dev *pcdev, 155 int id, int max_mW); 156 int (*pi_get_pw_limit_ranges)(struct pse_controller_dev *pcdev, int id, 157 struct pse_pw_limit_ranges *pw_limit_ranges); 158 }; 159 160 struct module; 161 struct device_node; 162 struct of_phandle_args; 163 struct pse_control; 164 struct ethtool_pse_control_status; 165 166 /* PSE PI pairset pinout can either be Alternative A or Alternative B */ 167 enum pse_pi_pairset_pinout { 168 ALTERNATIVE_A, 169 ALTERNATIVE_B, 170 }; 171 172 /** 173 * struct pse_pi_pairset - PSE PI pairset entity describing the pinout 174 * alternative ant its phandle 175 * 176 * @pinout: description of the pinout alternative 177 * @np: device node pointer describing the pairset phandle 178 */ 179 struct pse_pi_pairset { 180 enum pse_pi_pairset_pinout pinout; 181 struct device_node *np; 182 }; 183 184 /** 185 * struct pse_pi - PSE PI (Power Interface) entity as described in 186 * IEEE 802.3-2022 145.2.4 187 * 188 * @pairset: table of the PSE PI pinout alternative for the two pairset 189 * @np: device node pointer of the PSE PI node 190 * @rdev: regulator represented by the PSE PI 191 * @admin_state_enabled: PI enabled state 192 */ 193 struct pse_pi { 194 struct pse_pi_pairset pairset[2]; 195 struct device_node *np; 196 struct regulator_dev *rdev; 197 bool admin_state_enabled; 198 }; 199 200 /** 201 * struct pse_controller_dev - PSE controller entity that might 202 * provide multiple PSE controls 203 * @ops: a pointer to device specific struct pse_controller_ops 204 * @owner: kernel module of the PSE controller driver 205 * @list: internal list of PSE controller devices 206 * @pse_control_head: head of internal list of requested PSE controls 207 * @dev: corresponding driver model device struct 208 * @of_pse_n_cells: number of cells in PSE line specifiers 209 * @nr_lines: number of PSE controls in this controller device 210 * @lock: Mutex for serialization access to the PSE controller 211 * @types: types of the PSE controller 212 * @pi: table of PSE PIs described in this controller device 213 * @no_of_pse_pi: flag set if the pse_pis devicetree node is not used 214 */ 215 struct pse_controller_dev { 216 const struct pse_controller_ops *ops; 217 struct module *owner; 218 struct list_head list; 219 struct list_head pse_control_head; 220 struct device *dev; 221 int of_pse_n_cells; 222 unsigned int nr_lines; 223 struct mutex lock; 224 enum ethtool_pse_types types; 225 struct pse_pi *pi; 226 bool no_of_pse_pi; 227 }; 228 229 #if IS_ENABLED(CONFIG_PSE_CONTROLLER) 230 int pse_controller_register(struct pse_controller_dev *pcdev); 231 void pse_controller_unregister(struct pse_controller_dev *pcdev); 232 struct device; 233 int devm_pse_controller_register(struct device *dev, 234 struct pse_controller_dev *pcdev); 235 236 struct pse_control *of_pse_control_get(struct device_node *node); 237 void pse_control_put(struct pse_control *psec); 238 239 int pse_ethtool_get_status(struct pse_control *psec, 240 struct netlink_ext_ack *extack, 241 struct ethtool_pse_control_status *status); 242 int pse_ethtool_set_config(struct pse_control *psec, 243 struct netlink_ext_ack *extack, 244 const struct pse_control_config *config); 245 int pse_ethtool_set_pw_limit(struct pse_control *psec, 246 struct netlink_ext_ack *extack, 247 const unsigned int pw_limit); 248 249 bool pse_has_podl(struct pse_control *psec); 250 bool pse_has_c33(struct pse_control *psec); 251 252 #else 253 254 static inline struct pse_control *of_pse_control_get(struct device_node *node) 255 { 256 return ERR_PTR(-ENOENT); 257 } 258 259 static inline void pse_control_put(struct pse_control *psec) 260 { 261 } 262 263 static inline int pse_ethtool_get_status(struct pse_control *psec, 264 struct netlink_ext_ack *extack, 265 struct ethtool_pse_control_status *status) 266 { 267 return -EOPNOTSUPP; 268 } 269 270 static inline int pse_ethtool_set_config(struct pse_control *psec, 271 struct netlink_ext_ack *extack, 272 const struct pse_control_config *config) 273 { 274 return -EOPNOTSUPP; 275 } 276 277 static inline int pse_ethtool_set_pw_limit(struct pse_control *psec, 278 struct netlink_ext_ack *extack, 279 const unsigned int pw_limit) 280 { 281 return -EOPNOTSUPP; 282 } 283 284 static inline bool pse_has_podl(struct pse_control *psec) 285 { 286 return false; 287 } 288 289 static inline bool pse_has_c33(struct pse_control *psec) 290 { 291 return false; 292 } 293 294 #endif 295 296 #endif 297