1 /* 2 * OMAP Smartreflex Defines and Routines 3 * 4 * Author: Thara Gopinath <[email protected]> 5 * 6 * Copyright (C) 2010 Texas Instruments, Inc. 7 * Thara Gopinath <[email protected]> 8 * 9 * Copyright (C) 2008 Nokia Corporation 10 * Kalle Jokiniemi 11 * 12 * Copyright (C) 2007 Texas Instruments, Inc. 13 * Lesly A M <[email protected]> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License version 2 as 17 * published by the Free Software Foundation. 18 */ 19 20 #ifndef __POWER_SMARTREFLEX_H 21 #define __POWER_SMARTREFLEX_H 22 23 #include <linux/types.h> 24 #include <linux/platform_device.h> 25 #include <linux/delay.h> 26 #include <linux/platform_data/voltage-omap.h> 27 28 /* 29 * Different Smartreflex IPs version. The v1 is the 65nm version used in 30 * OMAP3430. The v2 is the update for the 45nm version of the IP 31 * used in OMAP3630 and OMAP4430 32 */ 33 #define SR_TYPE_V1 1 34 #define SR_TYPE_V2 2 35 36 /* SMART REFLEX REG ADDRESS OFFSET */ 37 #define SRCONFIG 0x00 38 #define SRSTATUS 0x04 39 #define SENVAL 0x08 40 #define SENMIN 0x0C 41 #define SENMAX 0x10 42 #define SENAVG 0x14 43 #define AVGWEIGHT 0x18 44 #define NVALUERECIPROCAL 0x1c 45 #define SENERROR_V1 0x20 46 #define ERRCONFIG_V1 0x24 47 #define IRQ_EOI 0x20 48 #define IRQSTATUS_RAW 0x24 49 #define IRQSTATUS 0x28 50 #define IRQENABLE_SET 0x2C 51 #define IRQENABLE_CLR 0x30 52 #define SENERROR_V2 0x34 53 #define ERRCONFIG_V2 0x38 54 55 /* Bit/Shift Positions */ 56 57 /* SRCONFIG */ 58 #define SRCONFIG_ACCUMDATA_SHIFT 22 59 #define SRCONFIG_SRCLKLENGTH_SHIFT 12 60 #define SRCONFIG_SENNENABLE_V1_SHIFT 5 61 #define SRCONFIG_SENPENABLE_V1_SHIFT 3 62 #define SRCONFIG_SENNENABLE_V2_SHIFT 1 63 #define SRCONFIG_SENPENABLE_V2_SHIFT 0 64 #define SRCONFIG_CLKCTRL_SHIFT 0 65 66 #define SRCONFIG_ACCUMDATA_MASK (0x3ff << 22) 67 68 #define SRCONFIG_SRENABLE BIT(11) 69 #define SRCONFIG_SENENABLE BIT(10) 70 #define SRCONFIG_ERRGEN_EN BIT(9) 71 #define SRCONFIG_MINMAXAVG_EN BIT(8) 72 #define SRCONFIG_DELAYCTRL BIT(2) 73 74 /* AVGWEIGHT */ 75 #define AVGWEIGHT_SENPAVGWEIGHT_SHIFT 2 76 #define AVGWEIGHT_SENNAVGWEIGHT_SHIFT 0 77 78 /* NVALUERECIPROCAL */ 79 #define NVALUERECIPROCAL_SENPGAIN_SHIFT 20 80 #define NVALUERECIPROCAL_SENNGAIN_SHIFT 16 81 #define NVALUERECIPROCAL_RNSENP_SHIFT 8 82 #define NVALUERECIPROCAL_RNSENN_SHIFT 0 83 84 /* ERRCONFIG */ 85 #define ERRCONFIG_ERRWEIGHT_SHIFT 16 86 #define ERRCONFIG_ERRMAXLIMIT_SHIFT 8 87 #define ERRCONFIG_ERRMINLIMIT_SHIFT 0 88 89 #define SR_ERRWEIGHT_MASK (0x07 << 16) 90 #define SR_ERRMAXLIMIT_MASK (0xff << 8) 91 #define SR_ERRMINLIMIT_MASK (0xff << 0) 92 93 #define ERRCONFIG_VPBOUNDINTEN_V1 BIT(31) 94 #define ERRCONFIG_VPBOUNDINTST_V1 BIT(30) 95 #define ERRCONFIG_MCUACCUMINTEN BIT(29) 96 #define ERRCONFIG_MCUACCUMINTST BIT(28) 97 #define ERRCONFIG_MCUVALIDINTEN BIT(27) 98 #define ERRCONFIG_MCUVALIDINTST BIT(26) 99 #define ERRCONFIG_MCUBOUNDINTEN BIT(25) 100 #define ERRCONFIG_MCUBOUNDINTST BIT(24) 101 #define ERRCONFIG_MCUDISACKINTEN BIT(23) 102 #define ERRCONFIG_VPBOUNDINTST_V2 BIT(23) 103 #define ERRCONFIG_MCUDISACKINTST BIT(22) 104 #define ERRCONFIG_VPBOUNDINTEN_V2 BIT(22) 105 106 #define ERRCONFIG_STATUS_V1_MASK (ERRCONFIG_VPBOUNDINTST_V1 | \ 107 ERRCONFIG_MCUACCUMINTST | \ 108 ERRCONFIG_MCUVALIDINTST | \ 109 ERRCONFIG_MCUBOUNDINTST | \ 110 ERRCONFIG_MCUDISACKINTST) 111 /* IRQSTATUS */ 112 #define IRQSTATUS_MCUACCUMINT BIT(3) 113 #define IRQSTATUS_MCVALIDINT BIT(2) 114 #define IRQSTATUS_MCBOUNDSINT BIT(1) 115 #define IRQSTATUS_MCUDISABLEACKINT BIT(0) 116 117 /* IRQENABLE_SET and IRQENABLE_CLEAR */ 118 #define IRQENABLE_MCUACCUMINT BIT(3) 119 #define IRQENABLE_MCUVALIDINT BIT(2) 120 #define IRQENABLE_MCUBOUNDSINT BIT(1) 121 #define IRQENABLE_MCUDISABLEACKINT BIT(0) 122 123 /* Common Bit values */ 124 125 #define SRCLKLENGTH_12MHZ_SYSCLK 0x3c 126 #define SRCLKLENGTH_13MHZ_SYSCLK 0x41 127 #define SRCLKLENGTH_19MHZ_SYSCLK 0x60 128 #define SRCLKLENGTH_26MHZ_SYSCLK 0x82 129 #define SRCLKLENGTH_38MHZ_SYSCLK 0xC0 130 131 /* 132 * 3430 specific values. Maybe these should be passed from board file or 133 * pmic structures. 134 */ 135 #define OMAP3430_SR_ACCUMDATA 0x1f4 136 137 #define OMAP3430_SR1_SENPAVGWEIGHT 0x03 138 #define OMAP3430_SR1_SENNAVGWEIGHT 0x03 139 140 #define OMAP3430_SR2_SENPAVGWEIGHT 0x01 141 #define OMAP3430_SR2_SENNAVGWEIGHT 0x01 142 143 #define OMAP3430_SR_ERRWEIGHT 0x04 144 #define OMAP3430_SR_ERRMAXLIMIT 0x02 145 146 enum sr_instance { 147 OMAP_SR_MPU, /* shared with iva on omap3 */ 148 OMAP_SR_CORE, 149 OMAP_SR_IVA, 150 OMAP_SR_NR, 151 }; 152 153 struct omap_sr { 154 char *name; 155 struct list_head node; 156 struct platform_device *pdev; 157 struct omap_sr_nvalue_table *nvalue_table; 158 struct voltagedomain *voltdm; 159 struct dentry *dbg_dir; 160 unsigned int irq; 161 int srid; 162 int ip_type; 163 int nvalue_count; 164 bool autocomp_active; 165 u32 clk_length; 166 u32 err_weight; 167 u32 err_minlimit; 168 u32 err_maxlimit; 169 u32 accum_data; 170 u32 senn_avgweight; 171 u32 senp_avgweight; 172 u32 senp_mod; 173 u32 senn_mod; 174 void __iomem *base; 175 }; 176 177 /** 178 * test_cond_timeout - busy-loop, testing a condition 179 * @cond: condition to test until it evaluates to true 180 * @timeout: maximum number of microseconds in the timeout 181 * @index: loop index (integer) 182 * 183 * Loop waiting for @cond to become true or until at least @timeout 184 * microseconds have passed. To use, define some integer @index in the 185 * calling code. After running, if @index == @timeout, then the loop has 186 * timed out. 187 * 188 * Copied from omap_test_timeout */ 189 #define sr_test_cond_timeout(cond, timeout, index) \ 190 ({ \ 191 for (index = 0; index < timeout; index++) { \ 192 if (cond) \ 193 break; \ 194 udelay(1); \ 195 } \ 196 }) 197 198 /** 199 * struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass 200 * pmic specific info to smartreflex driver 201 * 202 * @sr_pmic_init: API to initialize smartreflex on the PMIC side. 203 */ 204 struct omap_sr_pmic_data { 205 void (*sr_pmic_init) (void); 206 }; 207 208 /** 209 * struct omap_smartreflex_dev_attr - Smartreflex Device attribute. 210 * 211 * @sensor_voltdm_name: Name of voltdomain of SR instance 212 */ 213 struct omap_smartreflex_dev_attr { 214 const char *sensor_voltdm_name; 215 }; 216 217 /* 218 * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR. 219 * The smartreflex class driver should pass the class type. 220 * Should be used to populate the class_type field of the 221 * omap_smartreflex_class_data structure. 222 */ 223 #define SR_CLASS1 0x1 224 #define SR_CLASS2 0x2 225 #define SR_CLASS3 0x3 226 227 /** 228 * struct omap_sr_class_data - Smartreflex class driver info 229 * 230 * @enable: API to enable a particular class smaartreflex. 231 * @disable: API to disable a particular class smartreflex. 232 * @configure: API to configure a particular class smartreflex. 233 * @notify: API to notify the class driver about an event in SR. 234 * Not needed for class3. 235 * @notify_flags: specify the events to be notified to the class driver 236 * @class_type: specify which smartreflex class. 237 * Can be used by the SR driver to take any class 238 * based decisions. 239 */ 240 struct omap_sr_class_data { 241 int (*enable)(struct omap_sr *sr); 242 int (*disable)(struct omap_sr *sr, int is_volt_reset); 243 int (*configure)(struct omap_sr *sr); 244 int (*notify)(struct omap_sr *sr, u32 status); 245 u8 notify_flags; 246 u8 class_type; 247 }; 248 249 /** 250 * struct omap_sr_nvalue_table - Smartreflex n-target value info 251 * 252 * @efuse_offs: The offset of the efuse where n-target values are stored. 253 * @nvalue: The n-target value. 254 * @errminlimit: The value of the ERRMINLIMIT bitfield for this n-target 255 * @volt_nominal: microvolts DC that the VDD is initially programmed to 256 */ 257 struct omap_sr_nvalue_table { 258 u32 efuse_offs; 259 u32 nvalue; 260 u32 errminlimit; 261 unsigned long volt_nominal; 262 }; 263 264 /** 265 * struct omap_sr_data - Smartreflex platform data. 266 * 267 * @name: instance name 268 * @ip_type: Smartreflex IP type. 269 * @senp_mod: SENPENABLE value of the sr CONFIG register 270 * @senn_mod: SENNENABLE value for sr CONFIG register 271 * @err_weight ERRWEIGHT value of the sr ERRCONFIG register 272 * @err_maxlimit ERRMAXLIMIT value of the sr ERRCONFIG register 273 * @accum_data ACCUMDATA value of the sr CONFIG register 274 * @senn_avgweight SENNAVGWEIGHT value of the sr AVGWEIGHT register 275 * @senp_avgweight SENPAVGWEIGHT value of the sr AVGWEIGHT register 276 * @nvalue_count: Number of distinct nvalues in the nvalue table 277 * @enable_on_init: whether this sr module needs to enabled at 278 * boot up or not. 279 * @nvalue_table: table containing the efuse offsets and nvalues 280 * corresponding to them. 281 * @voltdm: Pointer to the voltage domain associated with the SR 282 */ 283 struct omap_sr_data { 284 const char *name; 285 int ip_type; 286 u32 senp_mod; 287 u32 senn_mod; 288 u32 err_weight; 289 u32 err_maxlimit; 290 u32 accum_data; 291 u32 senn_avgweight; 292 u32 senp_avgweight; 293 int nvalue_count; 294 bool enable_on_init; 295 struct omap_sr_nvalue_table *nvalue_table; 296 struct voltagedomain *voltdm; 297 }; 298 299 #ifdef CONFIG_POWER_AVS_OMAP 300 301 /* Smartreflex module enable/disable interface */ 302 void omap_sr_enable(struct voltagedomain *voltdm); 303 void omap_sr_disable(struct voltagedomain *voltdm); 304 void omap_sr_disable_reset_volt(struct voltagedomain *voltdm); 305 306 /* API to register the pmic specific data with the smartreflex driver. */ 307 void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data); 308 309 /* Smartreflex driver hooks to be called from Smartreflex class driver */ 310 int sr_enable(struct omap_sr *sr, unsigned long volt); 311 void sr_disable(struct omap_sr *sr); 312 int sr_configure_errgen(struct omap_sr *sr); 313 int sr_disable_errgen(struct omap_sr *sr); 314 int sr_configure_minmax(struct omap_sr *sr); 315 316 /* API to register the smartreflex class driver with the smartreflex driver */ 317 int sr_register_class(struct omap_sr_class_data *class_data); 318 #else 319 static inline void omap_sr_enable(struct voltagedomain *voltdm) {} 320 static inline void omap_sr_disable(struct voltagedomain *voltdm) {} 321 static inline void omap_sr_disable_reset_volt( 322 struct voltagedomain *voltdm) {} 323 static inline void omap_sr_register_pmic( 324 struct omap_sr_pmic_data *pmic_data) {} 325 #endif 326 #endif 327