1*70b46487SWolfram Sang /* SPDX-License-Identifier: GPL-2.0 */ 2*70b46487SWolfram Sang #ifndef MFD_TMIO_H 3*70b46487SWolfram Sang #define MFD_TMIO_H 4*70b46487SWolfram Sang 5*70b46487SWolfram Sang #include <linux/platform_device.h> 6*70b46487SWolfram Sang #include <linux/types.h> 7*70b46487SWolfram Sang 8*70b46487SWolfram Sang /* TMIO MMC platform flags */ 9*70b46487SWolfram Sang 10*70b46487SWolfram Sang /* 11*70b46487SWolfram Sang * Some controllers can support a 2-byte block size when the bus width is 12*70b46487SWolfram Sang * configured in 4-bit mode. 13*70b46487SWolfram Sang */ 14*70b46487SWolfram Sang #define TMIO_MMC_BLKSZ_2BYTES BIT(1) 15*70b46487SWolfram Sang 16*70b46487SWolfram Sang /* Some controllers can support SDIO IRQ signalling */ 17*70b46487SWolfram Sang #define TMIO_MMC_SDIO_IRQ BIT(2) 18*70b46487SWolfram Sang 19*70b46487SWolfram Sang /* Some features are only available or tested on R-Car Gen2 or later */ 20*70b46487SWolfram Sang #define TMIO_MMC_MIN_RCAR2 BIT(3) 21*70b46487SWolfram Sang 22*70b46487SWolfram Sang /* 23*70b46487SWolfram Sang * Some controllers require waiting for the SD bus to become idle before 24*70b46487SWolfram Sang * writing to some registers. 25*70b46487SWolfram Sang */ 26*70b46487SWolfram Sang #define TMIO_MMC_HAS_IDLE_WAIT BIT(4) 27*70b46487SWolfram Sang 28*70b46487SWolfram Sang /* 29*70b46487SWolfram Sang * Use the busy timeout feature. Probably all TMIO versions support it. Yet, 30*70b46487SWolfram Sang * we don't have documentation for old variants, so we enable only known good 31*70b46487SWolfram Sang * variants with this flag. Can be removed once all variants are known good. 32*70b46487SWolfram Sang */ 33*70b46487SWolfram Sang #define TMIO_MMC_USE_BUSY_TIMEOUT BIT(5) 34*70b46487SWolfram Sang 35*70b46487SWolfram Sang /* Some controllers have CMD12 automatically issue/non-issue register */ 36*70b46487SWolfram Sang #define TMIO_MMC_HAVE_CMD12_CTRL BIT(7) 37*70b46487SWolfram Sang 38*70b46487SWolfram Sang /* Controller has some SDIO status bits which must be 1 */ 39*70b46487SWolfram Sang #define TMIO_MMC_SDIO_STATUS_SETBITS BIT(8) 40*70b46487SWolfram Sang 41*70b46487SWolfram Sang /* Some controllers have a 32-bit wide data port register */ 42*70b46487SWolfram Sang #define TMIO_MMC_32BIT_DATA_PORT BIT(9) 43*70b46487SWolfram Sang 44*70b46487SWolfram Sang /* Some controllers allows to set SDx actual clock */ 45*70b46487SWolfram Sang #define TMIO_MMC_CLK_ACTUAL BIT(10) 46*70b46487SWolfram Sang 47*70b46487SWolfram Sang /* Some controllers have a CBSY bit */ 48*70b46487SWolfram Sang #define TMIO_MMC_HAVE_CBSY BIT(11) 49*70b46487SWolfram Sang 50*70b46487SWolfram Sang struct tmio_mmc_data { 51*70b46487SWolfram Sang void *chan_priv_tx; 52*70b46487SWolfram Sang void *chan_priv_rx; 53*70b46487SWolfram Sang unsigned int hclk; 54*70b46487SWolfram Sang unsigned long capabilities; 55*70b46487SWolfram Sang unsigned long capabilities2; 56*70b46487SWolfram Sang unsigned long flags; 57*70b46487SWolfram Sang u32 ocr_mask; /* available voltages */ 58*70b46487SWolfram Sang dma_addr_t dma_rx_offset; 59*70b46487SWolfram Sang unsigned int max_blk_count; 60*70b46487SWolfram Sang unsigned short max_segs; 61*70b46487SWolfram Sang }; 62*70b46487SWolfram Sang #endif 63*70b46487SWolfram Sang