1*74ba9207SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2ec2a0833SArnd Bergmann /* 3ec2a0833SArnd Bergmann * Copyright 2009 Texas Instruments. 4ec2a0833SArnd Bergmann */ 5ec2a0833SArnd Bergmann 6ec2a0833SArnd Bergmann #ifndef __ARCH_ARM_DAVINCI_SPI_H 7ec2a0833SArnd Bergmann #define __ARCH_ARM_DAVINCI_SPI_H 8ec2a0833SArnd Bergmann 93ad7a42dSMatt Porter #include <linux/platform_data/edma.h> 10ec2a0833SArnd Bergmann 11ec2a0833SArnd Bergmann #define SPI_INTERN_CS 0xFF 12ec2a0833SArnd Bergmann 13ec2a0833SArnd Bergmann enum { 14ec2a0833SArnd Bergmann SPI_VERSION_1, /* For DM355/DM365/DM6467 */ 15ec2a0833SArnd Bergmann SPI_VERSION_2, /* For DA8xx */ 16ec2a0833SArnd Bergmann }; 17ec2a0833SArnd Bergmann 18ec2a0833SArnd Bergmann /** 19ec2a0833SArnd Bergmann * davinci_spi_platform_data - Platform data for SPI master device on DaVinci 20ec2a0833SArnd Bergmann * 21ec2a0833SArnd Bergmann * @version: version of the SPI IP. Different DaVinci devices have slightly 22ec2a0833SArnd Bergmann * varying versions of the same IP. 23ec2a0833SArnd Bergmann * @num_chipselect: number of chipselects supported by this SPI master 24ec2a0833SArnd Bergmann * @intr_line: interrupt line used to connect the SPI IP to the ARM interrupt 25ec2a0833SArnd Bergmann * controller withn the SoC. Possible values are 0 and 1. 26ec2a0833SArnd Bergmann * @cshold_bug: set this to true if the SPI controller on your chip requires 27ec2a0833SArnd Bergmann * a write to CSHOLD bit in between transfers (like in DM355). 28ec2a0833SArnd Bergmann * @dma_event_q: DMA event queue to use if SPI_IO_TYPE_DMA is used for any 29ec2a0833SArnd Bergmann * device on the bus. 30ec2a0833SArnd Bergmann */ 31ec2a0833SArnd Bergmann struct davinci_spi_platform_data { 32ec2a0833SArnd Bergmann u8 version; 33ec2a0833SArnd Bergmann u8 num_chipselect; 34ec2a0833SArnd Bergmann u8 intr_line; 35fa466c91SFranklin S Cooper Jr u8 prescaler_limit; 36ec2a0833SArnd Bergmann bool cshold_bug; 37ec2a0833SArnd Bergmann enum dma_event_q dma_event_q; 38ec2a0833SArnd Bergmann }; 39ec2a0833SArnd Bergmann 40ec2a0833SArnd Bergmann /** 41ec2a0833SArnd Bergmann * davinci_spi_config - Per-chip-select configuration for SPI slave devices 42ec2a0833SArnd Bergmann * 43ec2a0833SArnd Bergmann * @wdelay: amount of delay between transmissions. Measured in number of 44ec2a0833SArnd Bergmann * SPI module clocks. 45ec2a0833SArnd Bergmann * @odd_parity: polarity of parity flag at the end of transmit data stream. 46ec2a0833SArnd Bergmann * 0 - odd parity, 1 - even parity. 47ec2a0833SArnd Bergmann * @parity_enable: enable transmission of parity at end of each transmit 48ec2a0833SArnd Bergmann * data stream. 49ec2a0833SArnd Bergmann * @io_type: type of IO transfer. Choose between polled, interrupt and DMA. 50ec2a0833SArnd Bergmann * @timer_disable: disable chip-select timers (setup and hold) 51ec2a0833SArnd Bergmann * @c2tdelay: chip-select setup time. Measured in number of SPI module clocks. 52ec2a0833SArnd Bergmann * @t2cdelay: chip-select hold time. Measured in number of SPI module clocks. 53ec2a0833SArnd Bergmann * @t2edelay: transmit data finished to SPI ENAn pin inactive time. Measured 54ec2a0833SArnd Bergmann * in number of SPI clocks. 55ec2a0833SArnd Bergmann * @c2edelay: chip-select active to SPI ENAn signal active time. Measured in 56ec2a0833SArnd Bergmann * number of SPI clocks. 57ec2a0833SArnd Bergmann */ 58ec2a0833SArnd Bergmann struct davinci_spi_config { 59ec2a0833SArnd Bergmann u8 wdelay; 60ec2a0833SArnd Bergmann u8 odd_parity; 61ec2a0833SArnd Bergmann u8 parity_enable; 62ec2a0833SArnd Bergmann #define SPI_IO_TYPE_INTR 0 63ec2a0833SArnd Bergmann #define SPI_IO_TYPE_POLL 1 64ec2a0833SArnd Bergmann #define SPI_IO_TYPE_DMA 2 65ec2a0833SArnd Bergmann u8 io_type; 66ec2a0833SArnd Bergmann u8 timer_disable; 67ec2a0833SArnd Bergmann u8 c2tdelay; 68ec2a0833SArnd Bergmann u8 t2cdelay; 69ec2a0833SArnd Bergmann u8 t2edelay; 70ec2a0833SArnd Bergmann u8 c2edelay; 71ec2a0833SArnd Bergmann }; 72ec2a0833SArnd Bergmann 73ec2a0833SArnd Bergmann #endif /* __ARCH_ARM_DAVINCI_SPI_H */ 74