1 /*
2  * OMAP GPIO handling defines and functions
3  *
4  * Copyright (C) 2003-2005 Nokia Corporation
5  *
6  * Written by Juha Yrjölä <[email protected]>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21  *
22  */
23 
24 #ifndef __ASM_ARCH_OMAP_GPIO_H
25 #define __ASM_ARCH_OMAP_GPIO_H
26 
27 #ifndef __ASSEMBLER__
28 #include <linux/io.h>
29 #include <linux/platform_device.h>
30 #endif
31 
32 #define OMAP1_MPUIO_BASE			0xfffb5000
33 
34 /*
35  * These are the omap15xx/16xx offsets. The omap7xx offset are
36  * OMAP_MPUIO_ / 2 offsets below.
37  */
38 #define OMAP_MPUIO_INPUT_LATCH		0x00
39 #define OMAP_MPUIO_OUTPUT		0x04
40 #define OMAP_MPUIO_IO_CNTL		0x08
41 #define OMAP_MPUIO_KBR_LATCH		0x10
42 #define OMAP_MPUIO_KBC			0x14
43 #define OMAP_MPUIO_GPIO_EVENT_MODE	0x18
44 #define OMAP_MPUIO_GPIO_INT_EDGE	0x1c
45 #define OMAP_MPUIO_KBD_INT		0x20
46 #define OMAP_MPUIO_GPIO_INT		0x24
47 #define OMAP_MPUIO_KBD_MASKIT		0x28
48 #define OMAP_MPUIO_GPIO_MASKIT		0x2c
49 #define OMAP_MPUIO_GPIO_DEBOUNCING	0x30
50 #define OMAP_MPUIO_LATCH		0x34
51 
52 #define OMAP34XX_NR_GPIOS		6
53 
54 /*
55  * OMAP1510 GPIO registers
56  */
57 #define OMAP1510_GPIO_DATA_INPUT	0x00
58 #define OMAP1510_GPIO_DATA_OUTPUT	0x04
59 #define OMAP1510_GPIO_DIR_CONTROL	0x08
60 #define OMAP1510_GPIO_INT_CONTROL	0x0c
61 #define OMAP1510_GPIO_INT_MASK		0x10
62 #define OMAP1510_GPIO_INT_STATUS	0x14
63 #define OMAP1510_GPIO_PIN_CONTROL	0x18
64 
65 #define OMAP1510_IH_GPIO_BASE		64
66 
67 /*
68  * OMAP1610 specific GPIO registers
69  */
70 #define OMAP1610_GPIO_REVISION		0x0000
71 #define OMAP1610_GPIO_SYSCONFIG		0x0010
72 #define OMAP1610_GPIO_SYSSTATUS		0x0014
73 #define OMAP1610_GPIO_IRQSTATUS1	0x0018
74 #define OMAP1610_GPIO_IRQENABLE1	0x001c
75 #define OMAP1610_GPIO_WAKEUPENABLE	0x0028
76 #define OMAP1610_GPIO_DATAIN		0x002c
77 #define OMAP1610_GPIO_DATAOUT		0x0030
78 #define OMAP1610_GPIO_DIRECTION		0x0034
79 #define OMAP1610_GPIO_EDGE_CTRL1	0x0038
80 #define OMAP1610_GPIO_EDGE_CTRL2	0x003c
81 #define OMAP1610_GPIO_CLEAR_IRQENABLE1	0x009c
82 #define OMAP1610_GPIO_CLEAR_WAKEUPENA	0x00a8
83 #define OMAP1610_GPIO_CLEAR_DATAOUT	0x00b0
84 #define OMAP1610_GPIO_SET_IRQENABLE1	0x00dc
85 #define OMAP1610_GPIO_SET_WAKEUPENA	0x00e8
86 #define OMAP1610_GPIO_SET_DATAOUT	0x00f0
87 
88 /*
89  * OMAP7XX specific GPIO registers
90  */
91 #define OMAP7XX_GPIO_DATA_INPUT		0x00
92 #define OMAP7XX_GPIO_DATA_OUTPUT	0x04
93 #define OMAP7XX_GPIO_DIR_CONTROL	0x08
94 #define OMAP7XX_GPIO_INT_CONTROL	0x0c
95 #define OMAP7XX_GPIO_INT_MASK		0x10
96 #define OMAP7XX_GPIO_INT_STATUS		0x14
97 
98 /*
99  * omap2+ specific GPIO registers
100  */
101 #define OMAP24XX_GPIO_REVISION		0x0000
102 #define OMAP24XX_GPIO_IRQSTATUS1	0x0018
103 #define OMAP24XX_GPIO_IRQSTATUS2	0x0028
104 #define OMAP24XX_GPIO_IRQENABLE2	0x002c
105 #define OMAP24XX_GPIO_IRQENABLE1	0x001c
106 #define OMAP24XX_GPIO_WAKE_EN		0x0020
107 #define OMAP24XX_GPIO_CTRL		0x0030
108 #define OMAP24XX_GPIO_OE		0x0034
109 #define OMAP24XX_GPIO_DATAIN		0x0038
110 #define OMAP24XX_GPIO_DATAOUT		0x003c
111 #define OMAP24XX_GPIO_LEVELDETECT0	0x0040
112 #define OMAP24XX_GPIO_LEVELDETECT1	0x0044
113 #define OMAP24XX_GPIO_RISINGDETECT	0x0048
114 #define OMAP24XX_GPIO_FALLINGDETECT	0x004c
115 #define OMAP24XX_GPIO_DEBOUNCE_EN	0x0050
116 #define OMAP24XX_GPIO_DEBOUNCE_VAL	0x0054
117 #define OMAP24XX_GPIO_CLEARIRQENABLE1	0x0060
118 #define OMAP24XX_GPIO_SETIRQENABLE1	0x0064
119 #define OMAP24XX_GPIO_CLEARWKUENA	0x0080
120 #define OMAP24XX_GPIO_SETWKUENA		0x0084
121 #define OMAP24XX_GPIO_CLEARDATAOUT	0x0090
122 #define OMAP24XX_GPIO_SETDATAOUT	0x0094
123 
124 #define OMAP4_GPIO_REVISION		0x0000
125 #define OMAP4_GPIO_EOI			0x0020
126 #define OMAP4_GPIO_IRQSTATUSRAW0	0x0024
127 #define OMAP4_GPIO_IRQSTATUSRAW1	0x0028
128 #define OMAP4_GPIO_IRQSTATUS0		0x002c
129 #define OMAP4_GPIO_IRQSTATUS1		0x0030
130 #define OMAP4_GPIO_IRQSTATUSSET0	0x0034
131 #define OMAP4_GPIO_IRQSTATUSSET1	0x0038
132 #define OMAP4_GPIO_IRQSTATUSCLR0	0x003c
133 #define OMAP4_GPIO_IRQSTATUSCLR1	0x0040
134 #define OMAP4_GPIO_IRQWAKEN0		0x0044
135 #define OMAP4_GPIO_IRQWAKEN1		0x0048
136 #define OMAP4_GPIO_IRQENABLE1		0x011c
137 #define OMAP4_GPIO_WAKE_EN		0x0120
138 #define OMAP4_GPIO_IRQSTATUS2		0x0128
139 #define OMAP4_GPIO_IRQENABLE2		0x012c
140 #define OMAP4_GPIO_CTRL			0x0130
141 #define OMAP4_GPIO_OE			0x0134
142 #define OMAP4_GPIO_DATAIN		0x0138
143 #define OMAP4_GPIO_DATAOUT		0x013c
144 #define OMAP4_GPIO_LEVELDETECT0		0x0140
145 #define OMAP4_GPIO_LEVELDETECT1		0x0144
146 #define OMAP4_GPIO_RISINGDETECT		0x0148
147 #define OMAP4_GPIO_FALLINGDETECT	0x014c
148 #define OMAP4_GPIO_DEBOUNCENABLE	0x0150
149 #define OMAP4_GPIO_DEBOUNCINGTIME	0x0154
150 #define OMAP4_GPIO_CLEARIRQENABLE1	0x0160
151 #define OMAP4_GPIO_SETIRQENABLE1	0x0164
152 #define OMAP4_GPIO_CLEARWKUENA		0x0180
153 #define OMAP4_GPIO_SETWKUENA		0x0184
154 #define OMAP4_GPIO_CLEARDATAOUT		0x0190
155 #define OMAP4_GPIO_SETDATAOUT		0x0194
156 
157 #define OMAP_MAX_GPIO_LINES		192
158 
159 #define OMAP_MPUIO(nr)		(OMAP_MAX_GPIO_LINES + (nr))
160 #define OMAP_GPIO_IS_MPUIO(nr)	((nr) >= OMAP_MAX_GPIO_LINES)
161 
162 #ifndef __ASSEMBLER__
163 struct omap_gpio_reg_offs {
164 	u16 revision;
165 	u16 direction;
166 	u16 datain;
167 	u16 dataout;
168 	u16 set_dataout;
169 	u16 clr_dataout;
170 	u16 irqstatus;
171 	u16 irqstatus2;
172 	u16 irqstatus_raw0;
173 	u16 irqstatus_raw1;
174 	u16 irqenable;
175 	u16 irqenable2;
176 	u16 set_irqenable;
177 	u16 clr_irqenable;
178 	u16 debounce;
179 	u16 debounce_en;
180 	u16 ctrl;
181 	u16 wkup_en;
182 	u16 leveldetect0;
183 	u16 leveldetect1;
184 	u16 risingdetect;
185 	u16 fallingdetect;
186 	u16 irqctrl;
187 	u16 edgectrl1;
188 	u16 edgectrl2;
189 	u16 pinctrl;
190 
191 	bool irqenable_inv;
192 };
193 
194 struct omap_gpio_platform_data {
195 	int bank_type;
196 	int bank_width;		/* GPIO bank width */
197 	int bank_stride;	/* Only needed for omap1 MPUIO */
198 	bool dbck_flag;		/* dbck required or not - True for OMAP3&4 */
199 	bool loses_context;	/* whether the bank would ever lose context */
200 	bool is_mpuio;		/* whether the bank is of type MPUIO */
201 	u32 non_wakeup_gpios;
202 
203 	struct omap_gpio_reg_offs *regs;
204 
205 	/* Return context loss count due to PM states changing */
206 	int (*get_context_loss_count)(struct device *dev);
207 };
208 
209 #endif /* __ASSEMBLER__ */
210 
211 #endif
212