1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
22b49e0c5SAndy Shevchenko /*
32b49e0c5SAndy Shevchenko  * Driver for the High Speed UART DMA
42b49e0c5SAndy Shevchenko  *
52b49e0c5SAndy Shevchenko  * Copyright (C) 2015 Intel Corporation
62b49e0c5SAndy Shevchenko  */
72b49e0c5SAndy Shevchenko 
82b49e0c5SAndy Shevchenko #ifndef _PLATFORM_DATA_DMA_HSU_H
92b49e0c5SAndy Shevchenko #define _PLATFORM_DATA_DMA_HSU_H
102b49e0c5SAndy Shevchenko 
11*9c060026SAndy Shevchenko struct device;
122b49e0c5SAndy Shevchenko 
132b49e0c5SAndy Shevchenko struct hsu_dma_slave {
142b49e0c5SAndy Shevchenko 	struct device	*dma_dev;
152b49e0c5SAndy Shevchenko 	int		chan_id;
162b49e0c5SAndy Shevchenko };
172b49e0c5SAndy Shevchenko 
182b49e0c5SAndy Shevchenko #endif /* _PLATFORM_DATA_DMA_HSU_H */
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