1 /* 2 * Driver for the Synopsys DesignWare DMA Controller 3 * 4 * Copyright (C) 2007 Atmel Corporation 5 * Copyright (C) 2010-2011 ST Microelectronics 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #ifndef _PLATFORM_DATA_DMA_DW_H 12 #define _PLATFORM_DATA_DMA_DW_H 13 14 #include <linux/device.h> 15 16 /** 17 * struct dw_dma_slave - Controller-specific information about a slave 18 * 19 * @dma_dev: required DMA master device 20 * @src_id: src request line 21 * @dst_id: dst request line 22 * @src_master: src master for transfers on allocated channel. 23 * @dst_master: dest master for transfers on allocated channel. 24 */ 25 struct dw_dma_slave { 26 struct device *dma_dev; 27 u8 src_id; 28 u8 dst_id; 29 u8 src_master; 30 u8 dst_master; 31 }; 32 33 /** 34 * struct dw_dma_platform_data - Controller configuration parameters 35 * @nr_channels: Number of channels supported by hardware (max 8) 36 * @is_private: The device channels should be marked as private and not for 37 * by the general purpose DMA channel allocator. 38 * @chan_allocation_order: Allocate channels starting from 0 or 7 39 * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0. 40 * @block_size: Maximum block size supported by the controller 41 * @nr_masters: Number of AHB masters supported by the controller 42 * @data_width: Maximum data width supported by hardware per AHB master 43 * (0 - 8bits, 1 - 16bits, ..., 5 - 256bits) 44 */ 45 struct dw_dma_platform_data { 46 unsigned int nr_channels; 47 bool is_private; 48 #define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ 49 #define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */ 50 unsigned char chan_allocation_order; 51 #define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */ 52 #define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */ 53 unsigned char chan_priority; 54 unsigned short block_size; 55 unsigned char nr_masters; 56 unsigned char data_width[4]; 57 }; 58 59 #endif /* _PLATFORM_DATA_DMA_DW_H */ 60