1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Driver for the Synopsys DesignWare DMA Controller 4 * 5 * Copyright (C) 2007 Atmel Corporation 6 * Copyright (C) 2010-2011 ST Microelectronics 7 */ 8 #ifndef _PLATFORM_DATA_DMA_DW_H 9 #define _PLATFORM_DATA_DMA_DW_H 10 11 #include <linux/bits.h> 12 #include <linux/types.h> 13 14 #define DW_DMA_MAX_NR_MASTERS 4 15 #define DW_DMA_MAX_NR_CHANNELS 8 16 #define DW_DMA_MIN_BURST 1 17 #define DW_DMA_MAX_BURST 256 18 19 struct device; 20 21 /** 22 * struct dw_dma_slave - Controller-specific information about a slave 23 * 24 * @dma_dev: required DMA master device 25 * @src_id: src request line 26 * @dst_id: dst request line 27 * @m_master: memory master for transfers on allocated channel 28 * @p_master: peripheral master for transfers on allocated channel 29 * @hs_polarity:set active low polarity of handshake interface 30 */ 31 struct dw_dma_slave { 32 struct device *dma_dev; 33 u8 src_id; 34 u8 dst_id; 35 u8 m_master; 36 u8 p_master; 37 bool hs_polarity; 38 }; 39 40 /** 41 * struct dw_dma_platform_data - Controller configuration parameters 42 * @nr_channels: Number of channels supported by hardware (max 8) 43 * @chan_allocation_order: Allocate channels starting from 0 or 7 44 * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0. 45 * @block_size: Maximum block size supported by the controller 46 * @nr_masters: Number of AHB masters supported by the controller 47 * @data_width: Maximum data width supported by hardware per AHB master 48 * (in bytes, power of 2) 49 * @multi_block: Multi block transfers supported by hardware per channel. 50 * @max_burst: Maximum value of burst transaction size supported by hardware 51 * per channel (in units of CTL.SRC_TR_WIDTH/CTL.DST_TR_WIDTH). 52 * @protctl: Protection control signals setting per channel. 53 */ 54 struct dw_dma_platform_data { 55 unsigned int nr_channels; 56 #define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ 57 #define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */ 58 unsigned char chan_allocation_order; 59 #define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */ 60 #define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */ 61 unsigned char chan_priority; 62 unsigned int block_size; 63 unsigned char nr_masters; 64 unsigned char data_width[DW_DMA_MAX_NR_MASTERS]; 65 unsigned char multi_block[DW_DMA_MAX_NR_CHANNELS]; 66 u32 max_burst[DW_DMA_MAX_NR_CHANNELS]; 67 #define CHAN_PROTCTL_PRIVILEGED BIT(0) 68 #define CHAN_PROTCTL_BUFFERABLE BIT(1) 69 #define CHAN_PROTCTL_CACHEABLE BIT(2) 70 #define CHAN_PROTCTL_MASK GENMASK(2, 0) 71 unsigned char protctl; 72 }; 73 74 #endif /* _PLATFORM_DATA_DMA_DW_H */ 75