1*17ce2522SLizhi Hou /* SPDX-License-Identifier: GPL-2.0-or-later */
2*17ce2522SLizhi Hou /*
3*17ce2522SLizhi Hou  * Copyright (C) 2022, Advanced Micro Devices, Inc.
4*17ce2522SLizhi Hou  */
5*17ce2522SLizhi Hou 
6*17ce2522SLizhi Hou #ifndef _PLATDATA_AMD_XDMA_H
7*17ce2522SLizhi Hou #define _PLATDATA_AMD_XDMA_H
8*17ce2522SLizhi Hou 
9*17ce2522SLizhi Hou #include <linux/dmaengine.h>
10*17ce2522SLizhi Hou 
11*17ce2522SLizhi Hou /**
12*17ce2522SLizhi Hou  * struct xdma_chan_info - DMA channel information
13*17ce2522SLizhi Hou  *	This information is used to match channel when request dma channel
14*17ce2522SLizhi Hou  * @dir: Channel transfer direction
15*17ce2522SLizhi Hou  */
16*17ce2522SLizhi Hou struct xdma_chan_info {
17*17ce2522SLizhi Hou 	enum dma_transfer_direction dir;
18*17ce2522SLizhi Hou };
19*17ce2522SLizhi Hou 
20*17ce2522SLizhi Hou #define XDMA_FILTER_PARAM(chan_info)	((void *)(chan_info))
21*17ce2522SLizhi Hou 
22*17ce2522SLizhi Hou struct dma_slave_map;
23*17ce2522SLizhi Hou 
24*17ce2522SLizhi Hou /**
25*17ce2522SLizhi Hou  * struct xdma_platdata - platform specific data for XDMA engine
26*17ce2522SLizhi Hou  * @max_dma_channels: Maximum dma channels in each direction
27*17ce2522SLizhi Hou  */
28*17ce2522SLizhi Hou struct xdma_platdata {
29*17ce2522SLizhi Hou 	u32 max_dma_channels;
30*17ce2522SLizhi Hou 	u32 device_map_cnt;
31*17ce2522SLizhi Hou 	struct dma_slave_map *device_map;
32*17ce2522SLizhi Hou };
33*17ce2522SLizhi Hou 
34*17ce2522SLizhi Hou #endif /* _PLATDATA_AMD_XDMA_H */
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