173d5fc92SNishad Saraf /* SPDX-License-Identifier: GPL-2.0-or-later */ 273d5fc92SNishad Saraf /* 373d5fc92SNishad Saraf * Copyright (C) 2023-2024, Advanced Micro Devices, Inc. 473d5fc92SNishad Saraf */ 573d5fc92SNishad Saraf 673d5fc92SNishad Saraf #ifndef _PLATDATA_AMD_QDMA_H 773d5fc92SNishad Saraf #define _PLATDATA_AMD_QDMA_H 873d5fc92SNishad Saraf 973d5fc92SNishad Saraf #include <linux/dmaengine.h> 1073d5fc92SNishad Saraf 1173d5fc92SNishad Saraf /** 1273d5fc92SNishad Saraf * struct qdma_queue_info - DMA queue information. This information is used to 1373d5fc92SNishad Saraf * match queue when DMA channel is requested 1473d5fc92SNishad Saraf * @dir: Channel transfer direction 1573d5fc92SNishad Saraf */ 1673d5fc92SNishad Saraf struct qdma_queue_info { 1773d5fc92SNishad Saraf enum dma_transfer_direction dir; 1873d5fc92SNishad Saraf }; 1973d5fc92SNishad Saraf 2073d5fc92SNishad Saraf #define QDMA_FILTER_PARAM(qinfo) ((void *)(qinfo)) 2173d5fc92SNishad Saraf 2273d5fc92SNishad Saraf struct dma_slave_map; 2373d5fc92SNishad Saraf 2473d5fc92SNishad Saraf /** 2573d5fc92SNishad Saraf * struct qdma_platdata - Platform specific data for QDMA engine 2673d5fc92SNishad Saraf * @max_mm_channels: Maximum number of MM DMA channels in each direction 2773d5fc92SNishad Saraf * @device_map: DMA slave map 2873d5fc92SNishad Saraf * @irq_index: The index of first IRQ 29*dcbef079SLizhi Hou * @dma_dev: The device pointer for dma operations 3073d5fc92SNishad Saraf */ 3173d5fc92SNishad Saraf struct qdma_platdata { 3273d5fc92SNishad Saraf u32 max_mm_channels; 3373d5fc92SNishad Saraf u32 irq_index; 3473d5fc92SNishad Saraf struct dma_slave_map *device_map; 35*dcbef079SLizhi Hou struct device *dma_dev; 3673d5fc92SNishad Saraf }; 3773d5fc92SNishad Saraf 3873d5fc92SNishad Saraf #endif /* _PLATDATA_AMD_QDMA_H */ 39