1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2018 Cadence Design Systems Inc. 4 */ 5 6 #ifndef __PHY_MIPI_DPHY_H_ 7 #define __PHY_MIPI_DPHY_H_ 8 9 #include <video/videomode.h> 10 11 /** 12 * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set 13 * 14 * This structure is used to represent the configuration state of a 15 * MIPI D-PHY phy. 16 */ 17 struct phy_configure_opts_mipi_dphy { 18 /** 19 * @clk_miss: 20 * 21 * Timeout, in picoseconds, for receiver to detect absence of 22 * Clock transitions and disable the Clock Lane HS-RX. 23 * 24 * Maximum value: 60000 ps 25 */ 26 unsigned int clk_miss; 27 28 /** 29 * @clk_post: 30 * 31 * Time, in picoseconds, that the transmitter continues to 32 * send HS clock after the last associated Data Lane has 33 * transitioned to LP Mode. Interval is defined as the period 34 * from the end of @hs_trail to the beginning of @clk_trail. 35 * 36 * Minimum value: 60000 ps + 52 * @hs_clk_rate period in ps 37 */ 38 unsigned int clk_post; 39 40 /** 41 * @clk_pre: 42 * 43 * Time, in UI, that the HS clock shall be driven by 44 * the transmitter prior to any associated Data Lane beginning 45 * the transition from LP to HS mode. 46 * 47 * Minimum value: 8 UI 48 */ 49 unsigned int clk_pre; 50 51 /** 52 * @clk_prepare: 53 * 54 * Time, in picoseconds, that the transmitter drives the Clock 55 * Lane LP-00 Line state immediately before the HS-0 Line 56 * state starting the HS transmission. 57 * 58 * Minimum value: 38000 ps 59 * Maximum value: 95000 ps 60 */ 61 unsigned int clk_prepare; 62 63 /** 64 * @clk_settle: 65 * 66 * Time interval, in picoseconds, during which the HS receiver 67 * should ignore any Clock Lane HS transitions, starting from 68 * the beginning of @clk_prepare. 69 * 70 * Minimum value: 95000 ps 71 * Maximum value: 300000 ps 72 */ 73 unsigned int clk_settle; 74 75 /** 76 * @clk_term_en: 77 * 78 * Time, in picoseconds, for the Clock Lane receiver to enable 79 * the HS line termination. 80 * 81 * Maximum value: 38000 ps 82 */ 83 unsigned int clk_term_en; 84 85 /** 86 * @clk_trail: 87 * 88 * Time, in picoseconds, that the transmitter drives the HS-0 89 * state after the last payload clock bit of a HS transmission 90 * burst. 91 * 92 * Minimum value: 60000 ps 93 */ 94 unsigned int clk_trail; 95 96 /** 97 * @clk_zero: 98 * 99 * Time, in picoseconds, that the transmitter drives the HS-0 100 * state prior to starting the Clock. 101 */ 102 unsigned int clk_zero; 103 104 /** 105 * @d_term_en: 106 * 107 * Time, in picoseconds, for the Data Lane receiver to enable 108 * the HS line termination. 109 * 110 * Maximum value: 35000 ps + 4 * @hs_clk_rate period in ps 111 */ 112 unsigned int d_term_en; 113 114 /** 115 * @eot: 116 * 117 * Transmitted time interval, in picoseconds, from the start 118 * of @hs_trail or @clk_trail, to the start of the LP- 11 119 * state following a HS burst. 120 * 121 * Maximum value: 105000 ps + 12 * @hs_clk_rate period in ps 122 */ 123 unsigned int eot; 124 125 /** 126 * @hs_exit: 127 * 128 * Time, in picoseconds, that the transmitter drives LP-11 129 * following a HS burst. 130 * 131 * Minimum value: 100000 ps 132 */ 133 unsigned int hs_exit; 134 135 /** 136 * @hs_prepare: 137 * 138 * Time, in picoseconds, that the transmitter drives the Data 139 * Lane LP-00 Line state immediately before the HS-0 Line 140 * state starting the HS transmission. 141 * 142 * Minimum value: 40000 ps + 4 * @hs_clk_rate period in ps 143 * Maximum value: 85000 ps + 6 * @hs_clk_rate period in ps 144 */ 145 unsigned int hs_prepare; 146 147 /** 148 * @hs_settle: 149 * 150 * Time interval, in picoseconds, during which the HS receiver 151 * shall ignore any Data Lane HS transitions, starting from 152 * the beginning of @hs_prepare. 153 * 154 * Minimum value: 85000 ps + 6 * @hs_clk_rate period in ps 155 * Maximum value: 145000 ps + 10 * @hs_clk_rate period in ps 156 */ 157 unsigned int hs_settle; 158 159 /** 160 * @hs_skip: 161 * 162 * Time interval, in picoseconds, during which the HS-RX 163 * should ignore any transitions on the Data Lane, following a 164 * HS burst. The end point of the interval is defined as the 165 * beginning of the LP-11 state following the HS burst. 166 * 167 * Minimum value: 40000 ps 168 * Maximum value: 55000 ps + 4 * @hs_clk_rate period in ps 169 */ 170 unsigned int hs_skip; 171 172 /** 173 * @hs_trail: 174 * 175 * Time, in picoseconds, that the transmitter drives the 176 * flipped differential state after last payload data bit of a 177 * HS transmission burst 178 * 179 * Minimum value: max(8 * @hs_clk_rate period in ps, 180 * 60000 ps + 4 * @hs_clk_rate period in ps) 181 */ 182 unsigned int hs_trail; 183 184 /** 185 * @hs_zero: 186 * 187 * Time, in picoseconds, that the transmitter drives the HS-0 188 * state prior to transmitting the Sync sequence. 189 */ 190 unsigned int hs_zero; 191 192 /** 193 * @init: 194 * 195 * Time, in picoseconds for the initialization period to 196 * complete. 197 * 198 * Minimum value: 100000000 ps 199 */ 200 unsigned int init; 201 202 /** 203 * @lpx: 204 * 205 * Transmitted length, in picoseconds, of any Low-Power state 206 * period. 207 * 208 * Minimum value: 50000 ps 209 */ 210 unsigned int lpx; 211 212 /** 213 * @ta_get: 214 * 215 * Time, in picoseconds, that the new transmitter drives the 216 * Bridge state (LP-00) after accepting control during a Link 217 * Turnaround. 218 * 219 * Value: 5 * @lpx 220 */ 221 unsigned int ta_get; 222 223 /** 224 * @ta_go: 225 * 226 * Time, in picoseconds, that the transmitter drives the 227 * Bridge state (LP-00) before releasing control during a Link 228 * Turnaround. 229 * 230 * Value: 4 * @lpx 231 */ 232 unsigned int ta_go; 233 234 /** 235 * @ta_sure: 236 * 237 * Time, in picoseconds, that the new transmitter waits after 238 * the LP-10 state before transmitting the Bridge state 239 * (LP-00) during a Link Turnaround. 240 * 241 * Minimum value: @lpx 242 * Maximum value: 2 * @lpx 243 */ 244 unsigned int ta_sure; 245 246 /** 247 * @wakeup: 248 * 249 * Time, in picoseconds, that a transmitter drives a Mark-1 250 * state prior to a Stop state in order to initiate an exit 251 * from ULPS. 252 * 253 * Minimum value: 1000000000 ps 254 */ 255 unsigned int wakeup; 256 257 /** 258 * @hs_clk_rate: 259 * 260 * Clock rate, in Hertz, of the high-speed clock. 261 */ 262 unsigned long hs_clk_rate; 263 264 /** 265 * @lp_clk_rate: 266 * 267 * Clock rate, in Hertz, of the low-power clock. 268 */ 269 unsigned long lp_clk_rate; 270 271 /** 272 * @lanes: 273 * 274 * Number of active data lanes used for the transmissions. 275 */ 276 unsigned char lanes; 277 }; 278 279 int phy_mipi_dphy_get_default_config(unsigned long pixel_clock, 280 unsigned int bpp, 281 unsigned int lanes, 282 struct phy_configure_opts_mipi_dphy *cfg); 283 int phy_mipi_dphy_config_validate(struct phy_configure_opts_mipi_dphy *cfg); 284 285 #endif /* __PHY_MIPI_DPHY_H_ */ 286