1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Framework and drivers for configuring and reading different PHYs 4 * Based on code in sungem_phy.c and (long-removed) gianfar_phy.c 5 * 6 * Author: Andy Fleming 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 */ 10 11 #ifndef __PHY_H 12 #define __PHY_H 13 14 #include <linux/compiler.h> 15 #include <linux/spinlock.h> 16 #include <linux/ethtool.h> 17 #include <linux/leds.h> 18 #include <linux/linkmode.h> 19 #include <linux/netlink.h> 20 #include <linux/mdio.h> 21 #include <linux/mii.h> 22 #include <linux/mii_timestamper.h> 23 #include <linux/module.h> 24 #include <linux/timer.h> 25 #include <linux/workqueue.h> 26 #include <linux/mod_devicetable.h> 27 #include <linux/u64_stats_sync.h> 28 #include <linux/irqreturn.h> 29 #include <linux/iopoll.h> 30 #include <linux/refcount.h> 31 32 #include <linux/atomic.h> 33 #include <net/eee.h> 34 35 #define PHY_DEFAULT_FEATURES (SUPPORTED_Autoneg | \ 36 SUPPORTED_TP | \ 37 SUPPORTED_MII) 38 39 #define PHY_10BT_FEATURES (SUPPORTED_10baseT_Half | \ 40 SUPPORTED_10baseT_Full) 41 42 #define PHY_100BT_FEATURES (SUPPORTED_100baseT_Half | \ 43 SUPPORTED_100baseT_Full) 44 45 #define PHY_1000BT_FEATURES (SUPPORTED_1000baseT_Half | \ 46 SUPPORTED_1000baseT_Full) 47 48 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_features) __ro_after_init; 49 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1_features) __ro_after_init; 50 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1s_p2mp_features) __ro_after_init; 51 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_features) __ro_after_init; 52 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_fibre_features) __ro_after_init; 53 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_all_ports_features) __ro_after_init; 54 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_features) __ro_after_init; 55 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_fec_features) __ro_after_init; 56 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_full_features) __ro_after_init; 57 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_eee_cap1_features) __ro_after_init; 58 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_eee_cap2_features) __ro_after_init; 59 60 #define PHY_BASIC_FEATURES ((unsigned long *)&phy_basic_features) 61 #define PHY_BASIC_T1_FEATURES ((unsigned long *)&phy_basic_t1_features) 62 #define PHY_BASIC_T1S_P2MP_FEATURES ((unsigned long *)&phy_basic_t1s_p2mp_features) 63 #define PHY_GBIT_FEATURES ((unsigned long *)&phy_gbit_features) 64 #define PHY_GBIT_FIBRE_FEATURES ((unsigned long *)&phy_gbit_fibre_features) 65 #define PHY_GBIT_ALL_PORTS_FEATURES ((unsigned long *)&phy_gbit_all_ports_features) 66 #define PHY_10GBIT_FEATURES ((unsigned long *)&phy_10gbit_features) 67 #define PHY_10GBIT_FEC_FEATURES ((unsigned long *)&phy_10gbit_fec_features) 68 #define PHY_10GBIT_FULL_FEATURES ((unsigned long *)&phy_10gbit_full_features) 69 #define PHY_EEE_CAP1_FEATURES ((unsigned long *)&phy_eee_cap1_features) 70 #define PHY_EEE_CAP2_FEATURES ((unsigned long *)&phy_eee_cap2_features) 71 72 extern const int phy_basic_ports_array[3]; 73 extern const int phy_fibre_port_array[1]; 74 extern const int phy_all_ports_features_array[7]; 75 extern const int phy_10_100_features_array[4]; 76 extern const int phy_basic_t1_features_array[3]; 77 extern const int phy_basic_t1s_p2mp_features_array[2]; 78 extern const int phy_gbit_features_array[2]; 79 extern const int phy_10gbit_features_array[1]; 80 81 /* 82 * Set phydev->irq to PHY_POLL if interrupts are not supported, 83 * or not desired for this PHY. Set to PHY_MAC_INTERRUPT if 84 * the attached MAC driver handles the interrupt 85 */ 86 #define PHY_POLL -1 87 #define PHY_MAC_INTERRUPT -2 88 89 #define PHY_IS_INTERNAL 0x00000001 90 #define PHY_RST_AFTER_CLK_EN 0x00000002 91 #define PHY_POLL_CABLE_TEST 0x00000004 92 #define PHY_ALWAYS_CALL_SUSPEND 0x00000008 93 #define MDIO_DEVICE_IS_PHY 0x80000000 94 95 /** 96 * enum phy_interface_t - Interface Mode definitions 97 * 98 * @PHY_INTERFACE_MODE_NA: Not Applicable - don't touch 99 * @PHY_INTERFACE_MODE_INTERNAL: No interface, MAC and PHY combined 100 * @PHY_INTERFACE_MODE_MII: Media-independent interface 101 * @PHY_INTERFACE_MODE_GMII: Gigabit media-independent interface 102 * @PHY_INTERFACE_MODE_SGMII: Serial gigabit media-independent interface 103 * @PHY_INTERFACE_MODE_TBI: Ten Bit Interface 104 * @PHY_INTERFACE_MODE_REVMII: Reverse Media Independent Interface 105 * @PHY_INTERFACE_MODE_RMII: Reduced Media Independent Interface 106 * @PHY_INTERFACE_MODE_REVRMII: Reduced Media Independent Interface in PHY role 107 * @PHY_INTERFACE_MODE_RGMII: Reduced gigabit media-independent interface 108 * @PHY_INTERFACE_MODE_RGMII_ID: RGMII with Internal RX+TX delay 109 * @PHY_INTERFACE_MODE_RGMII_RXID: RGMII with Internal RX delay 110 * @PHY_INTERFACE_MODE_RGMII_TXID: RGMII with Internal RX delay 111 * @PHY_INTERFACE_MODE_RTBI: Reduced TBI 112 * @PHY_INTERFACE_MODE_SMII: Serial MII 113 * @PHY_INTERFACE_MODE_XGMII: 10 gigabit media-independent interface 114 * @PHY_INTERFACE_MODE_XLGMII:40 gigabit media-independent interface 115 * @PHY_INTERFACE_MODE_MOCA: Multimedia over Coax 116 * @PHY_INTERFACE_MODE_PSGMII: Penta SGMII 117 * @PHY_INTERFACE_MODE_QSGMII: Quad SGMII 118 * @PHY_INTERFACE_MODE_TRGMII: Turbo RGMII 119 * @PHY_INTERFACE_MODE_100BASEX: 100 BaseX 120 * @PHY_INTERFACE_MODE_1000BASEX: 1000 BaseX 121 * @PHY_INTERFACE_MODE_2500BASEX: 2500 BaseX 122 * @PHY_INTERFACE_MODE_5GBASER: 5G BaseR 123 * @PHY_INTERFACE_MODE_RXAUI: Reduced XAUI 124 * @PHY_INTERFACE_MODE_XAUI: 10 Gigabit Attachment Unit Interface 125 * @PHY_INTERFACE_MODE_10GBASER: 10G BaseR 126 * @PHY_INTERFACE_MODE_25GBASER: 25G BaseR 127 * @PHY_INTERFACE_MODE_USXGMII: Universal Serial 10GE MII 128 * @PHY_INTERFACE_MODE_10GKR: 10GBASE-KR - with Clause 73 AN 129 * @PHY_INTERFACE_MODE_QUSGMII: Quad Universal SGMII 130 * @PHY_INTERFACE_MODE_1000BASEKX: 1000Base-KX - with Clause 73 AN 131 * @PHY_INTERFACE_MODE_10G_QXGMII: 10G-QXGMII - 4 ports over 10G USXGMII 132 * @PHY_INTERFACE_MODE_MAX: Book keeping 133 * 134 * Describes the interface between the MAC and PHY. 135 */ 136 typedef enum { 137 PHY_INTERFACE_MODE_NA, 138 PHY_INTERFACE_MODE_INTERNAL, 139 PHY_INTERFACE_MODE_MII, 140 PHY_INTERFACE_MODE_GMII, 141 PHY_INTERFACE_MODE_SGMII, 142 PHY_INTERFACE_MODE_TBI, 143 PHY_INTERFACE_MODE_REVMII, 144 PHY_INTERFACE_MODE_RMII, 145 PHY_INTERFACE_MODE_REVRMII, 146 PHY_INTERFACE_MODE_RGMII, 147 PHY_INTERFACE_MODE_RGMII_ID, 148 PHY_INTERFACE_MODE_RGMII_RXID, 149 PHY_INTERFACE_MODE_RGMII_TXID, 150 PHY_INTERFACE_MODE_RTBI, 151 PHY_INTERFACE_MODE_SMII, 152 PHY_INTERFACE_MODE_XGMII, 153 PHY_INTERFACE_MODE_XLGMII, 154 PHY_INTERFACE_MODE_MOCA, 155 PHY_INTERFACE_MODE_PSGMII, 156 PHY_INTERFACE_MODE_QSGMII, 157 PHY_INTERFACE_MODE_TRGMII, 158 PHY_INTERFACE_MODE_100BASEX, 159 PHY_INTERFACE_MODE_1000BASEX, 160 PHY_INTERFACE_MODE_2500BASEX, 161 PHY_INTERFACE_MODE_5GBASER, 162 PHY_INTERFACE_MODE_RXAUI, 163 PHY_INTERFACE_MODE_XAUI, 164 /* 10GBASE-R, XFI, SFI - single lane 10G Serdes */ 165 PHY_INTERFACE_MODE_10GBASER, 166 PHY_INTERFACE_MODE_25GBASER, 167 PHY_INTERFACE_MODE_USXGMII, 168 /* 10GBASE-KR - with Clause 73 AN */ 169 PHY_INTERFACE_MODE_10GKR, 170 PHY_INTERFACE_MODE_QUSGMII, 171 PHY_INTERFACE_MODE_1000BASEKX, 172 PHY_INTERFACE_MODE_10G_QXGMII, 173 PHY_INTERFACE_MODE_MAX, 174 } phy_interface_t; 175 176 /* PHY interface mode bitmap handling */ 177 #define DECLARE_PHY_INTERFACE_MASK(name) \ 178 DECLARE_BITMAP(name, PHY_INTERFACE_MODE_MAX) 179 180 static inline void phy_interface_zero(unsigned long *intf) 181 { 182 bitmap_zero(intf, PHY_INTERFACE_MODE_MAX); 183 } 184 185 static inline bool phy_interface_empty(const unsigned long *intf) 186 { 187 return bitmap_empty(intf, PHY_INTERFACE_MODE_MAX); 188 } 189 190 static inline void phy_interface_and(unsigned long *dst, const unsigned long *a, 191 const unsigned long *b) 192 { 193 bitmap_and(dst, a, b, PHY_INTERFACE_MODE_MAX); 194 } 195 196 static inline void phy_interface_or(unsigned long *dst, const unsigned long *a, 197 const unsigned long *b) 198 { 199 bitmap_or(dst, a, b, PHY_INTERFACE_MODE_MAX); 200 } 201 202 static inline void phy_interface_set_rgmii(unsigned long *intf) 203 { 204 __set_bit(PHY_INTERFACE_MODE_RGMII, intf); 205 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, intf); 206 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, intf); 207 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, intf); 208 } 209 210 /* 211 * phy_supported_speeds - return all speeds currently supported by a PHY device 212 */ 213 unsigned int phy_supported_speeds(struct phy_device *phy, 214 unsigned int *speeds, 215 unsigned int size); 216 217 /** 218 * phy_modes - map phy_interface_t enum to device tree binding of phy-mode 219 * @interface: enum phy_interface_t value 220 * 221 * Description: maps enum &phy_interface_t defined in this file 222 * into the device tree binding of 'phy-mode', so that Ethernet 223 * device driver can get PHY interface from device tree. 224 */ 225 static inline const char *phy_modes(phy_interface_t interface) 226 { 227 switch (interface) { 228 case PHY_INTERFACE_MODE_NA: 229 return ""; 230 case PHY_INTERFACE_MODE_INTERNAL: 231 return "internal"; 232 case PHY_INTERFACE_MODE_MII: 233 return "mii"; 234 case PHY_INTERFACE_MODE_GMII: 235 return "gmii"; 236 case PHY_INTERFACE_MODE_SGMII: 237 return "sgmii"; 238 case PHY_INTERFACE_MODE_TBI: 239 return "tbi"; 240 case PHY_INTERFACE_MODE_REVMII: 241 return "rev-mii"; 242 case PHY_INTERFACE_MODE_RMII: 243 return "rmii"; 244 case PHY_INTERFACE_MODE_REVRMII: 245 return "rev-rmii"; 246 case PHY_INTERFACE_MODE_RGMII: 247 return "rgmii"; 248 case PHY_INTERFACE_MODE_RGMII_ID: 249 return "rgmii-id"; 250 case PHY_INTERFACE_MODE_RGMII_RXID: 251 return "rgmii-rxid"; 252 case PHY_INTERFACE_MODE_RGMII_TXID: 253 return "rgmii-txid"; 254 case PHY_INTERFACE_MODE_RTBI: 255 return "rtbi"; 256 case PHY_INTERFACE_MODE_SMII: 257 return "smii"; 258 case PHY_INTERFACE_MODE_XGMII: 259 return "xgmii"; 260 case PHY_INTERFACE_MODE_XLGMII: 261 return "xlgmii"; 262 case PHY_INTERFACE_MODE_MOCA: 263 return "moca"; 264 case PHY_INTERFACE_MODE_PSGMII: 265 return "psgmii"; 266 case PHY_INTERFACE_MODE_QSGMII: 267 return "qsgmii"; 268 case PHY_INTERFACE_MODE_TRGMII: 269 return "trgmii"; 270 case PHY_INTERFACE_MODE_1000BASEX: 271 return "1000base-x"; 272 case PHY_INTERFACE_MODE_1000BASEKX: 273 return "1000base-kx"; 274 case PHY_INTERFACE_MODE_2500BASEX: 275 return "2500base-x"; 276 case PHY_INTERFACE_MODE_5GBASER: 277 return "5gbase-r"; 278 case PHY_INTERFACE_MODE_RXAUI: 279 return "rxaui"; 280 case PHY_INTERFACE_MODE_XAUI: 281 return "xaui"; 282 case PHY_INTERFACE_MODE_10GBASER: 283 return "10gbase-r"; 284 case PHY_INTERFACE_MODE_25GBASER: 285 return "25gbase-r"; 286 case PHY_INTERFACE_MODE_USXGMII: 287 return "usxgmii"; 288 case PHY_INTERFACE_MODE_10GKR: 289 return "10gbase-kr"; 290 case PHY_INTERFACE_MODE_100BASEX: 291 return "100base-x"; 292 case PHY_INTERFACE_MODE_QUSGMII: 293 return "qusgmii"; 294 case PHY_INTERFACE_MODE_10G_QXGMII: 295 return "10g-qxgmii"; 296 default: 297 return "unknown"; 298 } 299 } 300 301 #define PHY_INIT_TIMEOUT 100000 302 #define PHY_FORCE_TIMEOUT 10 303 304 #define PHY_MAX_ADDR 32 305 306 /* Used when trying to connect to a specific phy (mii bus id:phy device id) */ 307 #define PHY_ID_FMT "%s:%02x" 308 309 #define MII_BUS_ID_SIZE 61 310 311 struct device; 312 struct kernel_hwtstamp_config; 313 struct phylink; 314 struct sfp_bus; 315 struct sfp_upstream_ops; 316 struct sk_buff; 317 318 /** 319 * struct mdio_bus_stats - Statistics counters for MDIO busses 320 * @transfers: Total number of transfers, i.e. @writes + @reads 321 * @errors: Number of MDIO transfers that returned an error 322 * @writes: Number of write transfers 323 * @reads: Number of read transfers 324 * @syncp: Synchronisation for incrementing statistics 325 */ 326 struct mdio_bus_stats { 327 u64_stats_t transfers; 328 u64_stats_t errors; 329 u64_stats_t writes; 330 u64_stats_t reads; 331 /* Must be last, add new statistics above */ 332 struct u64_stats_sync syncp; 333 }; 334 335 /** 336 * struct phy_package_shared - Shared information in PHY packages 337 * @base_addr: Base PHY address of PHY package used to combine PHYs 338 * in one package and for offset calculation of phy_package_read/write 339 * @np: Pointer to the Device Node if PHY package defined in DT 340 * @refcnt: Number of PHYs connected to this shared data 341 * @flags: Initialization of PHY package 342 * @priv_size: Size of the shared private data @priv 343 * @priv: Driver private data shared across a PHY package 344 * 345 * Represents a shared structure between different phydev's in the same 346 * package, for example a quad PHY. See phy_package_join() and 347 * phy_package_leave(). 348 */ 349 struct phy_package_shared { 350 u8 base_addr; 351 /* With PHY package defined in DT this points to the PHY package node */ 352 struct device_node *np; 353 refcount_t refcnt; 354 unsigned long flags; 355 size_t priv_size; 356 357 /* private data pointer */ 358 /* note that this pointer is shared between different phydevs and 359 * the user has to take care of appropriate locking. It is allocated 360 * and freed automatically by phy_package_join() and 361 * phy_package_leave(). 362 */ 363 void *priv; 364 }; 365 366 /* used as bit number in atomic bitops */ 367 #define PHY_SHARED_F_INIT_DONE 0 368 #define PHY_SHARED_F_PROBE_DONE 1 369 370 /** 371 * struct mii_bus - Represents an MDIO bus 372 * 373 * @owner: Who owns this device 374 * @name: User friendly name for this MDIO device, or driver name 375 * @id: Unique identifier for this bus, typical from bus hierarchy 376 * @priv: Driver private data 377 * 378 * The Bus class for PHYs. Devices which provide access to 379 * PHYs should register using this structure 380 */ 381 struct mii_bus { 382 struct module *owner; 383 const char *name; 384 char id[MII_BUS_ID_SIZE]; 385 void *priv; 386 /** @read: Perform a read transfer on the bus */ 387 int (*read)(struct mii_bus *bus, int addr, int regnum); 388 /** @write: Perform a write transfer on the bus */ 389 int (*write)(struct mii_bus *bus, int addr, int regnum, u16 val); 390 /** @read_c45: Perform a C45 read transfer on the bus */ 391 int (*read_c45)(struct mii_bus *bus, int addr, int devnum, int regnum); 392 /** @write_c45: Perform a C45 write transfer on the bus */ 393 int (*write_c45)(struct mii_bus *bus, int addr, int devnum, 394 int regnum, u16 val); 395 /** @reset: Perform a reset of the bus */ 396 int (*reset)(struct mii_bus *bus); 397 398 /** @stats: Statistic counters per device on the bus */ 399 struct mdio_bus_stats stats[PHY_MAX_ADDR]; 400 401 /** 402 * @mdio_lock: A lock to ensure that only one thing can read/write 403 * the MDIO bus at a time 404 */ 405 struct mutex mdio_lock; 406 407 /** @parent: Parent device of this bus */ 408 struct device *parent; 409 /** @state: State of bus structure */ 410 enum { 411 MDIOBUS_ALLOCATED = 1, 412 MDIOBUS_REGISTERED, 413 MDIOBUS_UNREGISTERED, 414 MDIOBUS_RELEASED, 415 } state; 416 417 /** @dev: Kernel device representation */ 418 struct device dev; 419 420 /** @mdio_map: list of all MDIO devices on bus */ 421 struct mdio_device *mdio_map[PHY_MAX_ADDR]; 422 423 /** @phy_mask: PHY addresses to be ignored when probing */ 424 u32 phy_mask; 425 426 /** @phy_ignore_ta_mask: PHY addresses to ignore the TA/read failure */ 427 u32 phy_ignore_ta_mask; 428 429 /** 430 * @irq: An array of interrupts, each PHY's interrupt at the index 431 * matching its address 432 */ 433 int irq[PHY_MAX_ADDR]; 434 435 /** @reset_delay_us: GPIO reset pulse width in microseconds */ 436 int reset_delay_us; 437 /** @reset_post_delay_us: GPIO reset deassert delay in microseconds */ 438 int reset_post_delay_us; 439 /** @reset_gpiod: Reset GPIO descriptor pointer */ 440 struct gpio_desc *reset_gpiod; 441 442 /** @shared_lock: protect access to the shared element */ 443 struct mutex shared_lock; 444 445 /** @shared: shared state across different PHYs */ 446 struct phy_package_shared *shared[PHY_MAX_ADDR]; 447 }; 448 #define to_mii_bus(d) container_of(d, struct mii_bus, dev) 449 450 struct mii_bus *mdiobus_alloc_size(size_t size); 451 452 /** 453 * mdiobus_alloc - Allocate an MDIO bus structure 454 * 455 * The internal state of the MDIO bus will be set of MDIOBUS_ALLOCATED ready 456 * for the driver to register the bus. 457 */ 458 static inline struct mii_bus *mdiobus_alloc(void) 459 { 460 return mdiobus_alloc_size(0); 461 } 462 463 int __mdiobus_register(struct mii_bus *bus, struct module *owner); 464 int __devm_mdiobus_register(struct device *dev, struct mii_bus *bus, 465 struct module *owner); 466 #define mdiobus_register(bus) __mdiobus_register(bus, THIS_MODULE) 467 #define devm_mdiobus_register(dev, bus) \ 468 __devm_mdiobus_register(dev, bus, THIS_MODULE) 469 470 void mdiobus_unregister(struct mii_bus *bus); 471 void mdiobus_free(struct mii_bus *bus); 472 struct mii_bus *devm_mdiobus_alloc_size(struct device *dev, int sizeof_priv); 473 static inline struct mii_bus *devm_mdiobus_alloc(struct device *dev) 474 { 475 return devm_mdiobus_alloc_size(dev, 0); 476 } 477 478 struct mii_bus *mdio_find_bus(const char *mdio_name); 479 struct phy_device *mdiobus_scan_c22(struct mii_bus *bus, int addr); 480 481 #define PHY_INTERRUPT_DISABLED false 482 #define PHY_INTERRUPT_ENABLED true 483 484 /** 485 * enum phy_state - PHY state machine states: 486 * 487 * @PHY_DOWN: PHY device and driver are not ready for anything. probe 488 * should be called if and only if the PHY is in this state, 489 * given that the PHY device exists. 490 * - PHY driver probe function will set the state to @PHY_READY 491 * 492 * @PHY_READY: PHY is ready to send and receive packets, but the 493 * controller is not. By default, PHYs which do not implement 494 * probe will be set to this state by phy_probe(). 495 * - start will set the state to UP 496 * 497 * @PHY_UP: The PHY and attached device are ready to do work. 498 * Interrupts should be started here. 499 * - timer moves to @PHY_NOLINK or @PHY_RUNNING 500 * 501 * @PHY_NOLINK: PHY is up, but not currently plugged in. 502 * - irq or timer will set @PHY_RUNNING if link comes back 503 * - phy_stop moves to @PHY_HALTED 504 * 505 * @PHY_RUNNING: PHY is currently up, running, and possibly sending 506 * and/or receiving packets 507 * - irq or timer will set @PHY_NOLINK if link goes down 508 * - phy_stop moves to @PHY_HALTED 509 * 510 * @PHY_CABLETEST: PHY is performing a cable test. Packet reception/sending 511 * is not expected to work, carrier will be indicated as down. PHY will be 512 * poll once per second, or on interrupt for it current state. 513 * Once complete, move to UP to restart the PHY. 514 * - phy_stop aborts the running test and moves to @PHY_HALTED 515 * 516 * @PHY_HALTED: PHY is up, but no polling or interrupts are done. 517 * - phy_start moves to @PHY_UP 518 * 519 * @PHY_ERROR: PHY is up, but is in an error state. 520 * - phy_stop moves to @PHY_HALTED 521 */ 522 enum phy_state { 523 PHY_DOWN = 0, 524 PHY_READY, 525 PHY_HALTED, 526 PHY_ERROR, 527 PHY_UP, 528 PHY_RUNNING, 529 PHY_NOLINK, 530 PHY_CABLETEST, 531 }; 532 533 #define MDIO_MMD_NUM 32 534 535 /** 536 * struct phy_c45_device_ids - 802.3-c45 Device Identifiers 537 * @devices_in_package: IEEE 802.3 devices in package register value. 538 * @mmds_present: bit vector of MMDs present. 539 * @device_ids: The device identifer for each present device. 540 */ 541 struct phy_c45_device_ids { 542 u32 devices_in_package; 543 u32 mmds_present; 544 u32 device_ids[MDIO_MMD_NUM]; 545 }; 546 547 struct macsec_context; 548 struct macsec_ops; 549 550 /** 551 * struct phy_device - An instance of a PHY 552 * 553 * @mdio: MDIO bus this PHY is on 554 * @drv: Pointer to the driver for this PHY instance 555 * @devlink: Create a link between phy dev and mac dev, if the external phy 556 * used by current mac interface is managed by another mac interface. 557 * @phy_id: UID for this device found during discovery 558 * @c45_ids: 802.3-c45 Device Identifiers if is_c45. 559 * @is_c45: Set to true if this PHY uses clause 45 addressing. 560 * @is_internal: Set to true if this PHY is internal to a MAC. 561 * @is_pseudo_fixed_link: Set to true if this PHY is an Ethernet switch, etc. 562 * @is_gigabit_capable: Set to true if PHY supports 1000Mbps 563 * @has_fixups: Set to true if this PHY has fixups/quirks. 564 * @suspended: Set to true if this PHY has been suspended successfully. 565 * @suspended_by_mdio_bus: Set to true if this PHY was suspended by MDIO bus. 566 * @sysfs_links: Internal boolean tracking sysfs symbolic links setup/removal. 567 * @loopback_enabled: Set true if this PHY has been loopbacked successfully. 568 * @downshifted_rate: Set true if link speed has been downshifted. 569 * @is_on_sfp_module: Set true if PHY is located on an SFP module. 570 * @mac_managed_pm: Set true if MAC driver takes of suspending/resuming PHY 571 * @wol_enabled: Set to true if the PHY or the attached MAC have Wake-on-LAN 572 * enabled. 573 * @state: State of the PHY for management purposes 574 * @dev_flags: Device-specific flags used by the PHY driver. 575 * 576 * - Bits [15:0] are free to use by the PHY driver to communicate 577 * driver specific behavior. 578 * - Bits [23:16] are currently reserved for future use. 579 * - Bits [31:24] are reserved for defining generic 580 * PHY driver behavior. 581 * @irq: IRQ number of the PHY's interrupt (-1 if none) 582 * @phylink: Pointer to phylink instance for this PHY 583 * @sfp_bus_attached: Flag indicating whether the SFP bus has been attached 584 * @sfp_bus: SFP bus attached to this PHY's fiber port 585 * @attached_dev: The attached enet driver's device instance ptr 586 * @adjust_link: Callback for the enet controller to respond to changes: in the 587 * link state. 588 * @phy_link_change: Callback for phylink for notification of link change 589 * @macsec_ops: MACsec offloading ops. 590 * 591 * @speed: Current link speed 592 * @duplex: Current duplex 593 * @port: Current port 594 * @pause: Current pause 595 * @asym_pause: Current asymmetric pause 596 * @supported: Combined MAC/PHY supported linkmodes 597 * @advertising: Currently advertised linkmodes 598 * @adv_old: Saved advertised while power saving for WoL 599 * @supported_eee: supported PHY EEE linkmodes 600 * @advertising_eee: Currently advertised EEE linkmodes 601 * @eee_enabled: Flag indicating whether the EEE feature is enabled 602 * @enable_tx_lpi: When True, MAC should transmit LPI to PHY 603 * @eee_cfg: User configuration of EEE 604 * @lp_advertising: Current link partner advertised linkmodes 605 * @host_interfaces: PHY interface modes supported by host 606 * @eee_broken_modes: Energy efficient ethernet modes which should be prohibited 607 * @autoneg: Flag autoneg being used 608 * @rate_matching: Current rate matching mode 609 * @link: Current link state 610 * @autoneg_complete: Flag auto negotiation of the link has completed 611 * @mdix: Current crossover 612 * @mdix_ctrl: User setting of crossover 613 * @pma_extable: Cached value of PMA/PMD Extended Abilities Register 614 * @interrupts: Flag interrupts have been enabled 615 * @irq_suspended: Flag indicating PHY is suspended and therefore interrupt 616 * handling shall be postponed until PHY has resumed 617 * @irq_rerun: Flag indicating interrupts occurred while PHY was suspended, 618 * requiring a rerun of the interrupt handler after resume 619 * @default_timestamp: Flag indicating whether we are using the phy 620 * timestamp as the default one 621 * @interface: enum phy_interface_t value 622 * @possible_interfaces: bitmap if interface modes that the attached PHY 623 * will switch between depending on media speed. 624 * @skb: Netlink message for cable diagnostics 625 * @nest: Netlink nest used for cable diagnostics 626 * @ehdr: nNtlink header for cable diagnostics 627 * @phy_led_triggers: Array of LED triggers 628 * @phy_num_led_triggers: Number of triggers in @phy_led_triggers 629 * @led_link_trigger: LED trigger for link up/down 630 * @last_triggered: last LED trigger for link speed 631 * @leds: list of PHY LED structures 632 * @master_slave_set: User requested master/slave configuration 633 * @master_slave_get: Current master/slave advertisement 634 * @master_slave_state: Current master/slave configuration 635 * @mii_ts: Pointer to time stamper callbacks 636 * @psec: Pointer to Power Sourcing Equipment control struct 637 * @lock: Mutex for serialization access to PHY 638 * @state_queue: Work queue for state machine 639 * @link_down_events: Number of times link was lost 640 * @shared: Pointer to private data shared by phys in one package 641 * @priv: Pointer to driver private data 642 * 643 * interrupts currently only supports enabled or disabled, 644 * but could be changed in the future to support enabling 645 * and disabling specific interrupts 646 * 647 * Contains some infrastructure for polling and interrupt 648 * handling, as well as handling shifts in PHY hardware state 649 */ 650 struct phy_device { 651 struct mdio_device mdio; 652 653 /* Information about the PHY type */ 654 /* And management functions */ 655 const struct phy_driver *drv; 656 657 struct device_link *devlink; 658 659 u32 phy_id; 660 661 struct phy_c45_device_ids c45_ids; 662 unsigned is_c45:1; 663 unsigned is_internal:1; 664 unsigned is_pseudo_fixed_link:1; 665 unsigned is_gigabit_capable:1; 666 unsigned has_fixups:1; 667 unsigned suspended:1; 668 unsigned suspended_by_mdio_bus:1; 669 unsigned sysfs_links:1; 670 unsigned loopback_enabled:1; 671 unsigned downshifted_rate:1; 672 unsigned is_on_sfp_module:1; 673 unsigned mac_managed_pm:1; 674 unsigned wol_enabled:1; 675 676 unsigned autoneg:1; 677 /* The most recently read link state */ 678 unsigned link:1; 679 unsigned autoneg_complete:1; 680 681 /* Interrupts are enabled */ 682 unsigned interrupts:1; 683 unsigned irq_suspended:1; 684 unsigned irq_rerun:1; 685 686 unsigned default_timestamp:1; 687 688 int rate_matching; 689 690 enum phy_state state; 691 692 u32 dev_flags; 693 694 phy_interface_t interface; 695 DECLARE_PHY_INTERFACE_MASK(possible_interfaces); 696 697 /* 698 * forced speed & duplex (no autoneg) 699 * partner speed & duplex & pause (autoneg) 700 */ 701 int speed; 702 int duplex; 703 int port; 704 int pause; 705 int asym_pause; 706 u8 master_slave_get; 707 u8 master_slave_set; 708 u8 master_slave_state; 709 710 /* Union of PHY and Attached devices' supported link modes */ 711 /* See ethtool.h for more info */ 712 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); 713 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); 714 __ETHTOOL_DECLARE_LINK_MODE_MASK(lp_advertising); 715 /* used with phy_speed_down */ 716 __ETHTOOL_DECLARE_LINK_MODE_MASK(adv_old); 717 /* used for eee validation and configuration*/ 718 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported_eee); 719 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising_eee); 720 bool eee_enabled; 721 722 /* Host supported PHY interface types. Should be ignored if empty. */ 723 DECLARE_PHY_INTERFACE_MASK(host_interfaces); 724 725 /* Energy efficient ethernet modes which should be prohibited */ 726 u32 eee_broken_modes; 727 bool enable_tx_lpi; 728 struct eee_config eee_cfg; 729 730 #ifdef CONFIG_LED_TRIGGER_PHY 731 struct phy_led_trigger *phy_led_triggers; 732 unsigned int phy_num_led_triggers; 733 struct phy_led_trigger *last_triggered; 734 735 struct phy_led_trigger *led_link_trigger; 736 #endif 737 struct list_head leds; 738 739 /* 740 * Interrupt number for this PHY 741 * -1 means no interrupt 742 */ 743 int irq; 744 745 /* private data pointer */ 746 /* For use by PHYs to maintain extra state */ 747 void *priv; 748 749 /* shared data pointer */ 750 /* For use by PHYs inside the same package that need a shared state. */ 751 struct phy_package_shared *shared; 752 753 /* Reporting cable test results */ 754 struct sk_buff *skb; 755 void *ehdr; 756 struct nlattr *nest; 757 758 /* Interrupt and Polling infrastructure */ 759 struct delayed_work state_queue; 760 761 struct mutex lock; 762 763 /* This may be modified under the rtnl lock */ 764 bool sfp_bus_attached; 765 struct sfp_bus *sfp_bus; 766 struct phylink *phylink; 767 struct net_device *attached_dev; 768 struct mii_timestamper *mii_ts; 769 struct pse_control *psec; 770 771 u8 mdix; 772 u8 mdix_ctrl; 773 774 int pma_extable; 775 776 unsigned int link_down_events; 777 778 void (*phy_link_change)(struct phy_device *phydev, bool up); 779 void (*adjust_link)(struct net_device *dev); 780 781 #if IS_ENABLED(CONFIG_MACSEC) 782 /* MACsec management functions */ 783 const struct macsec_ops *macsec_ops; 784 #endif 785 }; 786 787 /* Generic phy_device::dev_flags */ 788 #define PHY_F_NO_IRQ 0x80000000 789 #define PHY_F_RXC_ALWAYS_ON 0x40000000 790 791 static inline struct phy_device *to_phy_device(const struct device *dev) 792 { 793 return container_of(to_mdio_device(dev), struct phy_device, mdio); 794 } 795 796 /** 797 * struct phy_tdr_config - Configuration of a TDR raw test 798 * 799 * @first: Distance for first data collection point 800 * @last: Distance for last data collection point 801 * @step: Step between data collection points 802 * @pair: Bitmap of cable pairs to collect data for 803 * 804 * A structure containing possible configuration parameters 805 * for a TDR cable test. The driver does not need to implement 806 * all the parameters, but should report what is actually used. 807 * All distances are in centimeters. 808 */ 809 struct phy_tdr_config { 810 u32 first; 811 u32 last; 812 u32 step; 813 s8 pair; 814 }; 815 #define PHY_PAIR_ALL -1 816 817 /** 818 * struct phy_plca_cfg - Configuration of the PLCA (Physical Layer Collision 819 * Avoidance) Reconciliation Sublayer. 820 * 821 * @version: read-only PLCA register map version. -1 = not available. Ignored 822 * when setting the configuration. Format is the same as reported by the PLCA 823 * IDVER register (31.CA00). -1 = not available. 824 * @enabled: PLCA configured mode (enabled/disabled). -1 = not available / don't 825 * set. 0 = disabled, anything else = enabled. 826 * @node_id: the PLCA local node identifier. -1 = not available / don't set. 827 * Allowed values [0 .. 254]. 255 = node disabled. 828 * @node_cnt: the PLCA node count (maximum number of nodes having a TO). Only 829 * meaningful for the coordinator (node_id = 0). -1 = not available / don't 830 * set. Allowed values [1 .. 255]. 831 * @to_tmr: The value of the PLCA to_timer in bit-times, which determines the 832 * PLCA transmit opportunity window opening. See IEEE802.3 Clause 148 for 833 * more details. The to_timer shall be set equal over all nodes. 834 * -1 = not available / don't set. Allowed values [0 .. 255]. 835 * @burst_cnt: controls how many additional frames a node is allowed to send in 836 * single transmit opportunity (TO). The default value of 0 means that the 837 * node is allowed exactly one frame per TO. A value of 1 allows two frames 838 * per TO, and so on. -1 = not available / don't set. 839 * Allowed values [0 .. 255]. 840 * @burst_tmr: controls how many bit times to wait for the MAC to send a new 841 * frame before interrupting the burst. This value should be set to a value 842 * greater than the MAC inter-packet gap (which is typically 96 bits). 843 * -1 = not available / don't set. Allowed values [0 .. 255]. 844 * 845 * A structure containing configuration parameters for setting/getting the PLCA 846 * RS configuration. The driver does not need to implement all the parameters, 847 * but should report what is actually used. 848 */ 849 struct phy_plca_cfg { 850 int version; 851 int enabled; 852 int node_id; 853 int node_cnt; 854 int to_tmr; 855 int burst_cnt; 856 int burst_tmr; 857 }; 858 859 /** 860 * struct phy_plca_status - Status of the PLCA (Physical Layer Collision 861 * Avoidance) Reconciliation Sublayer. 862 * 863 * @pst: The PLCA status as reported by the PST bit in the PLCA STATUS 864 * register(31.CA03), indicating BEACON activity. 865 * 866 * A structure containing status information of the PLCA RS configuration. 867 * The driver does not need to implement all the parameters, but should report 868 * what is actually used. 869 */ 870 struct phy_plca_status { 871 bool pst; 872 }; 873 874 /* Modes for PHY LED configuration */ 875 enum phy_led_modes { 876 PHY_LED_ACTIVE_LOW = 0, 877 PHY_LED_INACTIVE_HIGH_IMPEDANCE = 1, 878 879 /* keep it last */ 880 __PHY_LED_MODES_NUM, 881 }; 882 883 /** 884 * struct phy_led: An LED driven by the PHY 885 * 886 * @list: List of LEDs 887 * @phydev: PHY this LED is attached to 888 * @led_cdev: Standard LED class structure 889 * @index: Number of the LED 890 */ 891 struct phy_led { 892 struct list_head list; 893 struct phy_device *phydev; 894 struct led_classdev led_cdev; 895 u8 index; 896 }; 897 898 #define to_phy_led(d) container_of(d, struct phy_led, led_cdev) 899 900 /** 901 * struct phy_driver - Driver structure for a particular PHY type 902 * 903 * @mdiodrv: Data common to all MDIO devices 904 * @phy_id: The result of reading the UID registers of this PHY 905 * type, and ANDing them with the phy_id_mask. This driver 906 * only works for PHYs with IDs which match this field 907 * @name: The friendly name of this PHY type 908 * @phy_id_mask: Defines the important bits of the phy_id 909 * @features: A mandatory list of features (speed, duplex, etc) 910 * supported by this PHY 911 * @flags: A bitfield defining certain other features this PHY 912 * supports (like interrupts) 913 * @driver_data: Static driver data 914 * 915 * All functions are optional. If config_aneg or read_status 916 * are not implemented, the phy core uses the genphy versions. 917 * Note that none of these functions should be called from 918 * interrupt time. The goal is for the bus read/write functions 919 * to be able to block when the bus transaction is happening, 920 * and be freed up by an interrupt (The MPC85xx has this ability, 921 * though it is not currently supported in the driver). 922 */ 923 struct phy_driver { 924 struct mdio_driver_common mdiodrv; 925 u32 phy_id; 926 char *name; 927 u32 phy_id_mask; 928 const unsigned long * const features; 929 u32 flags; 930 const void *driver_data; 931 932 /** 933 * @soft_reset: Called to issue a PHY software reset 934 */ 935 int (*soft_reset)(struct phy_device *phydev); 936 937 /** 938 * @config_init: Called to initialize the PHY, 939 * including after a reset 940 */ 941 int (*config_init)(struct phy_device *phydev); 942 943 /** 944 * @probe: Called during discovery. Used to set 945 * up device-specific structures, if any 946 */ 947 int (*probe)(struct phy_device *phydev); 948 949 /** 950 * @get_features: Probe the hardware to determine what 951 * abilities it has. Should only set phydev->supported. 952 */ 953 int (*get_features)(struct phy_device *phydev); 954 955 /** 956 * @get_rate_matching: Get the supported type of rate matching for a 957 * particular phy interface. This is used by phy consumers to determine 958 * whether to advertise lower-speed modes for that interface. It is 959 * assumed that if a rate matching mode is supported on an interface, 960 * then that interface's rate can be adapted to all slower link speeds 961 * supported by the phy. If the interface is not supported, this should 962 * return %RATE_MATCH_NONE. 963 */ 964 int (*get_rate_matching)(struct phy_device *phydev, 965 phy_interface_t iface); 966 967 /* PHY Power Management */ 968 /** @suspend: Suspend the hardware, saving state if needed */ 969 int (*suspend)(struct phy_device *phydev); 970 /** @resume: Resume the hardware, restoring state if needed */ 971 int (*resume)(struct phy_device *phydev); 972 973 /** 974 * @config_aneg: Configures the advertisement and resets 975 * autonegotiation if phydev->autoneg is on, 976 * forces the speed to the current settings in phydev 977 * if phydev->autoneg is off 978 */ 979 int (*config_aneg)(struct phy_device *phydev); 980 981 /** @aneg_done: Determines the auto negotiation result */ 982 int (*aneg_done)(struct phy_device *phydev); 983 984 /** @read_status: Determines the negotiated speed and duplex */ 985 int (*read_status)(struct phy_device *phydev); 986 987 /** 988 * @config_intr: Enables or disables interrupts. 989 * It should also clear any pending interrupts prior to enabling the 990 * IRQs and after disabling them. 991 */ 992 int (*config_intr)(struct phy_device *phydev); 993 994 /** @handle_interrupt: Override default interrupt handling */ 995 irqreturn_t (*handle_interrupt)(struct phy_device *phydev); 996 997 /** @remove: Clears up any memory if needed */ 998 void (*remove)(struct phy_device *phydev); 999 1000 /** 1001 * @match_phy_device: Returns true if this is a suitable 1002 * driver for the given phydev. If NULL, matching is based on 1003 * phy_id and phy_id_mask. 1004 */ 1005 int (*match_phy_device)(struct phy_device *phydev); 1006 1007 /** 1008 * @set_wol: Some devices (e.g. qnap TS-119P II) require PHY 1009 * register changes to enable Wake on LAN, so set_wol is 1010 * provided to be called in the ethernet driver's set_wol 1011 * function. 1012 */ 1013 int (*set_wol)(struct phy_device *dev, struct ethtool_wolinfo *wol); 1014 1015 /** 1016 * @get_wol: See set_wol, but for checking whether Wake on LAN 1017 * is enabled. 1018 */ 1019 void (*get_wol)(struct phy_device *dev, struct ethtool_wolinfo *wol); 1020 1021 /** 1022 * @link_change_notify: Called to inform a PHY device driver 1023 * when the core is about to change the link state. This 1024 * callback is supposed to be used as fixup hook for drivers 1025 * that need to take action when the link state 1026 * changes. Drivers are by no means allowed to mess with the 1027 * PHY device structure in their implementations. 1028 */ 1029 void (*link_change_notify)(struct phy_device *dev); 1030 1031 /** 1032 * @read_mmd: PHY specific driver override for reading a MMD 1033 * register. This function is optional for PHY specific 1034 * drivers. When not provided, the default MMD read function 1035 * will be used by phy_read_mmd(), which will use either a 1036 * direct read for Clause 45 PHYs or an indirect read for 1037 * Clause 22 PHYs. devnum is the MMD device number within the 1038 * PHY device, regnum is the register within the selected MMD 1039 * device. 1040 */ 1041 int (*read_mmd)(struct phy_device *dev, int devnum, u16 regnum); 1042 1043 /** 1044 * @write_mmd: PHY specific driver override for writing a MMD 1045 * register. This function is optional for PHY specific 1046 * drivers. When not provided, the default MMD write function 1047 * will be used by phy_write_mmd(), which will use either a 1048 * direct write for Clause 45 PHYs, or an indirect write for 1049 * Clause 22 PHYs. devnum is the MMD device number within the 1050 * PHY device, regnum is the register within the selected MMD 1051 * device. val is the value to be written. 1052 */ 1053 int (*write_mmd)(struct phy_device *dev, int devnum, u16 regnum, 1054 u16 val); 1055 1056 /** @read_page: Return the current PHY register page number */ 1057 int (*read_page)(struct phy_device *dev); 1058 /** @write_page: Set the current PHY register page number */ 1059 int (*write_page)(struct phy_device *dev, int page); 1060 1061 /** 1062 * @module_info: Get the size and type of the eeprom contained 1063 * within a plug-in module 1064 */ 1065 int (*module_info)(struct phy_device *dev, 1066 struct ethtool_modinfo *modinfo); 1067 1068 /** 1069 * @module_eeprom: Get the eeprom information from the plug-in 1070 * module 1071 */ 1072 int (*module_eeprom)(struct phy_device *dev, 1073 struct ethtool_eeprom *ee, u8 *data); 1074 1075 /** @cable_test_start: Start a cable test */ 1076 int (*cable_test_start)(struct phy_device *dev); 1077 1078 /** @cable_test_tdr_start: Start a raw TDR cable test */ 1079 int (*cable_test_tdr_start)(struct phy_device *dev, 1080 const struct phy_tdr_config *config); 1081 1082 /** 1083 * @cable_test_get_status: Once per second, or on interrupt, 1084 * request the status of the test. 1085 */ 1086 int (*cable_test_get_status)(struct phy_device *dev, bool *finished); 1087 1088 /* Get statistics from the PHY using ethtool */ 1089 /** @get_sset_count: Number of statistic counters */ 1090 int (*get_sset_count)(struct phy_device *dev); 1091 /** @get_strings: Names of the statistic counters */ 1092 void (*get_strings)(struct phy_device *dev, u8 *data); 1093 /** @get_stats: Return the statistic counter values */ 1094 void (*get_stats)(struct phy_device *dev, 1095 struct ethtool_stats *stats, u64 *data); 1096 1097 /* Get and Set PHY tunables */ 1098 /** @get_tunable: Return the value of a tunable */ 1099 int (*get_tunable)(struct phy_device *dev, 1100 struct ethtool_tunable *tuna, void *data); 1101 /** @set_tunable: Set the value of a tunable */ 1102 int (*set_tunable)(struct phy_device *dev, 1103 struct ethtool_tunable *tuna, 1104 const void *data); 1105 /** @set_loopback: Set the loopback mood of the PHY */ 1106 int (*set_loopback)(struct phy_device *dev, bool enable); 1107 /** @get_sqi: Get the signal quality indication */ 1108 int (*get_sqi)(struct phy_device *dev); 1109 /** @get_sqi_max: Get the maximum signal quality indication */ 1110 int (*get_sqi_max)(struct phy_device *dev); 1111 1112 /* PLCA RS interface */ 1113 /** @get_plca_cfg: Return the current PLCA configuration */ 1114 int (*get_plca_cfg)(struct phy_device *dev, 1115 struct phy_plca_cfg *plca_cfg); 1116 /** @set_plca_cfg: Set the PLCA configuration */ 1117 int (*set_plca_cfg)(struct phy_device *dev, 1118 const struct phy_plca_cfg *plca_cfg); 1119 /** @get_plca_status: Return the current PLCA status info */ 1120 int (*get_plca_status)(struct phy_device *dev, 1121 struct phy_plca_status *plca_st); 1122 1123 /** 1124 * @led_brightness_set: Set a PHY LED brightness. Index 1125 * indicates which of the PHYs led should be set. Value 1126 * follows the standard LED class meaning, e.g. LED_OFF, 1127 * LED_HALF, LED_FULL. 1128 */ 1129 int (*led_brightness_set)(struct phy_device *dev, 1130 u8 index, enum led_brightness value); 1131 1132 /** 1133 * @led_blink_set: Set a PHY LED blinking. Index indicates 1134 * which of the PHYs led should be configured to blink. Delays 1135 * are in milliseconds and if both are zero then a sensible 1136 * default should be chosen. The call should adjust the 1137 * timings in that case and if it can't match the values 1138 * specified exactly. 1139 */ 1140 int (*led_blink_set)(struct phy_device *dev, u8 index, 1141 unsigned long *delay_on, 1142 unsigned long *delay_off); 1143 /** 1144 * @led_hw_is_supported: Can the HW support the given rules. 1145 * @dev: PHY device which has the LED 1146 * @index: Which LED of the PHY device 1147 * @rules The core is interested in these rules 1148 * 1149 * Return 0 if yes, -EOPNOTSUPP if not, or an error code. 1150 */ 1151 int (*led_hw_is_supported)(struct phy_device *dev, u8 index, 1152 unsigned long rules); 1153 /** 1154 * @led_hw_control_set: Set the HW to control the LED 1155 * @dev: PHY device which has the LED 1156 * @index: Which LED of the PHY device 1157 * @rules The rules used to control the LED 1158 * 1159 * Returns 0, or a an error code. 1160 */ 1161 int (*led_hw_control_set)(struct phy_device *dev, u8 index, 1162 unsigned long rules); 1163 /** 1164 * @led_hw_control_get: Get how the HW is controlling the LED 1165 * @dev: PHY device which has the LED 1166 * @index: Which LED of the PHY device 1167 * @rules Pointer to the rules used to control the LED 1168 * 1169 * Set *@rules to how the HW is currently blinking. Returns 0 1170 * on success, or a error code if the current blinking cannot 1171 * be represented in rules, or some other error happens. 1172 */ 1173 int (*led_hw_control_get)(struct phy_device *dev, u8 index, 1174 unsigned long *rules); 1175 1176 /** 1177 * @led_polarity_set: Set the LED polarity modes 1178 * @dev: PHY device which has the LED 1179 * @index: Which LED of the PHY device 1180 * @modes: bitmap of LED polarity modes 1181 * 1182 * Configure LED with all the required polarity modes in @modes 1183 * to make it correctly turn ON or OFF. 1184 * 1185 * Returns 0, or an error code. 1186 */ 1187 int (*led_polarity_set)(struct phy_device *dev, int index, 1188 unsigned long modes); 1189 }; 1190 #define to_phy_driver(d) container_of_const(to_mdio_common_driver(d), \ 1191 struct phy_driver, mdiodrv) 1192 1193 #define PHY_ANY_ID "MATCH ANY PHY" 1194 #define PHY_ANY_UID 0xffffffff 1195 1196 #define PHY_ID_MATCH_EXACT(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 0) 1197 #define PHY_ID_MATCH_MODEL(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 4) 1198 #define PHY_ID_MATCH_VENDOR(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 10) 1199 1200 /** 1201 * phy_id_compare - compare @id1 with @id2 taking account of @mask 1202 * @id1: first PHY ID 1203 * @id2: second PHY ID 1204 * @mask: the PHY ID mask, set bits are significant in matching 1205 * 1206 * Return true if the bits from @id1 and @id2 specified by @mask match. 1207 * This uses an equivalent test to (@id & @mask) == (@phy_id & @mask). 1208 */ 1209 static inline bool phy_id_compare(u32 id1, u32 id2, u32 mask) 1210 { 1211 return !((id1 ^ id2) & mask); 1212 } 1213 1214 /** 1215 * phydev_id_compare - compare @id with the PHY's Clause 22 ID 1216 * @phydev: the PHY device 1217 * @id: the PHY ID to be matched 1218 * 1219 * Compare the @phydev clause 22 ID with the provided @id and return true or 1220 * false depending whether it matches, using the bound driver mask. The 1221 * @phydev must be bound to a driver. 1222 */ 1223 static inline bool phydev_id_compare(struct phy_device *phydev, u32 id) 1224 { 1225 return phy_id_compare(id, phydev->phy_id, phydev->drv->phy_id_mask); 1226 } 1227 1228 /* A Structure for boards to register fixups with the PHY Lib */ 1229 struct phy_fixup { 1230 struct list_head list; 1231 char bus_id[MII_BUS_ID_SIZE + 3]; 1232 u32 phy_uid; 1233 u32 phy_uid_mask; 1234 int (*run)(struct phy_device *phydev); 1235 }; 1236 1237 const char *phy_speed_to_str(int speed); 1238 const char *phy_duplex_to_str(unsigned int duplex); 1239 const char *phy_rate_matching_to_str(int rate_matching); 1240 1241 int phy_interface_num_ports(phy_interface_t interface); 1242 1243 /* A structure for mapping a particular speed and duplex 1244 * combination to a particular SUPPORTED and ADVERTISED value 1245 */ 1246 struct phy_setting { 1247 u32 speed; 1248 u8 duplex; 1249 u8 bit; 1250 }; 1251 1252 const struct phy_setting * 1253 phy_lookup_setting(int speed, int duplex, const unsigned long *mask, 1254 bool exact); 1255 size_t phy_speeds(unsigned int *speeds, size_t size, 1256 unsigned long *mask); 1257 void of_set_phy_supported(struct phy_device *phydev); 1258 void of_set_phy_eee_broken(struct phy_device *phydev); 1259 int phy_speed_down_core(struct phy_device *phydev); 1260 1261 /** 1262 * phy_is_started - Convenience function to check whether PHY is started 1263 * @phydev: The phy_device struct 1264 */ 1265 static inline bool phy_is_started(struct phy_device *phydev) 1266 { 1267 return phydev->state >= PHY_UP; 1268 } 1269 1270 void phy_resolve_aneg_pause(struct phy_device *phydev); 1271 void phy_resolve_aneg_linkmode(struct phy_device *phydev); 1272 void phy_check_downshift(struct phy_device *phydev); 1273 1274 /** 1275 * phy_read - Convenience function for reading a given PHY register 1276 * @phydev: the phy_device struct 1277 * @regnum: register number to read 1278 * 1279 * NOTE: MUST NOT be called from interrupt context, 1280 * because the bus read/write functions may wait for an interrupt 1281 * to conclude the operation. 1282 */ 1283 static inline int phy_read(struct phy_device *phydev, u32 regnum) 1284 { 1285 return mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, regnum); 1286 } 1287 1288 #define phy_read_poll_timeout(phydev, regnum, val, cond, sleep_us, \ 1289 timeout_us, sleep_before_read) \ 1290 ({ \ 1291 int __ret, __val; \ 1292 __ret = read_poll_timeout(__val = phy_read, val, \ 1293 __val < 0 || (cond), \ 1294 sleep_us, timeout_us, sleep_before_read, phydev, regnum); \ 1295 if (__val < 0) \ 1296 __ret = __val; \ 1297 if (__ret) \ 1298 phydev_err(phydev, "%s failed: %d\n", __func__, __ret); \ 1299 __ret; \ 1300 }) 1301 1302 /** 1303 * __phy_read - convenience function for reading a given PHY register 1304 * @phydev: the phy_device struct 1305 * @regnum: register number to read 1306 * 1307 * The caller must have taken the MDIO bus lock. 1308 */ 1309 static inline int __phy_read(struct phy_device *phydev, u32 regnum) 1310 { 1311 return __mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, regnum); 1312 } 1313 1314 /** 1315 * phy_write - Convenience function for writing a given PHY register 1316 * @phydev: the phy_device struct 1317 * @regnum: register number to write 1318 * @val: value to write to @regnum 1319 * 1320 * NOTE: MUST NOT be called from interrupt context, 1321 * because the bus read/write functions may wait for an interrupt 1322 * to conclude the operation. 1323 */ 1324 static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val) 1325 { 1326 return mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, regnum, val); 1327 } 1328 1329 /** 1330 * __phy_write - Convenience function for writing a given PHY register 1331 * @phydev: the phy_device struct 1332 * @regnum: register number to write 1333 * @val: value to write to @regnum 1334 * 1335 * The caller must have taken the MDIO bus lock. 1336 */ 1337 static inline int __phy_write(struct phy_device *phydev, u32 regnum, u16 val) 1338 { 1339 return __mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, regnum, 1340 val); 1341 } 1342 1343 /** 1344 * __phy_modify_changed() - Convenience function for modifying a PHY register 1345 * @phydev: a pointer to a &struct phy_device 1346 * @regnum: register number 1347 * @mask: bit mask of bits to clear 1348 * @set: bit mask of bits to set 1349 * 1350 * Unlocked helper function which allows a PHY register to be modified as 1351 * new register value = (old register value & ~mask) | set 1352 * 1353 * Returns negative errno, 0 if there was no change, and 1 in case of change 1354 */ 1355 static inline int __phy_modify_changed(struct phy_device *phydev, u32 regnum, 1356 u16 mask, u16 set) 1357 { 1358 return __mdiobus_modify_changed(phydev->mdio.bus, phydev->mdio.addr, 1359 regnum, mask, set); 1360 } 1361 1362 /* 1363 * phy_read_mmd - Convenience function for reading a register 1364 * from an MMD on a given PHY. 1365 */ 1366 int phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum); 1367 1368 /** 1369 * phy_read_mmd_poll_timeout - Periodically poll a PHY register until a 1370 * condition is met or a timeout occurs 1371 * 1372 * @phydev: The phy_device struct 1373 * @devaddr: The MMD to read from 1374 * @regnum: The register on the MMD to read 1375 * @val: Variable to read the register into 1376 * @cond: Break condition (usually involving @val) 1377 * @sleep_us: Maximum time to sleep between reads in us (0 1378 * tight-loops). Should be less than ~20ms since usleep_range 1379 * is used (see Documentation/timers/timers-howto.rst). 1380 * @timeout_us: Timeout in us, 0 means never timeout 1381 * @sleep_before_read: if it is true, sleep @sleep_us before read. 1382 * Returns 0 on success and -ETIMEDOUT upon a timeout. In either 1383 * case, the last read value at @args is stored in @val. Must not 1384 * be called from atomic context if sleep_us or timeout_us are used. 1385 */ 1386 #define phy_read_mmd_poll_timeout(phydev, devaddr, regnum, val, cond, \ 1387 sleep_us, timeout_us, sleep_before_read) \ 1388 ({ \ 1389 int __ret, __val; \ 1390 __ret = read_poll_timeout(__val = phy_read_mmd, val, \ 1391 __val < 0 || (cond), \ 1392 sleep_us, timeout_us, sleep_before_read, \ 1393 phydev, devaddr, regnum); \ 1394 if (__val < 0) \ 1395 __ret = __val; \ 1396 if (__ret) \ 1397 phydev_err(phydev, "%s failed: %d\n", __func__, __ret); \ 1398 __ret; \ 1399 }) 1400 1401 /* 1402 * __phy_read_mmd - Convenience function for reading a register 1403 * from an MMD on a given PHY. 1404 */ 1405 int __phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum); 1406 1407 /* 1408 * phy_write_mmd - Convenience function for writing a register 1409 * on an MMD on a given PHY. 1410 */ 1411 int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val); 1412 1413 /* 1414 * __phy_write_mmd - Convenience function for writing a register 1415 * on an MMD on a given PHY. 1416 */ 1417 int __phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val); 1418 1419 int __phy_modify_changed(struct phy_device *phydev, u32 regnum, u16 mask, 1420 u16 set); 1421 int phy_modify_changed(struct phy_device *phydev, u32 regnum, u16 mask, 1422 u16 set); 1423 int __phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set); 1424 int phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set); 1425 1426 int __phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum, 1427 u16 mask, u16 set); 1428 int phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum, 1429 u16 mask, u16 set); 1430 int __phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum, 1431 u16 mask, u16 set); 1432 int phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum, 1433 u16 mask, u16 set); 1434 1435 /** 1436 * __phy_set_bits - Convenience function for setting bits in a PHY register 1437 * @phydev: the phy_device struct 1438 * @regnum: register number to write 1439 * @val: bits to set 1440 * 1441 * The caller must have taken the MDIO bus lock. 1442 */ 1443 static inline int __phy_set_bits(struct phy_device *phydev, u32 regnum, u16 val) 1444 { 1445 return __phy_modify(phydev, regnum, 0, val); 1446 } 1447 1448 /** 1449 * __phy_clear_bits - Convenience function for clearing bits in a PHY register 1450 * @phydev: the phy_device struct 1451 * @regnum: register number to write 1452 * @val: bits to clear 1453 * 1454 * The caller must have taken the MDIO bus lock. 1455 */ 1456 static inline int __phy_clear_bits(struct phy_device *phydev, u32 regnum, 1457 u16 val) 1458 { 1459 return __phy_modify(phydev, regnum, val, 0); 1460 } 1461 1462 /** 1463 * phy_set_bits - Convenience function for setting bits in a PHY register 1464 * @phydev: the phy_device struct 1465 * @regnum: register number to write 1466 * @val: bits to set 1467 */ 1468 static inline int phy_set_bits(struct phy_device *phydev, u32 regnum, u16 val) 1469 { 1470 return phy_modify(phydev, regnum, 0, val); 1471 } 1472 1473 /** 1474 * phy_clear_bits - Convenience function for clearing bits in a PHY register 1475 * @phydev: the phy_device struct 1476 * @regnum: register number to write 1477 * @val: bits to clear 1478 */ 1479 static inline int phy_clear_bits(struct phy_device *phydev, u32 regnum, u16 val) 1480 { 1481 return phy_modify(phydev, regnum, val, 0); 1482 } 1483 1484 /** 1485 * __phy_set_bits_mmd - Convenience function for setting bits in a register 1486 * on MMD 1487 * @phydev: the phy_device struct 1488 * @devad: the MMD containing register to modify 1489 * @regnum: register number to modify 1490 * @val: bits to set 1491 * 1492 * The caller must have taken the MDIO bus lock. 1493 */ 1494 static inline int __phy_set_bits_mmd(struct phy_device *phydev, int devad, 1495 u32 regnum, u16 val) 1496 { 1497 return __phy_modify_mmd(phydev, devad, regnum, 0, val); 1498 } 1499 1500 /** 1501 * __phy_clear_bits_mmd - Convenience function for clearing bits in a register 1502 * on MMD 1503 * @phydev: the phy_device struct 1504 * @devad: the MMD containing register to modify 1505 * @regnum: register number to modify 1506 * @val: bits to clear 1507 * 1508 * The caller must have taken the MDIO bus lock. 1509 */ 1510 static inline int __phy_clear_bits_mmd(struct phy_device *phydev, int devad, 1511 u32 regnum, u16 val) 1512 { 1513 return __phy_modify_mmd(phydev, devad, regnum, val, 0); 1514 } 1515 1516 /** 1517 * phy_set_bits_mmd - Convenience function for setting bits in a register 1518 * on MMD 1519 * @phydev: the phy_device struct 1520 * @devad: the MMD containing register to modify 1521 * @regnum: register number to modify 1522 * @val: bits to set 1523 */ 1524 static inline int phy_set_bits_mmd(struct phy_device *phydev, int devad, 1525 u32 regnum, u16 val) 1526 { 1527 return phy_modify_mmd(phydev, devad, regnum, 0, val); 1528 } 1529 1530 /** 1531 * phy_clear_bits_mmd - Convenience function for clearing bits in a register 1532 * on MMD 1533 * @phydev: the phy_device struct 1534 * @devad: the MMD containing register to modify 1535 * @regnum: register number to modify 1536 * @val: bits to clear 1537 */ 1538 static inline int phy_clear_bits_mmd(struct phy_device *phydev, int devad, 1539 u32 regnum, u16 val) 1540 { 1541 return phy_modify_mmd(phydev, devad, regnum, val, 0); 1542 } 1543 1544 /** 1545 * phy_interrupt_is_valid - Convenience function for testing a given PHY irq 1546 * @phydev: the phy_device struct 1547 * 1548 * NOTE: must be kept in sync with addition/removal of PHY_POLL and 1549 * PHY_MAC_INTERRUPT 1550 */ 1551 static inline bool phy_interrupt_is_valid(struct phy_device *phydev) 1552 { 1553 return phydev->irq != PHY_POLL && phydev->irq != PHY_MAC_INTERRUPT; 1554 } 1555 1556 /** 1557 * phy_polling_mode - Convenience function for testing whether polling is 1558 * used to detect PHY status changes 1559 * @phydev: the phy_device struct 1560 */ 1561 static inline bool phy_polling_mode(struct phy_device *phydev) 1562 { 1563 if (phydev->state == PHY_CABLETEST) 1564 if (phydev->drv->flags & PHY_POLL_CABLE_TEST) 1565 return true; 1566 1567 return phydev->irq == PHY_POLL; 1568 } 1569 1570 /** 1571 * phy_has_hwtstamp - Tests whether a PHY time stamp configuration. 1572 * @phydev: the phy_device struct 1573 */ 1574 static inline bool phy_has_hwtstamp(struct phy_device *phydev) 1575 { 1576 return phydev && phydev->mii_ts && phydev->mii_ts->hwtstamp; 1577 } 1578 1579 /** 1580 * phy_has_rxtstamp - Tests whether a PHY supports receive time stamping. 1581 * @phydev: the phy_device struct 1582 */ 1583 static inline bool phy_has_rxtstamp(struct phy_device *phydev) 1584 { 1585 return phydev && phydev->mii_ts && phydev->mii_ts->rxtstamp; 1586 } 1587 1588 /** 1589 * phy_has_tsinfo - Tests whether a PHY reports time stamping and/or 1590 * PTP hardware clock capabilities. 1591 * @phydev: the phy_device struct 1592 */ 1593 static inline bool phy_has_tsinfo(struct phy_device *phydev) 1594 { 1595 return phydev && phydev->mii_ts && phydev->mii_ts->ts_info; 1596 } 1597 1598 /** 1599 * phy_has_txtstamp - Tests whether a PHY supports transmit time stamping. 1600 * @phydev: the phy_device struct 1601 */ 1602 static inline bool phy_has_txtstamp(struct phy_device *phydev) 1603 { 1604 return phydev && phydev->mii_ts && phydev->mii_ts->txtstamp; 1605 } 1606 1607 static inline int phy_hwtstamp(struct phy_device *phydev, 1608 struct kernel_hwtstamp_config *cfg, 1609 struct netlink_ext_ack *extack) 1610 { 1611 return phydev->mii_ts->hwtstamp(phydev->mii_ts, cfg, extack); 1612 } 1613 1614 static inline bool phy_rxtstamp(struct phy_device *phydev, struct sk_buff *skb, 1615 int type) 1616 { 1617 return phydev->mii_ts->rxtstamp(phydev->mii_ts, skb, type); 1618 } 1619 1620 static inline int phy_ts_info(struct phy_device *phydev, 1621 struct kernel_ethtool_ts_info *tsinfo) 1622 { 1623 return phydev->mii_ts->ts_info(phydev->mii_ts, tsinfo); 1624 } 1625 1626 static inline void phy_txtstamp(struct phy_device *phydev, struct sk_buff *skb, 1627 int type) 1628 { 1629 phydev->mii_ts->txtstamp(phydev->mii_ts, skb, type); 1630 } 1631 1632 /** 1633 * phy_is_default_hwtstamp - Is the PHY hwtstamp the default timestamp 1634 * @phydev: Pointer to phy_device 1635 * 1636 * This is used to get default timestamping device taking into account 1637 * the new API choice, which is selecting the timestamping from MAC by 1638 * default if the phydev does not have default_timestamp flag enabled. 1639 * 1640 * Return: True if phy is the default hw timestamp, false otherwise. 1641 */ 1642 static inline bool phy_is_default_hwtstamp(struct phy_device *phydev) 1643 { 1644 return phy_has_hwtstamp(phydev) && phydev->default_timestamp; 1645 } 1646 1647 /** 1648 * phy_is_internal - Convenience function for testing if a PHY is internal 1649 * @phydev: the phy_device struct 1650 */ 1651 static inline bool phy_is_internal(struct phy_device *phydev) 1652 { 1653 return phydev->is_internal; 1654 } 1655 1656 /** 1657 * phy_on_sfp - Convenience function for testing if a PHY is on an SFP module 1658 * @phydev: the phy_device struct 1659 */ 1660 static inline bool phy_on_sfp(struct phy_device *phydev) 1661 { 1662 return phydev->is_on_sfp_module; 1663 } 1664 1665 /** 1666 * phy_interface_mode_is_rgmii - Convenience function for testing if a 1667 * PHY interface mode is RGMII (all variants) 1668 * @mode: the &phy_interface_t enum 1669 */ 1670 static inline bool phy_interface_mode_is_rgmii(phy_interface_t mode) 1671 { 1672 return mode >= PHY_INTERFACE_MODE_RGMII && 1673 mode <= PHY_INTERFACE_MODE_RGMII_TXID; 1674 }; 1675 1676 /** 1677 * phy_interface_mode_is_8023z() - does the PHY interface mode use 802.3z 1678 * negotiation 1679 * @mode: one of &enum phy_interface_t 1680 * 1681 * Returns true if the PHY interface mode uses the 16-bit negotiation 1682 * word as defined in 802.3z. (See 802.3-2015 37.2.1 Config_Reg encoding) 1683 */ 1684 static inline bool phy_interface_mode_is_8023z(phy_interface_t mode) 1685 { 1686 return mode == PHY_INTERFACE_MODE_1000BASEX || 1687 mode == PHY_INTERFACE_MODE_2500BASEX; 1688 } 1689 1690 /** 1691 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface 1692 * is RGMII (all variants) 1693 * @phydev: the phy_device struct 1694 */ 1695 static inline bool phy_interface_is_rgmii(struct phy_device *phydev) 1696 { 1697 return phy_interface_mode_is_rgmii(phydev->interface); 1698 }; 1699 1700 /** 1701 * phy_is_pseudo_fixed_link - Convenience function for testing if this 1702 * PHY is the CPU port facing side of an Ethernet switch, or similar. 1703 * @phydev: the phy_device struct 1704 */ 1705 static inline bool phy_is_pseudo_fixed_link(struct phy_device *phydev) 1706 { 1707 return phydev->is_pseudo_fixed_link; 1708 } 1709 1710 int phy_save_page(struct phy_device *phydev); 1711 int phy_select_page(struct phy_device *phydev, int page); 1712 int phy_restore_page(struct phy_device *phydev, int oldpage, int ret); 1713 int phy_read_paged(struct phy_device *phydev, int page, u32 regnum); 1714 int phy_write_paged(struct phy_device *phydev, int page, u32 regnum, u16 val); 1715 int phy_modify_paged_changed(struct phy_device *phydev, int page, u32 regnum, 1716 u16 mask, u16 set); 1717 int phy_modify_paged(struct phy_device *phydev, int page, u32 regnum, 1718 u16 mask, u16 set); 1719 1720 struct phy_device *phy_device_create(struct mii_bus *bus, int addr, u32 phy_id, 1721 bool is_c45, 1722 struct phy_c45_device_ids *c45_ids); 1723 #if IS_ENABLED(CONFIG_PHYLIB) 1724 int fwnode_get_phy_id(struct fwnode_handle *fwnode, u32 *phy_id); 1725 struct mdio_device *fwnode_mdio_find_device(struct fwnode_handle *fwnode); 1726 struct phy_device *fwnode_phy_find_device(struct fwnode_handle *phy_fwnode); 1727 struct phy_device *device_phy_find_device(struct device *dev); 1728 struct fwnode_handle *fwnode_get_phy_node(const struct fwnode_handle *fwnode); 1729 struct phy_device *get_phy_device(struct mii_bus *bus, int addr, bool is_c45); 1730 int phy_device_register(struct phy_device *phy); 1731 void phy_device_free(struct phy_device *phydev); 1732 #else 1733 static inline int fwnode_get_phy_id(struct fwnode_handle *fwnode, u32 *phy_id) 1734 { 1735 return 0; 1736 } 1737 static inline 1738 struct mdio_device *fwnode_mdio_find_device(struct fwnode_handle *fwnode) 1739 { 1740 return 0; 1741 } 1742 1743 static inline 1744 struct phy_device *fwnode_phy_find_device(struct fwnode_handle *phy_fwnode) 1745 { 1746 return NULL; 1747 } 1748 1749 static inline struct phy_device *device_phy_find_device(struct device *dev) 1750 { 1751 return NULL; 1752 } 1753 1754 static inline 1755 struct fwnode_handle *fwnode_get_phy_node(struct fwnode_handle *fwnode) 1756 { 1757 return NULL; 1758 } 1759 1760 static inline 1761 struct phy_device *get_phy_device(struct mii_bus *bus, int addr, bool is_c45) 1762 { 1763 return NULL; 1764 } 1765 1766 static inline int phy_device_register(struct phy_device *phy) 1767 { 1768 return 0; 1769 } 1770 1771 static inline void phy_device_free(struct phy_device *phydev) { } 1772 #endif /* CONFIG_PHYLIB */ 1773 void phy_device_remove(struct phy_device *phydev); 1774 int phy_get_c45_ids(struct phy_device *phydev); 1775 int phy_init_hw(struct phy_device *phydev); 1776 int phy_suspend(struct phy_device *phydev); 1777 int phy_resume(struct phy_device *phydev); 1778 int __phy_resume(struct phy_device *phydev); 1779 int phy_loopback(struct phy_device *phydev, bool enable); 1780 void phy_sfp_attach(void *upstream, struct sfp_bus *bus); 1781 void phy_sfp_detach(void *upstream, struct sfp_bus *bus); 1782 int phy_sfp_probe(struct phy_device *phydev, 1783 const struct sfp_upstream_ops *ops); 1784 struct phy_device *phy_attach(struct net_device *dev, const char *bus_id, 1785 phy_interface_t interface); 1786 struct phy_device *phy_find_first(struct mii_bus *bus); 1787 int phy_attach_direct(struct net_device *dev, struct phy_device *phydev, 1788 u32 flags, phy_interface_t interface); 1789 int phy_connect_direct(struct net_device *dev, struct phy_device *phydev, 1790 void (*handler)(struct net_device *), 1791 phy_interface_t interface); 1792 struct phy_device *phy_connect(struct net_device *dev, const char *bus_id, 1793 void (*handler)(struct net_device *), 1794 phy_interface_t interface); 1795 void phy_disconnect(struct phy_device *phydev); 1796 void phy_detach(struct phy_device *phydev); 1797 void phy_start(struct phy_device *phydev); 1798 void phy_stop(struct phy_device *phydev); 1799 int phy_config_aneg(struct phy_device *phydev); 1800 int _phy_start_aneg(struct phy_device *phydev); 1801 int phy_start_aneg(struct phy_device *phydev); 1802 int phy_aneg_done(struct phy_device *phydev); 1803 int phy_speed_down(struct phy_device *phydev, bool sync); 1804 int phy_speed_up(struct phy_device *phydev); 1805 bool phy_check_valid(int speed, int duplex, unsigned long *features); 1806 1807 int phy_restart_aneg(struct phy_device *phydev); 1808 int phy_reset_after_clk_enable(struct phy_device *phydev); 1809 1810 #if IS_ENABLED(CONFIG_PHYLIB) 1811 int phy_start_cable_test(struct phy_device *phydev, 1812 struct netlink_ext_ack *extack); 1813 int phy_start_cable_test_tdr(struct phy_device *phydev, 1814 struct netlink_ext_ack *extack, 1815 const struct phy_tdr_config *config); 1816 #else 1817 static inline 1818 int phy_start_cable_test(struct phy_device *phydev, 1819 struct netlink_ext_ack *extack) 1820 { 1821 NL_SET_ERR_MSG(extack, "Kernel not compiled with PHYLIB support"); 1822 return -EOPNOTSUPP; 1823 } 1824 static inline 1825 int phy_start_cable_test_tdr(struct phy_device *phydev, 1826 struct netlink_ext_ack *extack, 1827 const struct phy_tdr_config *config) 1828 { 1829 NL_SET_ERR_MSG(extack, "Kernel not compiled with PHYLIB support"); 1830 return -EOPNOTSUPP; 1831 } 1832 #endif 1833 1834 static inline void phy_device_reset(struct phy_device *phydev, int value) 1835 { 1836 mdio_device_reset(&phydev->mdio, value); 1837 } 1838 1839 #define phydev_err(_phydev, format, args...) \ 1840 dev_err(&_phydev->mdio.dev, format, ##args) 1841 1842 #define phydev_err_probe(_phydev, err, format, args...) \ 1843 dev_err_probe(&_phydev->mdio.dev, err, format, ##args) 1844 1845 #define phydev_info(_phydev, format, args...) \ 1846 dev_info(&_phydev->mdio.dev, format, ##args) 1847 1848 #define phydev_warn(_phydev, format, args...) \ 1849 dev_warn(&_phydev->mdio.dev, format, ##args) 1850 1851 #define phydev_dbg(_phydev, format, args...) \ 1852 dev_dbg(&_phydev->mdio.dev, format, ##args) 1853 1854 static inline const char *phydev_name(const struct phy_device *phydev) 1855 { 1856 return dev_name(&phydev->mdio.dev); 1857 } 1858 1859 static inline void phy_lock_mdio_bus(struct phy_device *phydev) 1860 { 1861 mutex_lock(&phydev->mdio.bus->mdio_lock); 1862 } 1863 1864 static inline void phy_unlock_mdio_bus(struct phy_device *phydev) 1865 { 1866 mutex_unlock(&phydev->mdio.bus->mdio_lock); 1867 } 1868 1869 void phy_attached_print(struct phy_device *phydev, const char *fmt, ...) 1870 __printf(2, 3); 1871 char *phy_attached_info_irq(struct phy_device *phydev) 1872 __malloc; 1873 void phy_attached_info(struct phy_device *phydev); 1874 1875 /* Clause 22 PHY */ 1876 int genphy_read_abilities(struct phy_device *phydev); 1877 int genphy_setup_forced(struct phy_device *phydev); 1878 int genphy_restart_aneg(struct phy_device *phydev); 1879 int genphy_check_and_restart_aneg(struct phy_device *phydev, bool restart); 1880 int genphy_config_eee_advert(struct phy_device *phydev); 1881 int __genphy_config_aneg(struct phy_device *phydev, bool changed); 1882 int genphy_aneg_done(struct phy_device *phydev); 1883 int genphy_update_link(struct phy_device *phydev); 1884 int genphy_read_lpa(struct phy_device *phydev); 1885 int genphy_read_status_fixed(struct phy_device *phydev); 1886 int genphy_read_status(struct phy_device *phydev); 1887 int genphy_read_master_slave(struct phy_device *phydev); 1888 int genphy_suspend(struct phy_device *phydev); 1889 int genphy_resume(struct phy_device *phydev); 1890 int genphy_loopback(struct phy_device *phydev, bool enable); 1891 int genphy_soft_reset(struct phy_device *phydev); 1892 irqreturn_t genphy_handle_interrupt_no_ack(struct phy_device *phydev); 1893 1894 static inline int genphy_config_aneg(struct phy_device *phydev) 1895 { 1896 return __genphy_config_aneg(phydev, false); 1897 } 1898 1899 static inline int genphy_no_config_intr(struct phy_device *phydev) 1900 { 1901 return 0; 1902 } 1903 int genphy_read_mmd_unsupported(struct phy_device *phdev, int devad, 1904 u16 regnum); 1905 int genphy_write_mmd_unsupported(struct phy_device *phdev, int devnum, 1906 u16 regnum, u16 val); 1907 1908 /* Clause 37 */ 1909 int genphy_c37_config_aneg(struct phy_device *phydev); 1910 int genphy_c37_read_status(struct phy_device *phydev, bool *changed); 1911 1912 /* Clause 45 PHY */ 1913 int genphy_c45_restart_aneg(struct phy_device *phydev); 1914 int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart); 1915 int genphy_c45_aneg_done(struct phy_device *phydev); 1916 int genphy_c45_read_link(struct phy_device *phydev); 1917 int genphy_c45_read_lpa(struct phy_device *phydev); 1918 int genphy_c45_read_pma(struct phy_device *phydev); 1919 int genphy_c45_pma_setup_forced(struct phy_device *phydev); 1920 int genphy_c45_pma_baset1_setup_master_slave(struct phy_device *phydev); 1921 int genphy_c45_an_config_aneg(struct phy_device *phydev); 1922 int genphy_c45_an_disable_aneg(struct phy_device *phydev); 1923 int genphy_c45_read_mdix(struct phy_device *phydev); 1924 int genphy_c45_pma_read_abilities(struct phy_device *phydev); 1925 int genphy_c45_pma_read_ext_abilities(struct phy_device *phydev); 1926 int genphy_c45_pma_baset1_read_abilities(struct phy_device *phydev); 1927 int genphy_c45_read_eee_abilities(struct phy_device *phydev); 1928 int genphy_c45_pma_baset1_read_master_slave(struct phy_device *phydev); 1929 int genphy_c45_read_status(struct phy_device *phydev); 1930 int genphy_c45_baset1_read_status(struct phy_device *phydev); 1931 int genphy_c45_config_aneg(struct phy_device *phydev); 1932 int genphy_c45_loopback(struct phy_device *phydev, bool enable); 1933 int genphy_c45_pma_resume(struct phy_device *phydev); 1934 int genphy_c45_pma_suspend(struct phy_device *phydev); 1935 int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable); 1936 int genphy_c45_plca_get_cfg(struct phy_device *phydev, 1937 struct phy_plca_cfg *plca_cfg); 1938 int genphy_c45_plca_set_cfg(struct phy_device *phydev, 1939 const struct phy_plca_cfg *plca_cfg); 1940 int genphy_c45_plca_get_status(struct phy_device *phydev, 1941 struct phy_plca_status *plca_st); 1942 int genphy_c45_eee_is_active(struct phy_device *phydev, unsigned long *adv, 1943 unsigned long *lp, bool *is_enabled); 1944 int genphy_c45_ethtool_get_eee(struct phy_device *phydev, 1945 struct ethtool_keee *data); 1946 int genphy_c45_ethtool_set_eee(struct phy_device *phydev, 1947 struct ethtool_keee *data); 1948 int genphy_c45_write_eee_adv(struct phy_device *phydev, unsigned long *adv); 1949 int genphy_c45_an_config_eee_aneg(struct phy_device *phydev); 1950 int genphy_c45_read_eee_adv(struct phy_device *phydev, unsigned long *adv); 1951 1952 /* Generic C45 PHY driver */ 1953 extern struct phy_driver genphy_c45_driver; 1954 1955 /* The gen10g_* functions are the old Clause 45 stub */ 1956 int gen10g_config_aneg(struct phy_device *phydev); 1957 1958 static inline int phy_read_status(struct phy_device *phydev) 1959 { 1960 if (!phydev->drv) 1961 return -EIO; 1962 1963 if (phydev->drv->read_status) 1964 return phydev->drv->read_status(phydev); 1965 else 1966 return genphy_read_status(phydev); 1967 } 1968 1969 void phy_driver_unregister(struct phy_driver *drv); 1970 void phy_drivers_unregister(struct phy_driver *drv, int n); 1971 int phy_driver_register(struct phy_driver *new_driver, struct module *owner); 1972 int phy_drivers_register(struct phy_driver *new_driver, int n, 1973 struct module *owner); 1974 void phy_error(struct phy_device *phydev); 1975 void phy_state_machine(struct work_struct *work); 1976 void phy_queue_state_machine(struct phy_device *phydev, unsigned long jiffies); 1977 void phy_trigger_machine(struct phy_device *phydev); 1978 void phy_mac_interrupt(struct phy_device *phydev); 1979 void phy_start_machine(struct phy_device *phydev); 1980 void phy_stop_machine(struct phy_device *phydev); 1981 void phy_ethtool_ksettings_get(struct phy_device *phydev, 1982 struct ethtool_link_ksettings *cmd); 1983 int phy_ethtool_ksettings_set(struct phy_device *phydev, 1984 const struct ethtool_link_ksettings *cmd); 1985 int phy_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd); 1986 int phy_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); 1987 int phy_do_ioctl_running(struct net_device *dev, struct ifreq *ifr, int cmd); 1988 int phy_disable_interrupts(struct phy_device *phydev); 1989 void phy_request_interrupt(struct phy_device *phydev); 1990 void phy_free_interrupt(struct phy_device *phydev); 1991 void phy_print_status(struct phy_device *phydev); 1992 int phy_get_rate_matching(struct phy_device *phydev, 1993 phy_interface_t iface); 1994 void phy_set_max_speed(struct phy_device *phydev, u32 max_speed); 1995 void phy_remove_link_mode(struct phy_device *phydev, u32 link_mode); 1996 void phy_advertise_supported(struct phy_device *phydev); 1997 void phy_advertise_eee_all(struct phy_device *phydev); 1998 void phy_support_sym_pause(struct phy_device *phydev); 1999 void phy_support_asym_pause(struct phy_device *phydev); 2000 void phy_support_eee(struct phy_device *phydev); 2001 void phy_set_sym_pause(struct phy_device *phydev, bool rx, bool tx, 2002 bool autoneg); 2003 void phy_set_asym_pause(struct phy_device *phydev, bool rx, bool tx); 2004 bool phy_validate_pause(struct phy_device *phydev, 2005 struct ethtool_pauseparam *pp); 2006 void phy_get_pause(struct phy_device *phydev, bool *tx_pause, bool *rx_pause); 2007 2008 s32 phy_get_internal_delay(struct phy_device *phydev, struct device *dev, 2009 const int *delay_values, int size, bool is_rx); 2010 2011 void phy_resolve_pause(unsigned long *local_adv, unsigned long *partner_adv, 2012 bool *tx_pause, bool *rx_pause); 2013 2014 int phy_register_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask, 2015 int (*run)(struct phy_device *)); 2016 int phy_register_fixup_for_id(const char *bus_id, 2017 int (*run)(struct phy_device *)); 2018 int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask, 2019 int (*run)(struct phy_device *)); 2020 2021 int phy_unregister_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask); 2022 int phy_unregister_fixup_for_id(const char *bus_id); 2023 int phy_unregister_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask); 2024 2025 int phy_init_eee(struct phy_device *phydev, bool clk_stop_enable); 2026 int phy_get_eee_err(struct phy_device *phydev); 2027 int phy_ethtool_set_eee(struct phy_device *phydev, struct ethtool_keee *data); 2028 int phy_ethtool_get_eee(struct phy_device *phydev, struct ethtool_keee *data); 2029 int phy_ethtool_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol); 2030 void phy_ethtool_get_wol(struct phy_device *phydev, 2031 struct ethtool_wolinfo *wol); 2032 int phy_ethtool_get_link_ksettings(struct net_device *ndev, 2033 struct ethtool_link_ksettings *cmd); 2034 int phy_ethtool_set_link_ksettings(struct net_device *ndev, 2035 const struct ethtool_link_ksettings *cmd); 2036 int phy_ethtool_nway_reset(struct net_device *ndev); 2037 int phy_package_join(struct phy_device *phydev, int base_addr, size_t priv_size); 2038 int of_phy_package_join(struct phy_device *phydev, size_t priv_size); 2039 void phy_package_leave(struct phy_device *phydev); 2040 int devm_phy_package_join(struct device *dev, struct phy_device *phydev, 2041 int base_addr, size_t priv_size); 2042 int devm_of_phy_package_join(struct device *dev, struct phy_device *phydev, 2043 size_t priv_size); 2044 2045 int __init mdio_bus_init(void); 2046 void mdio_bus_exit(void); 2047 2048 int phy_ethtool_get_strings(struct phy_device *phydev, u8 *data); 2049 int phy_ethtool_get_sset_count(struct phy_device *phydev); 2050 int phy_ethtool_get_stats(struct phy_device *phydev, 2051 struct ethtool_stats *stats, u64 *data); 2052 int phy_ethtool_get_plca_cfg(struct phy_device *phydev, 2053 struct phy_plca_cfg *plca_cfg); 2054 int phy_ethtool_set_plca_cfg(struct phy_device *phydev, 2055 const struct phy_plca_cfg *plca_cfg, 2056 struct netlink_ext_ack *extack); 2057 int phy_ethtool_get_plca_status(struct phy_device *phydev, 2058 struct phy_plca_status *plca_st); 2059 2060 int __phy_hwtstamp_get(struct phy_device *phydev, 2061 struct kernel_hwtstamp_config *config); 2062 int __phy_hwtstamp_set(struct phy_device *phydev, 2063 struct kernel_hwtstamp_config *config, 2064 struct netlink_ext_ack *extack); 2065 2066 static inline int phy_package_address(struct phy_device *phydev, 2067 unsigned int addr_offset) 2068 { 2069 struct phy_package_shared *shared = phydev->shared; 2070 u8 base_addr = shared->base_addr; 2071 2072 if (addr_offset >= PHY_MAX_ADDR - base_addr) 2073 return -EIO; 2074 2075 /* we know that addr will be in the range 0..31 and thus the 2076 * implicit cast to a signed int is not a problem. 2077 */ 2078 return base_addr + addr_offset; 2079 } 2080 2081 static inline int phy_package_read(struct phy_device *phydev, 2082 unsigned int addr_offset, u32 regnum) 2083 { 2084 int addr = phy_package_address(phydev, addr_offset); 2085 2086 if (addr < 0) 2087 return addr; 2088 2089 return mdiobus_read(phydev->mdio.bus, addr, regnum); 2090 } 2091 2092 static inline int __phy_package_read(struct phy_device *phydev, 2093 unsigned int addr_offset, u32 regnum) 2094 { 2095 int addr = phy_package_address(phydev, addr_offset); 2096 2097 if (addr < 0) 2098 return addr; 2099 2100 return __mdiobus_read(phydev->mdio.bus, addr, regnum); 2101 } 2102 2103 static inline int phy_package_write(struct phy_device *phydev, 2104 unsigned int addr_offset, u32 regnum, 2105 u16 val) 2106 { 2107 int addr = phy_package_address(phydev, addr_offset); 2108 2109 if (addr < 0) 2110 return addr; 2111 2112 return mdiobus_write(phydev->mdio.bus, addr, regnum, val); 2113 } 2114 2115 static inline int __phy_package_write(struct phy_device *phydev, 2116 unsigned int addr_offset, u32 regnum, 2117 u16 val) 2118 { 2119 int addr = phy_package_address(phydev, addr_offset); 2120 2121 if (addr < 0) 2122 return addr; 2123 2124 return __mdiobus_write(phydev->mdio.bus, addr, regnum, val); 2125 } 2126 2127 int __phy_package_read_mmd(struct phy_device *phydev, 2128 unsigned int addr_offset, int devad, 2129 u32 regnum); 2130 2131 int phy_package_read_mmd(struct phy_device *phydev, 2132 unsigned int addr_offset, int devad, 2133 u32 regnum); 2134 2135 int __phy_package_write_mmd(struct phy_device *phydev, 2136 unsigned int addr_offset, int devad, 2137 u32 regnum, u16 val); 2138 2139 int phy_package_write_mmd(struct phy_device *phydev, 2140 unsigned int addr_offset, int devad, 2141 u32 regnum, u16 val); 2142 2143 static inline bool __phy_package_set_once(struct phy_device *phydev, 2144 unsigned int b) 2145 { 2146 struct phy_package_shared *shared = phydev->shared; 2147 2148 if (!shared) 2149 return false; 2150 2151 return !test_and_set_bit(b, &shared->flags); 2152 } 2153 2154 static inline bool phy_package_init_once(struct phy_device *phydev) 2155 { 2156 return __phy_package_set_once(phydev, PHY_SHARED_F_INIT_DONE); 2157 } 2158 2159 static inline bool phy_package_probe_once(struct phy_device *phydev) 2160 { 2161 return __phy_package_set_once(phydev, PHY_SHARED_F_PROBE_DONE); 2162 } 2163 2164 extern const struct bus_type mdio_bus_type; 2165 2166 struct mdio_board_info { 2167 const char *bus_id; 2168 char modalias[MDIO_NAME_SIZE]; 2169 int mdio_addr; 2170 const void *platform_data; 2171 }; 2172 2173 #if IS_ENABLED(CONFIG_MDIO_DEVICE) 2174 int mdiobus_register_board_info(const struct mdio_board_info *info, 2175 unsigned int n); 2176 #else 2177 static inline int mdiobus_register_board_info(const struct mdio_board_info *i, 2178 unsigned int n) 2179 { 2180 return 0; 2181 } 2182 #endif 2183 2184 2185 /** 2186 * phy_module_driver() - Helper macro for registering PHY drivers 2187 * @__phy_drivers: array of PHY drivers to register 2188 * @__count: Numbers of members in array 2189 * 2190 * Helper macro for PHY drivers which do not do anything special in module 2191 * init/exit. Each module may only use this macro once, and calling it 2192 * replaces module_init() and module_exit(). 2193 */ 2194 #define phy_module_driver(__phy_drivers, __count) \ 2195 static int __init phy_module_init(void) \ 2196 { \ 2197 return phy_drivers_register(__phy_drivers, __count, THIS_MODULE); \ 2198 } \ 2199 module_init(phy_module_init); \ 2200 static void __exit phy_module_exit(void) \ 2201 { \ 2202 phy_drivers_unregister(__phy_drivers, __count); \ 2203 } \ 2204 module_exit(phy_module_exit) 2205 2206 #define module_phy_driver(__phy_drivers) \ 2207 phy_module_driver(__phy_drivers, ARRAY_SIZE(__phy_drivers)) 2208 2209 bool phy_driver_is_genphy(struct phy_device *phydev); 2210 bool phy_driver_is_genphy_10g(struct phy_device *phydev); 2211 2212 #endif /* __PHY_H */ 2213