1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Framework and drivers for configuring and reading different PHYs 4 * Based on code in sungem_phy.c and (long-removed) gianfar_phy.c 5 * 6 * Author: Andy Fleming 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 */ 10 11 #ifndef __PHY_H 12 #define __PHY_H 13 14 #include <linux/compiler.h> 15 #include <linux/spinlock.h> 16 #include <linux/ethtool.h> 17 #include <linux/leds.h> 18 #include <linux/linkmode.h> 19 #include <linux/netlink.h> 20 #include <linux/mdio.h> 21 #include <linux/mii.h> 22 #include <linux/mii_timestamper.h> 23 #include <linux/module.h> 24 #include <linux/timer.h> 25 #include <linux/workqueue.h> 26 #include <linux/mod_devicetable.h> 27 #include <linux/u64_stats_sync.h> 28 #include <linux/irqreturn.h> 29 #include <linux/iopoll.h> 30 #include <linux/refcount.h> 31 32 #include <linux/atomic.h> 33 #include <net/eee.h> 34 35 #define PHY_DEFAULT_FEATURES (SUPPORTED_Autoneg | \ 36 SUPPORTED_TP | \ 37 SUPPORTED_MII) 38 39 #define PHY_10BT_FEATURES (SUPPORTED_10baseT_Half | \ 40 SUPPORTED_10baseT_Full) 41 42 #define PHY_100BT_FEATURES (SUPPORTED_100baseT_Half | \ 43 SUPPORTED_100baseT_Full) 44 45 #define PHY_1000BT_FEATURES (SUPPORTED_1000baseT_Half | \ 46 SUPPORTED_1000baseT_Full) 47 48 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_features) __ro_after_init; 49 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1_features) __ro_after_init; 50 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1s_p2mp_features) __ro_after_init; 51 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_features) __ro_after_init; 52 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_fibre_features) __ro_after_init; 53 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_all_ports_features) __ro_after_init; 54 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_features) __ro_after_init; 55 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_fec_features) __ro_after_init; 56 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_full_features) __ro_after_init; 57 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_eee_cap1_features) __ro_after_init; 58 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_eee_cap2_features) __ro_after_init; 59 60 #define PHY_BASIC_FEATURES ((unsigned long *)&phy_basic_features) 61 #define PHY_BASIC_T1_FEATURES ((unsigned long *)&phy_basic_t1_features) 62 #define PHY_BASIC_T1S_P2MP_FEATURES ((unsigned long *)&phy_basic_t1s_p2mp_features) 63 #define PHY_GBIT_FEATURES ((unsigned long *)&phy_gbit_features) 64 #define PHY_GBIT_FIBRE_FEATURES ((unsigned long *)&phy_gbit_fibre_features) 65 #define PHY_GBIT_ALL_PORTS_FEATURES ((unsigned long *)&phy_gbit_all_ports_features) 66 #define PHY_10GBIT_FEATURES ((unsigned long *)&phy_10gbit_features) 67 #define PHY_10GBIT_FEC_FEATURES ((unsigned long *)&phy_10gbit_fec_features) 68 #define PHY_10GBIT_FULL_FEATURES ((unsigned long *)&phy_10gbit_full_features) 69 #define PHY_EEE_CAP1_FEATURES ((unsigned long *)&phy_eee_cap1_features) 70 #define PHY_EEE_CAP2_FEATURES ((unsigned long *)&phy_eee_cap2_features) 71 72 extern const int phy_basic_ports_array[3]; 73 extern const int phy_fibre_port_array[1]; 74 extern const int phy_all_ports_features_array[7]; 75 extern const int phy_10_100_features_array[4]; 76 extern const int phy_basic_t1_features_array[3]; 77 extern const int phy_basic_t1s_p2mp_features_array[2]; 78 extern const int phy_gbit_features_array[2]; 79 extern const int phy_10gbit_features_array[1]; 80 81 /* 82 * Set phydev->irq to PHY_POLL if interrupts are not supported, 83 * or not desired for this PHY. Set to PHY_MAC_INTERRUPT if 84 * the attached MAC driver handles the interrupt 85 */ 86 #define PHY_POLL -1 87 #define PHY_MAC_INTERRUPT -2 88 89 #define PHY_IS_INTERNAL 0x00000001 90 #define PHY_RST_AFTER_CLK_EN 0x00000002 91 #define PHY_POLL_CABLE_TEST 0x00000004 92 #define PHY_ALWAYS_CALL_SUSPEND 0x00000008 93 #define MDIO_DEVICE_IS_PHY 0x80000000 94 95 /** 96 * enum phy_interface_t - Interface Mode definitions 97 * 98 * @PHY_INTERFACE_MODE_NA: Not Applicable - don't touch 99 * @PHY_INTERFACE_MODE_INTERNAL: No interface, MAC and PHY combined 100 * @PHY_INTERFACE_MODE_MII: Media-independent interface 101 * @PHY_INTERFACE_MODE_GMII: Gigabit media-independent interface 102 * @PHY_INTERFACE_MODE_SGMII: Serial gigabit media-independent interface 103 * @PHY_INTERFACE_MODE_TBI: Ten Bit Interface 104 * @PHY_INTERFACE_MODE_REVMII: Reverse Media Independent Interface 105 * @PHY_INTERFACE_MODE_RMII: Reduced Media Independent Interface 106 * @PHY_INTERFACE_MODE_REVRMII: Reduced Media Independent Interface in PHY role 107 * @PHY_INTERFACE_MODE_RGMII: Reduced gigabit media-independent interface 108 * @PHY_INTERFACE_MODE_RGMII_ID: RGMII with Internal RX+TX delay 109 * @PHY_INTERFACE_MODE_RGMII_RXID: RGMII with Internal RX delay 110 * @PHY_INTERFACE_MODE_RGMII_TXID: RGMII with Internal RX delay 111 * @PHY_INTERFACE_MODE_RTBI: Reduced TBI 112 * @PHY_INTERFACE_MODE_SMII: Serial MII 113 * @PHY_INTERFACE_MODE_XGMII: 10 gigabit media-independent interface 114 * @PHY_INTERFACE_MODE_XLGMII:40 gigabit media-independent interface 115 * @PHY_INTERFACE_MODE_MOCA: Multimedia over Coax 116 * @PHY_INTERFACE_MODE_PSGMII: Penta SGMII 117 * @PHY_INTERFACE_MODE_QSGMII: Quad SGMII 118 * @PHY_INTERFACE_MODE_TRGMII: Turbo RGMII 119 * @PHY_INTERFACE_MODE_100BASEX: 100 BaseX 120 * @PHY_INTERFACE_MODE_1000BASEX: 1000 BaseX 121 * @PHY_INTERFACE_MODE_2500BASEX: 2500 BaseX 122 * @PHY_INTERFACE_MODE_5GBASER: 5G BaseR 123 * @PHY_INTERFACE_MODE_RXAUI: Reduced XAUI 124 * @PHY_INTERFACE_MODE_XAUI: 10 Gigabit Attachment Unit Interface 125 * @PHY_INTERFACE_MODE_10GBASER: 10G BaseR 126 * @PHY_INTERFACE_MODE_25GBASER: 25G BaseR 127 * @PHY_INTERFACE_MODE_USXGMII: Universal Serial 10GE MII 128 * @PHY_INTERFACE_MODE_10GKR: 10GBASE-KR - with Clause 73 AN 129 * @PHY_INTERFACE_MODE_QUSGMII: Quad Universal SGMII 130 * @PHY_INTERFACE_MODE_1000BASEKX: 1000Base-KX - with Clause 73 AN 131 * @PHY_INTERFACE_MODE_10G_QXGMII: 10G-QXGMII - 4 ports over 10G USXGMII 132 * @PHY_INTERFACE_MODE_MAX: Book keeping 133 * 134 * Describes the interface between the MAC and PHY. 135 */ 136 typedef enum { 137 PHY_INTERFACE_MODE_NA, 138 PHY_INTERFACE_MODE_INTERNAL, 139 PHY_INTERFACE_MODE_MII, 140 PHY_INTERFACE_MODE_GMII, 141 PHY_INTERFACE_MODE_SGMII, 142 PHY_INTERFACE_MODE_TBI, 143 PHY_INTERFACE_MODE_REVMII, 144 PHY_INTERFACE_MODE_RMII, 145 PHY_INTERFACE_MODE_REVRMII, 146 PHY_INTERFACE_MODE_RGMII, 147 PHY_INTERFACE_MODE_RGMII_ID, 148 PHY_INTERFACE_MODE_RGMII_RXID, 149 PHY_INTERFACE_MODE_RGMII_TXID, 150 PHY_INTERFACE_MODE_RTBI, 151 PHY_INTERFACE_MODE_SMII, 152 PHY_INTERFACE_MODE_XGMII, 153 PHY_INTERFACE_MODE_XLGMII, 154 PHY_INTERFACE_MODE_MOCA, 155 PHY_INTERFACE_MODE_PSGMII, 156 PHY_INTERFACE_MODE_QSGMII, 157 PHY_INTERFACE_MODE_TRGMII, 158 PHY_INTERFACE_MODE_100BASEX, 159 PHY_INTERFACE_MODE_1000BASEX, 160 PHY_INTERFACE_MODE_2500BASEX, 161 PHY_INTERFACE_MODE_5GBASER, 162 PHY_INTERFACE_MODE_RXAUI, 163 PHY_INTERFACE_MODE_XAUI, 164 /* 10GBASE-R, XFI, SFI - single lane 10G Serdes */ 165 PHY_INTERFACE_MODE_10GBASER, 166 PHY_INTERFACE_MODE_25GBASER, 167 PHY_INTERFACE_MODE_USXGMII, 168 /* 10GBASE-KR - with Clause 73 AN */ 169 PHY_INTERFACE_MODE_10GKR, 170 PHY_INTERFACE_MODE_QUSGMII, 171 PHY_INTERFACE_MODE_1000BASEKX, 172 PHY_INTERFACE_MODE_10G_QXGMII, 173 PHY_INTERFACE_MODE_MAX, 174 } phy_interface_t; 175 176 /* PHY interface mode bitmap handling */ 177 #define DECLARE_PHY_INTERFACE_MASK(name) \ 178 DECLARE_BITMAP(name, PHY_INTERFACE_MODE_MAX) 179 180 static inline void phy_interface_zero(unsigned long *intf) 181 { 182 bitmap_zero(intf, PHY_INTERFACE_MODE_MAX); 183 } 184 185 static inline bool phy_interface_empty(const unsigned long *intf) 186 { 187 return bitmap_empty(intf, PHY_INTERFACE_MODE_MAX); 188 } 189 190 static inline void phy_interface_and(unsigned long *dst, const unsigned long *a, 191 const unsigned long *b) 192 { 193 bitmap_and(dst, a, b, PHY_INTERFACE_MODE_MAX); 194 } 195 196 static inline void phy_interface_or(unsigned long *dst, const unsigned long *a, 197 const unsigned long *b) 198 { 199 bitmap_or(dst, a, b, PHY_INTERFACE_MODE_MAX); 200 } 201 202 static inline void phy_interface_set_rgmii(unsigned long *intf) 203 { 204 __set_bit(PHY_INTERFACE_MODE_RGMII, intf); 205 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, intf); 206 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, intf); 207 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, intf); 208 } 209 210 /* 211 * phy_supported_speeds - return all speeds currently supported by a PHY device 212 */ 213 unsigned int phy_supported_speeds(struct phy_device *phy, 214 unsigned int *speeds, 215 unsigned int size); 216 217 /** 218 * phy_modes - map phy_interface_t enum to device tree binding of phy-mode 219 * @interface: enum phy_interface_t value 220 * 221 * Description: maps enum &phy_interface_t defined in this file 222 * into the device tree binding of 'phy-mode', so that Ethernet 223 * device driver can get PHY interface from device tree. 224 */ 225 static inline const char *phy_modes(phy_interface_t interface) 226 { 227 switch (interface) { 228 case PHY_INTERFACE_MODE_NA: 229 return ""; 230 case PHY_INTERFACE_MODE_INTERNAL: 231 return "internal"; 232 case PHY_INTERFACE_MODE_MII: 233 return "mii"; 234 case PHY_INTERFACE_MODE_GMII: 235 return "gmii"; 236 case PHY_INTERFACE_MODE_SGMII: 237 return "sgmii"; 238 case PHY_INTERFACE_MODE_TBI: 239 return "tbi"; 240 case PHY_INTERFACE_MODE_REVMII: 241 return "rev-mii"; 242 case PHY_INTERFACE_MODE_RMII: 243 return "rmii"; 244 case PHY_INTERFACE_MODE_REVRMII: 245 return "rev-rmii"; 246 case PHY_INTERFACE_MODE_RGMII: 247 return "rgmii"; 248 case PHY_INTERFACE_MODE_RGMII_ID: 249 return "rgmii-id"; 250 case PHY_INTERFACE_MODE_RGMII_RXID: 251 return "rgmii-rxid"; 252 case PHY_INTERFACE_MODE_RGMII_TXID: 253 return "rgmii-txid"; 254 case PHY_INTERFACE_MODE_RTBI: 255 return "rtbi"; 256 case PHY_INTERFACE_MODE_SMII: 257 return "smii"; 258 case PHY_INTERFACE_MODE_XGMII: 259 return "xgmii"; 260 case PHY_INTERFACE_MODE_XLGMII: 261 return "xlgmii"; 262 case PHY_INTERFACE_MODE_MOCA: 263 return "moca"; 264 case PHY_INTERFACE_MODE_PSGMII: 265 return "psgmii"; 266 case PHY_INTERFACE_MODE_QSGMII: 267 return "qsgmii"; 268 case PHY_INTERFACE_MODE_TRGMII: 269 return "trgmii"; 270 case PHY_INTERFACE_MODE_1000BASEX: 271 return "1000base-x"; 272 case PHY_INTERFACE_MODE_1000BASEKX: 273 return "1000base-kx"; 274 case PHY_INTERFACE_MODE_2500BASEX: 275 return "2500base-x"; 276 case PHY_INTERFACE_MODE_5GBASER: 277 return "5gbase-r"; 278 case PHY_INTERFACE_MODE_RXAUI: 279 return "rxaui"; 280 case PHY_INTERFACE_MODE_XAUI: 281 return "xaui"; 282 case PHY_INTERFACE_MODE_10GBASER: 283 return "10gbase-r"; 284 case PHY_INTERFACE_MODE_25GBASER: 285 return "25gbase-r"; 286 case PHY_INTERFACE_MODE_USXGMII: 287 return "usxgmii"; 288 case PHY_INTERFACE_MODE_10GKR: 289 return "10gbase-kr"; 290 case PHY_INTERFACE_MODE_100BASEX: 291 return "100base-x"; 292 case PHY_INTERFACE_MODE_QUSGMII: 293 return "qusgmii"; 294 case PHY_INTERFACE_MODE_10G_QXGMII: 295 return "10g-qxgmii"; 296 default: 297 return "unknown"; 298 } 299 } 300 301 #define PHY_INIT_TIMEOUT 100000 302 #define PHY_FORCE_TIMEOUT 10 303 304 #define PHY_MAX_ADDR 32 305 306 /* Used when trying to connect to a specific phy (mii bus id:phy device id) */ 307 #define PHY_ID_FMT "%s:%02x" 308 309 #define MII_BUS_ID_SIZE 61 310 311 struct device; 312 struct kernel_hwtstamp_config; 313 struct phylink; 314 struct sfp_bus; 315 struct sfp_upstream_ops; 316 struct sk_buff; 317 318 /** 319 * struct mdio_bus_stats - Statistics counters for MDIO busses 320 * @transfers: Total number of transfers, i.e. @writes + @reads 321 * @errors: Number of MDIO transfers that returned an error 322 * @writes: Number of write transfers 323 * @reads: Number of read transfers 324 * @syncp: Synchronisation for incrementing statistics 325 */ 326 struct mdio_bus_stats { 327 u64_stats_t transfers; 328 u64_stats_t errors; 329 u64_stats_t writes; 330 u64_stats_t reads; 331 /* Must be last, add new statistics above */ 332 struct u64_stats_sync syncp; 333 }; 334 335 /** 336 * struct phy_package_shared - Shared information in PHY packages 337 * @base_addr: Base PHY address of PHY package used to combine PHYs 338 * in one package and for offset calculation of phy_package_read/write 339 * @np: Pointer to the Device Node if PHY package defined in DT 340 * @refcnt: Number of PHYs connected to this shared data 341 * @flags: Initialization of PHY package 342 * @priv_size: Size of the shared private data @priv 343 * @priv: Driver private data shared across a PHY package 344 * 345 * Represents a shared structure between different phydev's in the same 346 * package, for example a quad PHY. See phy_package_join() and 347 * phy_package_leave(). 348 */ 349 struct phy_package_shared { 350 u8 base_addr; 351 /* With PHY package defined in DT this points to the PHY package node */ 352 struct device_node *np; 353 refcount_t refcnt; 354 unsigned long flags; 355 size_t priv_size; 356 357 /* private data pointer */ 358 /* note that this pointer is shared between different phydevs and 359 * the user has to take care of appropriate locking. It is allocated 360 * and freed automatically by phy_package_join() and 361 * phy_package_leave(). 362 */ 363 void *priv; 364 }; 365 366 /* used as bit number in atomic bitops */ 367 #define PHY_SHARED_F_INIT_DONE 0 368 #define PHY_SHARED_F_PROBE_DONE 1 369 370 /** 371 * struct mii_bus - Represents an MDIO bus 372 * 373 * @owner: Who owns this device 374 * @name: User friendly name for this MDIO device, or driver name 375 * @id: Unique identifier for this bus, typical from bus hierarchy 376 * @priv: Driver private data 377 * 378 * The Bus class for PHYs. Devices which provide access to 379 * PHYs should register using this structure 380 */ 381 struct mii_bus { 382 struct module *owner; 383 const char *name; 384 char id[MII_BUS_ID_SIZE]; 385 void *priv; 386 /** @read: Perform a read transfer on the bus */ 387 int (*read)(struct mii_bus *bus, int addr, int regnum); 388 /** @write: Perform a write transfer on the bus */ 389 int (*write)(struct mii_bus *bus, int addr, int regnum, u16 val); 390 /** @read_c45: Perform a C45 read transfer on the bus */ 391 int (*read_c45)(struct mii_bus *bus, int addr, int devnum, int regnum); 392 /** @write_c45: Perform a C45 write transfer on the bus */ 393 int (*write_c45)(struct mii_bus *bus, int addr, int devnum, 394 int regnum, u16 val); 395 /** @reset: Perform a reset of the bus */ 396 int (*reset)(struct mii_bus *bus); 397 398 /** @stats: Statistic counters per device on the bus */ 399 struct mdio_bus_stats stats[PHY_MAX_ADDR]; 400 401 /** 402 * @mdio_lock: A lock to ensure that only one thing can read/write 403 * the MDIO bus at a time 404 */ 405 struct mutex mdio_lock; 406 407 /** @parent: Parent device of this bus */ 408 struct device *parent; 409 /** @state: State of bus structure */ 410 enum { 411 MDIOBUS_ALLOCATED = 1, 412 MDIOBUS_REGISTERED, 413 MDIOBUS_UNREGISTERED, 414 MDIOBUS_RELEASED, 415 } state; 416 417 /** @dev: Kernel device representation */ 418 struct device dev; 419 420 /** @mdio_map: list of all MDIO devices on bus */ 421 struct mdio_device *mdio_map[PHY_MAX_ADDR]; 422 423 /** @phy_mask: PHY addresses to be ignored when probing */ 424 u32 phy_mask; 425 426 /** @phy_ignore_ta_mask: PHY addresses to ignore the TA/read failure */ 427 u32 phy_ignore_ta_mask; 428 429 /** 430 * @irq: An array of interrupts, each PHY's interrupt at the index 431 * matching its address 432 */ 433 int irq[PHY_MAX_ADDR]; 434 435 /** @reset_delay_us: GPIO reset pulse width in microseconds */ 436 int reset_delay_us; 437 /** @reset_post_delay_us: GPIO reset deassert delay in microseconds */ 438 int reset_post_delay_us; 439 /** @reset_gpiod: Reset GPIO descriptor pointer */ 440 struct gpio_desc *reset_gpiod; 441 442 /** @shared_lock: protect access to the shared element */ 443 struct mutex shared_lock; 444 445 /** @shared: shared state across different PHYs */ 446 struct phy_package_shared *shared[PHY_MAX_ADDR]; 447 }; 448 #define to_mii_bus(d) container_of(d, struct mii_bus, dev) 449 450 struct mii_bus *mdiobus_alloc_size(size_t size); 451 452 /** 453 * mdiobus_alloc - Allocate an MDIO bus structure 454 * 455 * The internal state of the MDIO bus will be set of MDIOBUS_ALLOCATED ready 456 * for the driver to register the bus. 457 */ 458 static inline struct mii_bus *mdiobus_alloc(void) 459 { 460 return mdiobus_alloc_size(0); 461 } 462 463 int __mdiobus_register(struct mii_bus *bus, struct module *owner); 464 int __devm_mdiobus_register(struct device *dev, struct mii_bus *bus, 465 struct module *owner); 466 #define mdiobus_register(bus) __mdiobus_register(bus, THIS_MODULE) 467 #define devm_mdiobus_register(dev, bus) \ 468 __devm_mdiobus_register(dev, bus, THIS_MODULE) 469 470 void mdiobus_unregister(struct mii_bus *bus); 471 void mdiobus_free(struct mii_bus *bus); 472 struct mii_bus *devm_mdiobus_alloc_size(struct device *dev, int sizeof_priv); 473 static inline struct mii_bus *devm_mdiobus_alloc(struct device *dev) 474 { 475 return devm_mdiobus_alloc_size(dev, 0); 476 } 477 478 struct mii_bus *mdio_find_bus(const char *mdio_name); 479 struct phy_device *mdiobus_scan_c22(struct mii_bus *bus, int addr); 480 481 #define PHY_INTERRUPT_DISABLED false 482 #define PHY_INTERRUPT_ENABLED true 483 484 /** 485 * enum phy_state - PHY state machine states: 486 * 487 * @PHY_DOWN: PHY device and driver are not ready for anything. probe 488 * should be called if and only if the PHY is in this state, 489 * given that the PHY device exists. 490 * - PHY driver probe function will set the state to @PHY_READY 491 * 492 * @PHY_READY: PHY is ready to send and receive packets, but the 493 * controller is not. By default, PHYs which do not implement 494 * probe will be set to this state by phy_probe(). 495 * - start will set the state to UP 496 * 497 * @PHY_UP: The PHY and attached device are ready to do work. 498 * Interrupts should be started here. 499 * - timer moves to @PHY_NOLINK or @PHY_RUNNING 500 * 501 * @PHY_NOLINK: PHY is up, but not currently plugged in. 502 * - irq or timer will set @PHY_RUNNING if link comes back 503 * - phy_stop moves to @PHY_HALTED 504 * 505 * @PHY_RUNNING: PHY is currently up, running, and possibly sending 506 * and/or receiving packets 507 * - irq or timer will set @PHY_NOLINK if link goes down 508 * - phy_stop moves to @PHY_HALTED 509 * 510 * @PHY_CABLETEST: PHY is performing a cable test. Packet reception/sending 511 * is not expected to work, carrier will be indicated as down. PHY will be 512 * poll once per second, or on interrupt for it current state. 513 * Once complete, move to UP to restart the PHY. 514 * - phy_stop aborts the running test and moves to @PHY_HALTED 515 * 516 * @PHY_HALTED: PHY is up, but no polling or interrupts are done. 517 * - phy_start moves to @PHY_UP 518 * 519 * @PHY_ERROR: PHY is up, but is in an error state. 520 * - phy_stop moves to @PHY_HALTED 521 */ 522 enum phy_state { 523 PHY_DOWN = 0, 524 PHY_READY, 525 PHY_HALTED, 526 PHY_ERROR, 527 PHY_UP, 528 PHY_RUNNING, 529 PHY_NOLINK, 530 PHY_CABLETEST, 531 }; 532 533 #define MDIO_MMD_NUM 32 534 535 /** 536 * struct phy_c45_device_ids - 802.3-c45 Device Identifiers 537 * @devices_in_package: IEEE 802.3 devices in package register value. 538 * @mmds_present: bit vector of MMDs present. 539 * @device_ids: The device identifer for each present device. 540 */ 541 struct phy_c45_device_ids { 542 u32 devices_in_package; 543 u32 mmds_present; 544 u32 device_ids[MDIO_MMD_NUM]; 545 }; 546 547 struct macsec_context; 548 struct macsec_ops; 549 550 /** 551 * struct phy_device - An instance of a PHY 552 * 553 * @mdio: MDIO bus this PHY is on 554 * @drv: Pointer to the driver for this PHY instance 555 * @devlink: Create a link between phy dev and mac dev, if the external phy 556 * used by current mac interface is managed by another mac interface. 557 * @phyindex: Unique id across the phy's parent tree of phys to address the PHY 558 * from userspace, similar to ifindex. A zero index means the PHY 559 * wasn't assigned an id yet. 560 * @phy_id: UID for this device found during discovery 561 * @c45_ids: 802.3-c45 Device Identifiers if is_c45. 562 * @is_c45: Set to true if this PHY uses clause 45 addressing. 563 * @is_internal: Set to true if this PHY is internal to a MAC. 564 * @is_pseudo_fixed_link: Set to true if this PHY is an Ethernet switch, etc. 565 * @is_gigabit_capable: Set to true if PHY supports 1000Mbps 566 * @has_fixups: Set to true if this PHY has fixups/quirks. 567 * @suspended: Set to true if this PHY has been suspended successfully. 568 * @suspended_by_mdio_bus: Set to true if this PHY was suspended by MDIO bus. 569 * @sysfs_links: Internal boolean tracking sysfs symbolic links setup/removal. 570 * @loopback_enabled: Set true if this PHY has been loopbacked successfully. 571 * @downshifted_rate: Set true if link speed has been downshifted. 572 * @is_on_sfp_module: Set true if PHY is located on an SFP module. 573 * @mac_managed_pm: Set true if MAC driver takes of suspending/resuming PHY 574 * @wol_enabled: Set to true if the PHY or the attached MAC have Wake-on-LAN 575 * enabled. 576 * @state: State of the PHY for management purposes 577 * @dev_flags: Device-specific flags used by the PHY driver. 578 * 579 * - Bits [15:0] are free to use by the PHY driver to communicate 580 * driver specific behavior. 581 * - Bits [23:16] are currently reserved for future use. 582 * - Bits [31:24] are reserved for defining generic 583 * PHY driver behavior. 584 * @irq: IRQ number of the PHY's interrupt (-1 if none) 585 * @phylink: Pointer to phylink instance for this PHY 586 * @sfp_bus_attached: Flag indicating whether the SFP bus has been attached 587 * @sfp_bus: SFP bus attached to this PHY's fiber port 588 * @attached_dev: The attached enet driver's device instance ptr 589 * @adjust_link: Callback for the enet controller to respond to changes: in the 590 * link state. 591 * @phy_link_change: Callback for phylink for notification of link change 592 * @macsec_ops: MACsec offloading ops. 593 * 594 * @speed: Current link speed 595 * @duplex: Current duplex 596 * @port: Current port 597 * @pause: Current pause 598 * @asym_pause: Current asymmetric pause 599 * @supported: Combined MAC/PHY supported linkmodes 600 * @advertising: Currently advertised linkmodes 601 * @adv_old: Saved advertised while power saving for WoL 602 * @supported_eee: supported PHY EEE linkmodes 603 * @advertising_eee: Currently advertised EEE linkmodes 604 * @eee_enabled: Flag indicating whether the EEE feature is enabled 605 * @enable_tx_lpi: When True, MAC should transmit LPI to PHY 606 * @eee_cfg: User configuration of EEE 607 * @lp_advertising: Current link partner advertised linkmodes 608 * @host_interfaces: PHY interface modes supported by host 609 * @eee_broken_modes: Energy efficient ethernet modes which should be prohibited 610 * @autoneg: Flag autoneg being used 611 * @rate_matching: Current rate matching mode 612 * @link: Current link state 613 * @autoneg_complete: Flag auto negotiation of the link has completed 614 * @mdix: Current crossover 615 * @mdix_ctrl: User setting of crossover 616 * @pma_extable: Cached value of PMA/PMD Extended Abilities Register 617 * @interrupts: Flag interrupts have been enabled 618 * @irq_suspended: Flag indicating PHY is suspended and therefore interrupt 619 * handling shall be postponed until PHY has resumed 620 * @irq_rerun: Flag indicating interrupts occurred while PHY was suspended, 621 * requiring a rerun of the interrupt handler after resume 622 * @default_timestamp: Flag indicating whether we are using the phy 623 * timestamp as the default one 624 * @interface: enum phy_interface_t value 625 * @possible_interfaces: bitmap if interface modes that the attached PHY 626 * will switch between depending on media speed. 627 * @skb: Netlink message for cable diagnostics 628 * @nest: Netlink nest used for cable diagnostics 629 * @ehdr: nNtlink header for cable diagnostics 630 * @phy_led_triggers: Array of LED triggers 631 * @phy_num_led_triggers: Number of triggers in @phy_led_triggers 632 * @led_link_trigger: LED trigger for link up/down 633 * @last_triggered: last LED trigger for link speed 634 * @leds: list of PHY LED structures 635 * @master_slave_set: User requested master/slave configuration 636 * @master_slave_get: Current master/slave advertisement 637 * @master_slave_state: Current master/slave configuration 638 * @mii_ts: Pointer to time stamper callbacks 639 * @psec: Pointer to Power Sourcing Equipment control struct 640 * @lock: Mutex for serialization access to PHY 641 * @state_queue: Work queue for state machine 642 * @link_down_events: Number of times link was lost 643 * @shared: Pointer to private data shared by phys in one package 644 * @priv: Pointer to driver private data 645 * 646 * interrupts currently only supports enabled or disabled, 647 * but could be changed in the future to support enabling 648 * and disabling specific interrupts 649 * 650 * Contains some infrastructure for polling and interrupt 651 * handling, as well as handling shifts in PHY hardware state 652 */ 653 struct phy_device { 654 struct mdio_device mdio; 655 656 /* Information about the PHY type */ 657 /* And management functions */ 658 const struct phy_driver *drv; 659 660 struct device_link *devlink; 661 662 u32 phyindex; 663 u32 phy_id; 664 665 struct phy_c45_device_ids c45_ids; 666 unsigned is_c45:1; 667 unsigned is_internal:1; 668 unsigned is_pseudo_fixed_link:1; 669 unsigned is_gigabit_capable:1; 670 unsigned has_fixups:1; 671 unsigned suspended:1; 672 unsigned suspended_by_mdio_bus:1; 673 unsigned sysfs_links:1; 674 unsigned loopback_enabled:1; 675 unsigned downshifted_rate:1; 676 unsigned is_on_sfp_module:1; 677 unsigned mac_managed_pm:1; 678 unsigned wol_enabled:1; 679 680 unsigned autoneg:1; 681 /* The most recently read link state */ 682 unsigned link:1; 683 unsigned autoneg_complete:1; 684 685 /* Interrupts are enabled */ 686 unsigned interrupts:1; 687 unsigned irq_suspended:1; 688 unsigned irq_rerun:1; 689 690 unsigned default_timestamp:1; 691 692 int rate_matching; 693 694 enum phy_state state; 695 696 u32 dev_flags; 697 698 phy_interface_t interface; 699 DECLARE_PHY_INTERFACE_MASK(possible_interfaces); 700 701 /* 702 * forced speed & duplex (no autoneg) 703 * partner speed & duplex & pause (autoneg) 704 */ 705 int speed; 706 int duplex; 707 int port; 708 int pause; 709 int asym_pause; 710 u8 master_slave_get; 711 u8 master_slave_set; 712 u8 master_slave_state; 713 714 /* Union of PHY and Attached devices' supported link modes */ 715 /* See ethtool.h for more info */ 716 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); 717 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); 718 __ETHTOOL_DECLARE_LINK_MODE_MASK(lp_advertising); 719 /* used with phy_speed_down */ 720 __ETHTOOL_DECLARE_LINK_MODE_MASK(adv_old); 721 /* used for eee validation and configuration*/ 722 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported_eee); 723 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising_eee); 724 bool eee_enabled; 725 726 /* Host supported PHY interface types. Should be ignored if empty. */ 727 DECLARE_PHY_INTERFACE_MASK(host_interfaces); 728 729 /* Energy efficient ethernet modes which should be prohibited */ 730 u32 eee_broken_modes; 731 bool enable_tx_lpi; 732 struct eee_config eee_cfg; 733 734 #ifdef CONFIG_LED_TRIGGER_PHY 735 struct phy_led_trigger *phy_led_triggers; 736 unsigned int phy_num_led_triggers; 737 struct phy_led_trigger *last_triggered; 738 739 struct phy_led_trigger *led_link_trigger; 740 #endif 741 struct list_head leds; 742 743 /* 744 * Interrupt number for this PHY 745 * -1 means no interrupt 746 */ 747 int irq; 748 749 /* private data pointer */ 750 /* For use by PHYs to maintain extra state */ 751 void *priv; 752 753 /* shared data pointer */ 754 /* For use by PHYs inside the same package that need a shared state. */ 755 struct phy_package_shared *shared; 756 757 /* Reporting cable test results */ 758 struct sk_buff *skb; 759 void *ehdr; 760 struct nlattr *nest; 761 762 /* Interrupt and Polling infrastructure */ 763 struct delayed_work state_queue; 764 765 struct mutex lock; 766 767 /* This may be modified under the rtnl lock */ 768 bool sfp_bus_attached; 769 struct sfp_bus *sfp_bus; 770 struct phylink *phylink; 771 struct net_device *attached_dev; 772 struct mii_timestamper *mii_ts; 773 struct pse_control *psec; 774 775 u8 mdix; 776 u8 mdix_ctrl; 777 778 int pma_extable; 779 780 unsigned int link_down_events; 781 782 void (*phy_link_change)(struct phy_device *phydev, bool up); 783 void (*adjust_link)(struct net_device *dev); 784 785 #if IS_ENABLED(CONFIG_MACSEC) 786 /* MACsec management functions */ 787 const struct macsec_ops *macsec_ops; 788 #endif 789 }; 790 791 /* Generic phy_device::dev_flags */ 792 #define PHY_F_NO_IRQ 0x80000000 793 #define PHY_F_RXC_ALWAYS_ON 0x40000000 794 795 static inline struct phy_device *to_phy_device(const struct device *dev) 796 { 797 return container_of(to_mdio_device(dev), struct phy_device, mdio); 798 } 799 800 /** 801 * struct phy_tdr_config - Configuration of a TDR raw test 802 * 803 * @first: Distance for first data collection point 804 * @last: Distance for last data collection point 805 * @step: Step between data collection points 806 * @pair: Bitmap of cable pairs to collect data for 807 * 808 * A structure containing possible configuration parameters 809 * for a TDR cable test. The driver does not need to implement 810 * all the parameters, but should report what is actually used. 811 * All distances are in centimeters. 812 */ 813 struct phy_tdr_config { 814 u32 first; 815 u32 last; 816 u32 step; 817 s8 pair; 818 }; 819 #define PHY_PAIR_ALL -1 820 821 /** 822 * struct phy_plca_cfg - Configuration of the PLCA (Physical Layer Collision 823 * Avoidance) Reconciliation Sublayer. 824 * 825 * @version: read-only PLCA register map version. -1 = not available. Ignored 826 * when setting the configuration. Format is the same as reported by the PLCA 827 * IDVER register (31.CA00). -1 = not available. 828 * @enabled: PLCA configured mode (enabled/disabled). -1 = not available / don't 829 * set. 0 = disabled, anything else = enabled. 830 * @node_id: the PLCA local node identifier. -1 = not available / don't set. 831 * Allowed values [0 .. 254]. 255 = node disabled. 832 * @node_cnt: the PLCA node count (maximum number of nodes having a TO). Only 833 * meaningful for the coordinator (node_id = 0). -1 = not available / don't 834 * set. Allowed values [1 .. 255]. 835 * @to_tmr: The value of the PLCA to_timer in bit-times, which determines the 836 * PLCA transmit opportunity window opening. See IEEE802.3 Clause 148 for 837 * more details. The to_timer shall be set equal over all nodes. 838 * -1 = not available / don't set. Allowed values [0 .. 255]. 839 * @burst_cnt: controls how many additional frames a node is allowed to send in 840 * single transmit opportunity (TO). The default value of 0 means that the 841 * node is allowed exactly one frame per TO. A value of 1 allows two frames 842 * per TO, and so on. -1 = not available / don't set. 843 * Allowed values [0 .. 255]. 844 * @burst_tmr: controls how many bit times to wait for the MAC to send a new 845 * frame before interrupting the burst. This value should be set to a value 846 * greater than the MAC inter-packet gap (which is typically 96 bits). 847 * -1 = not available / don't set. Allowed values [0 .. 255]. 848 * 849 * A structure containing configuration parameters for setting/getting the PLCA 850 * RS configuration. The driver does not need to implement all the parameters, 851 * but should report what is actually used. 852 */ 853 struct phy_plca_cfg { 854 int version; 855 int enabled; 856 int node_id; 857 int node_cnt; 858 int to_tmr; 859 int burst_cnt; 860 int burst_tmr; 861 }; 862 863 /** 864 * struct phy_plca_status - Status of the PLCA (Physical Layer Collision 865 * Avoidance) Reconciliation Sublayer. 866 * 867 * @pst: The PLCA status as reported by the PST bit in the PLCA STATUS 868 * register(31.CA03), indicating BEACON activity. 869 * 870 * A structure containing status information of the PLCA RS configuration. 871 * The driver does not need to implement all the parameters, but should report 872 * what is actually used. 873 */ 874 struct phy_plca_status { 875 bool pst; 876 }; 877 878 /* Modes for PHY LED configuration */ 879 enum phy_led_modes { 880 PHY_LED_ACTIVE_HIGH = 0, 881 PHY_LED_ACTIVE_LOW = 1, 882 PHY_LED_INACTIVE_HIGH_IMPEDANCE = 2, 883 884 /* keep it last */ 885 __PHY_LED_MODES_NUM, 886 }; 887 888 /** 889 * struct phy_led: An LED driven by the PHY 890 * 891 * @list: List of LEDs 892 * @phydev: PHY this LED is attached to 893 * @led_cdev: Standard LED class structure 894 * @index: Number of the LED 895 */ 896 struct phy_led { 897 struct list_head list; 898 struct phy_device *phydev; 899 struct led_classdev led_cdev; 900 u8 index; 901 }; 902 903 #define to_phy_led(d) container_of(d, struct phy_led, led_cdev) 904 905 /** 906 * struct phy_driver - Driver structure for a particular PHY type 907 * 908 * @mdiodrv: Data common to all MDIO devices 909 * @phy_id: The result of reading the UID registers of this PHY 910 * type, and ANDing them with the phy_id_mask. This driver 911 * only works for PHYs with IDs which match this field 912 * @name: The friendly name of this PHY type 913 * @phy_id_mask: Defines the important bits of the phy_id 914 * @features: A mandatory list of features (speed, duplex, etc) 915 * supported by this PHY 916 * @flags: A bitfield defining certain other features this PHY 917 * supports (like interrupts) 918 * @driver_data: Static driver data 919 * 920 * All functions are optional. If config_aneg or read_status 921 * are not implemented, the phy core uses the genphy versions. 922 * Note that none of these functions should be called from 923 * interrupt time. The goal is for the bus read/write functions 924 * to be able to block when the bus transaction is happening, 925 * and be freed up by an interrupt (The MPC85xx has this ability, 926 * though it is not currently supported in the driver). 927 */ 928 struct phy_driver { 929 struct mdio_driver_common mdiodrv; 930 u32 phy_id; 931 char *name; 932 u32 phy_id_mask; 933 const unsigned long * const features; 934 u32 flags; 935 const void *driver_data; 936 937 /** 938 * @soft_reset: Called to issue a PHY software reset 939 */ 940 int (*soft_reset)(struct phy_device *phydev); 941 942 /** 943 * @config_init: Called to initialize the PHY, 944 * including after a reset 945 */ 946 int (*config_init)(struct phy_device *phydev); 947 948 /** 949 * @probe: Called during discovery. Used to set 950 * up device-specific structures, if any 951 */ 952 int (*probe)(struct phy_device *phydev); 953 954 /** 955 * @get_features: Probe the hardware to determine what 956 * abilities it has. Should only set phydev->supported. 957 */ 958 int (*get_features)(struct phy_device *phydev); 959 960 /** 961 * @get_rate_matching: Get the supported type of rate matching for a 962 * particular phy interface. This is used by phy consumers to determine 963 * whether to advertise lower-speed modes for that interface. It is 964 * assumed that if a rate matching mode is supported on an interface, 965 * then that interface's rate can be adapted to all slower link speeds 966 * supported by the phy. If the interface is not supported, this should 967 * return %RATE_MATCH_NONE. 968 */ 969 int (*get_rate_matching)(struct phy_device *phydev, 970 phy_interface_t iface); 971 972 /* PHY Power Management */ 973 /** @suspend: Suspend the hardware, saving state if needed */ 974 int (*suspend)(struct phy_device *phydev); 975 /** @resume: Resume the hardware, restoring state if needed */ 976 int (*resume)(struct phy_device *phydev); 977 978 /** 979 * @config_aneg: Configures the advertisement and resets 980 * autonegotiation if phydev->autoneg is on, 981 * forces the speed to the current settings in phydev 982 * if phydev->autoneg is off 983 */ 984 int (*config_aneg)(struct phy_device *phydev); 985 986 /** @aneg_done: Determines the auto negotiation result */ 987 int (*aneg_done)(struct phy_device *phydev); 988 989 /** @read_status: Determines the negotiated speed and duplex */ 990 int (*read_status)(struct phy_device *phydev); 991 992 /** 993 * @config_intr: Enables or disables interrupts. 994 * It should also clear any pending interrupts prior to enabling the 995 * IRQs and after disabling them. 996 */ 997 int (*config_intr)(struct phy_device *phydev); 998 999 /** @handle_interrupt: Override default interrupt handling */ 1000 irqreturn_t (*handle_interrupt)(struct phy_device *phydev); 1001 1002 /** @remove: Clears up any memory if needed */ 1003 void (*remove)(struct phy_device *phydev); 1004 1005 /** 1006 * @match_phy_device: Returns true if this is a suitable 1007 * driver for the given phydev. If NULL, matching is based on 1008 * phy_id and phy_id_mask. 1009 */ 1010 int (*match_phy_device)(struct phy_device *phydev); 1011 1012 /** 1013 * @set_wol: Some devices (e.g. qnap TS-119P II) require PHY 1014 * register changes to enable Wake on LAN, so set_wol is 1015 * provided to be called in the ethernet driver's set_wol 1016 * function. 1017 */ 1018 int (*set_wol)(struct phy_device *dev, struct ethtool_wolinfo *wol); 1019 1020 /** 1021 * @get_wol: See set_wol, but for checking whether Wake on LAN 1022 * is enabled. 1023 */ 1024 void (*get_wol)(struct phy_device *dev, struct ethtool_wolinfo *wol); 1025 1026 /** 1027 * @link_change_notify: Called to inform a PHY device driver 1028 * when the core is about to change the link state. This 1029 * callback is supposed to be used as fixup hook for drivers 1030 * that need to take action when the link state 1031 * changes. Drivers are by no means allowed to mess with the 1032 * PHY device structure in their implementations. 1033 */ 1034 void (*link_change_notify)(struct phy_device *dev); 1035 1036 /** 1037 * @read_mmd: PHY specific driver override for reading a MMD 1038 * register. This function is optional for PHY specific 1039 * drivers. When not provided, the default MMD read function 1040 * will be used by phy_read_mmd(), which will use either a 1041 * direct read for Clause 45 PHYs or an indirect read for 1042 * Clause 22 PHYs. devnum is the MMD device number within the 1043 * PHY device, regnum is the register within the selected MMD 1044 * device. 1045 */ 1046 int (*read_mmd)(struct phy_device *dev, int devnum, u16 regnum); 1047 1048 /** 1049 * @write_mmd: PHY specific driver override for writing a MMD 1050 * register. This function is optional for PHY specific 1051 * drivers. When not provided, the default MMD write function 1052 * will be used by phy_write_mmd(), which will use either a 1053 * direct write for Clause 45 PHYs, or an indirect write for 1054 * Clause 22 PHYs. devnum is the MMD device number within the 1055 * PHY device, regnum is the register within the selected MMD 1056 * device. val is the value to be written. 1057 */ 1058 int (*write_mmd)(struct phy_device *dev, int devnum, u16 regnum, 1059 u16 val); 1060 1061 /** @read_page: Return the current PHY register page number */ 1062 int (*read_page)(struct phy_device *dev); 1063 /** @write_page: Set the current PHY register page number */ 1064 int (*write_page)(struct phy_device *dev, int page); 1065 1066 /** 1067 * @module_info: Get the size and type of the eeprom contained 1068 * within a plug-in module 1069 */ 1070 int (*module_info)(struct phy_device *dev, 1071 struct ethtool_modinfo *modinfo); 1072 1073 /** 1074 * @module_eeprom: Get the eeprom information from the plug-in 1075 * module 1076 */ 1077 int (*module_eeprom)(struct phy_device *dev, 1078 struct ethtool_eeprom *ee, u8 *data); 1079 1080 /** @cable_test_start: Start a cable test */ 1081 int (*cable_test_start)(struct phy_device *dev); 1082 1083 /** @cable_test_tdr_start: Start a raw TDR cable test */ 1084 int (*cable_test_tdr_start)(struct phy_device *dev, 1085 const struct phy_tdr_config *config); 1086 1087 /** 1088 * @cable_test_get_status: Once per second, or on interrupt, 1089 * request the status of the test. 1090 */ 1091 int (*cable_test_get_status)(struct phy_device *dev, bool *finished); 1092 1093 /* Get statistics from the PHY using ethtool */ 1094 /** @get_sset_count: Number of statistic counters */ 1095 int (*get_sset_count)(struct phy_device *dev); 1096 /** @get_strings: Names of the statistic counters */ 1097 void (*get_strings)(struct phy_device *dev, u8 *data); 1098 /** @get_stats: Return the statistic counter values */ 1099 void (*get_stats)(struct phy_device *dev, 1100 struct ethtool_stats *stats, u64 *data); 1101 1102 /* Get and Set PHY tunables */ 1103 /** @get_tunable: Return the value of a tunable */ 1104 int (*get_tunable)(struct phy_device *dev, 1105 struct ethtool_tunable *tuna, void *data); 1106 /** @set_tunable: Set the value of a tunable */ 1107 int (*set_tunable)(struct phy_device *dev, 1108 struct ethtool_tunable *tuna, 1109 const void *data); 1110 /** @set_loopback: Set the loopback mood of the PHY */ 1111 int (*set_loopback)(struct phy_device *dev, bool enable); 1112 /** @get_sqi: Get the signal quality indication */ 1113 int (*get_sqi)(struct phy_device *dev); 1114 /** @get_sqi_max: Get the maximum signal quality indication */ 1115 int (*get_sqi_max)(struct phy_device *dev); 1116 1117 /* PLCA RS interface */ 1118 /** @get_plca_cfg: Return the current PLCA configuration */ 1119 int (*get_plca_cfg)(struct phy_device *dev, 1120 struct phy_plca_cfg *plca_cfg); 1121 /** @set_plca_cfg: Set the PLCA configuration */ 1122 int (*set_plca_cfg)(struct phy_device *dev, 1123 const struct phy_plca_cfg *plca_cfg); 1124 /** @get_plca_status: Return the current PLCA status info */ 1125 int (*get_plca_status)(struct phy_device *dev, 1126 struct phy_plca_status *plca_st); 1127 1128 /** 1129 * @led_brightness_set: Set a PHY LED brightness. Index 1130 * indicates which of the PHYs led should be set. Value 1131 * follows the standard LED class meaning, e.g. LED_OFF, 1132 * LED_HALF, LED_FULL. 1133 */ 1134 int (*led_brightness_set)(struct phy_device *dev, 1135 u8 index, enum led_brightness value); 1136 1137 /** 1138 * @led_blink_set: Set a PHY LED blinking. Index indicates 1139 * which of the PHYs led should be configured to blink. Delays 1140 * are in milliseconds and if both are zero then a sensible 1141 * default should be chosen. The call should adjust the 1142 * timings in that case and if it can't match the values 1143 * specified exactly. 1144 */ 1145 int (*led_blink_set)(struct phy_device *dev, u8 index, 1146 unsigned long *delay_on, 1147 unsigned long *delay_off); 1148 /** 1149 * @led_hw_is_supported: Can the HW support the given rules. 1150 * @dev: PHY device which has the LED 1151 * @index: Which LED of the PHY device 1152 * @rules The core is interested in these rules 1153 * 1154 * Return 0 if yes, -EOPNOTSUPP if not, or an error code. 1155 */ 1156 int (*led_hw_is_supported)(struct phy_device *dev, u8 index, 1157 unsigned long rules); 1158 /** 1159 * @led_hw_control_set: Set the HW to control the LED 1160 * @dev: PHY device which has the LED 1161 * @index: Which LED of the PHY device 1162 * @rules The rules used to control the LED 1163 * 1164 * Returns 0, or a an error code. 1165 */ 1166 int (*led_hw_control_set)(struct phy_device *dev, u8 index, 1167 unsigned long rules); 1168 /** 1169 * @led_hw_control_get: Get how the HW is controlling the LED 1170 * @dev: PHY device which has the LED 1171 * @index: Which LED of the PHY device 1172 * @rules Pointer to the rules used to control the LED 1173 * 1174 * Set *@rules to how the HW is currently blinking. Returns 0 1175 * on success, or a error code if the current blinking cannot 1176 * be represented in rules, or some other error happens. 1177 */ 1178 int (*led_hw_control_get)(struct phy_device *dev, u8 index, 1179 unsigned long *rules); 1180 1181 /** 1182 * @led_polarity_set: Set the LED polarity modes 1183 * @dev: PHY device which has the LED 1184 * @index: Which LED of the PHY device 1185 * @modes: bitmap of LED polarity modes 1186 * 1187 * Configure LED with all the required polarity modes in @modes 1188 * to make it correctly turn ON or OFF. 1189 * 1190 * Returns 0, or an error code. 1191 */ 1192 int (*led_polarity_set)(struct phy_device *dev, int index, 1193 unsigned long modes); 1194 }; 1195 #define to_phy_driver(d) container_of_const(to_mdio_common_driver(d), \ 1196 struct phy_driver, mdiodrv) 1197 1198 #define PHY_ANY_ID "MATCH ANY PHY" 1199 #define PHY_ANY_UID 0xffffffff 1200 1201 #define PHY_ID_MATCH_EXACT(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 0) 1202 #define PHY_ID_MATCH_MODEL(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 4) 1203 #define PHY_ID_MATCH_VENDOR(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 10) 1204 1205 /** 1206 * phy_id_compare - compare @id1 with @id2 taking account of @mask 1207 * @id1: first PHY ID 1208 * @id2: second PHY ID 1209 * @mask: the PHY ID mask, set bits are significant in matching 1210 * 1211 * Return true if the bits from @id1 and @id2 specified by @mask match. 1212 * This uses an equivalent test to (@id & @mask) == (@phy_id & @mask). 1213 */ 1214 static inline bool phy_id_compare(u32 id1, u32 id2, u32 mask) 1215 { 1216 return !((id1 ^ id2) & mask); 1217 } 1218 1219 /** 1220 * phydev_id_compare - compare @id with the PHY's Clause 22 ID 1221 * @phydev: the PHY device 1222 * @id: the PHY ID to be matched 1223 * 1224 * Compare the @phydev clause 22 ID with the provided @id and return true or 1225 * false depending whether it matches, using the bound driver mask. The 1226 * @phydev must be bound to a driver. 1227 */ 1228 static inline bool phydev_id_compare(struct phy_device *phydev, u32 id) 1229 { 1230 return phy_id_compare(id, phydev->phy_id, phydev->drv->phy_id_mask); 1231 } 1232 1233 /* A Structure for boards to register fixups with the PHY Lib */ 1234 struct phy_fixup { 1235 struct list_head list; 1236 char bus_id[MII_BUS_ID_SIZE + 3]; 1237 u32 phy_uid; 1238 u32 phy_uid_mask; 1239 int (*run)(struct phy_device *phydev); 1240 }; 1241 1242 const char *phy_speed_to_str(int speed); 1243 const char *phy_duplex_to_str(unsigned int duplex); 1244 const char *phy_rate_matching_to_str(int rate_matching); 1245 1246 int phy_interface_num_ports(phy_interface_t interface); 1247 1248 /* A structure for mapping a particular speed and duplex 1249 * combination to a particular SUPPORTED and ADVERTISED value 1250 */ 1251 struct phy_setting { 1252 u32 speed; 1253 u8 duplex; 1254 u8 bit; 1255 }; 1256 1257 const struct phy_setting * 1258 phy_lookup_setting(int speed, int duplex, const unsigned long *mask, 1259 bool exact); 1260 size_t phy_speeds(unsigned int *speeds, size_t size, 1261 unsigned long *mask); 1262 void of_set_phy_supported(struct phy_device *phydev); 1263 void of_set_phy_eee_broken(struct phy_device *phydev); 1264 void of_set_phy_timing_role(struct phy_device *phydev); 1265 int phy_speed_down_core(struct phy_device *phydev); 1266 1267 /** 1268 * phy_is_started - Convenience function to check whether PHY is started 1269 * @phydev: The phy_device struct 1270 */ 1271 static inline bool phy_is_started(struct phy_device *phydev) 1272 { 1273 return phydev->state >= PHY_UP; 1274 } 1275 1276 void phy_resolve_aneg_pause(struct phy_device *phydev); 1277 void phy_resolve_aneg_linkmode(struct phy_device *phydev); 1278 void phy_check_downshift(struct phy_device *phydev); 1279 1280 /** 1281 * phy_read - Convenience function for reading a given PHY register 1282 * @phydev: the phy_device struct 1283 * @regnum: register number to read 1284 * 1285 * NOTE: MUST NOT be called from interrupt context, 1286 * because the bus read/write functions may wait for an interrupt 1287 * to conclude the operation. 1288 */ 1289 static inline int phy_read(struct phy_device *phydev, u32 regnum) 1290 { 1291 return mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, regnum); 1292 } 1293 1294 #define phy_read_poll_timeout(phydev, regnum, val, cond, sleep_us, \ 1295 timeout_us, sleep_before_read) \ 1296 ({ \ 1297 int __ret, __val; \ 1298 __ret = read_poll_timeout(__val = phy_read, val, \ 1299 __val < 0 || (cond), \ 1300 sleep_us, timeout_us, sleep_before_read, phydev, regnum); \ 1301 if (__val < 0) \ 1302 __ret = __val; \ 1303 if (__ret) \ 1304 phydev_err(phydev, "%s failed: %d\n", __func__, __ret); \ 1305 __ret; \ 1306 }) 1307 1308 /** 1309 * __phy_read - convenience function for reading a given PHY register 1310 * @phydev: the phy_device struct 1311 * @regnum: register number to read 1312 * 1313 * The caller must have taken the MDIO bus lock. 1314 */ 1315 static inline int __phy_read(struct phy_device *phydev, u32 regnum) 1316 { 1317 return __mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, regnum); 1318 } 1319 1320 /** 1321 * phy_write - Convenience function for writing a given PHY register 1322 * @phydev: the phy_device struct 1323 * @regnum: register number to write 1324 * @val: value to write to @regnum 1325 * 1326 * NOTE: MUST NOT be called from interrupt context, 1327 * because the bus read/write functions may wait for an interrupt 1328 * to conclude the operation. 1329 */ 1330 static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val) 1331 { 1332 return mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, regnum, val); 1333 } 1334 1335 /** 1336 * __phy_write - Convenience function for writing a given PHY register 1337 * @phydev: the phy_device struct 1338 * @regnum: register number to write 1339 * @val: value to write to @regnum 1340 * 1341 * The caller must have taken the MDIO bus lock. 1342 */ 1343 static inline int __phy_write(struct phy_device *phydev, u32 regnum, u16 val) 1344 { 1345 return __mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, regnum, 1346 val); 1347 } 1348 1349 /** 1350 * __phy_modify_changed() - Convenience function for modifying a PHY register 1351 * @phydev: a pointer to a &struct phy_device 1352 * @regnum: register number 1353 * @mask: bit mask of bits to clear 1354 * @set: bit mask of bits to set 1355 * 1356 * Unlocked helper function which allows a PHY register to be modified as 1357 * new register value = (old register value & ~mask) | set 1358 * 1359 * Returns negative errno, 0 if there was no change, and 1 in case of change 1360 */ 1361 static inline int __phy_modify_changed(struct phy_device *phydev, u32 regnum, 1362 u16 mask, u16 set) 1363 { 1364 return __mdiobus_modify_changed(phydev->mdio.bus, phydev->mdio.addr, 1365 regnum, mask, set); 1366 } 1367 1368 /* 1369 * phy_read_mmd - Convenience function for reading a register 1370 * from an MMD on a given PHY. 1371 */ 1372 int phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum); 1373 1374 /** 1375 * phy_read_mmd_poll_timeout - Periodically poll a PHY register until a 1376 * condition is met or a timeout occurs 1377 * 1378 * @phydev: The phy_device struct 1379 * @devaddr: The MMD to read from 1380 * @regnum: The register on the MMD to read 1381 * @val: Variable to read the register into 1382 * @cond: Break condition (usually involving @val) 1383 * @sleep_us: Maximum time to sleep between reads in us (0 1384 * tight-loops). Should be less than ~20ms since usleep_range 1385 * is used (see Documentation/timers/timers-howto.rst). 1386 * @timeout_us: Timeout in us, 0 means never timeout 1387 * @sleep_before_read: if it is true, sleep @sleep_us before read. 1388 * Returns 0 on success and -ETIMEDOUT upon a timeout. In either 1389 * case, the last read value at @args is stored in @val. Must not 1390 * be called from atomic context if sleep_us or timeout_us are used. 1391 */ 1392 #define phy_read_mmd_poll_timeout(phydev, devaddr, regnum, val, cond, \ 1393 sleep_us, timeout_us, sleep_before_read) \ 1394 ({ \ 1395 int __ret, __val; \ 1396 __ret = read_poll_timeout(__val = phy_read_mmd, val, \ 1397 __val < 0 || (cond), \ 1398 sleep_us, timeout_us, sleep_before_read, \ 1399 phydev, devaddr, regnum); \ 1400 if (__val < 0) \ 1401 __ret = __val; \ 1402 if (__ret) \ 1403 phydev_err(phydev, "%s failed: %d\n", __func__, __ret); \ 1404 __ret; \ 1405 }) 1406 1407 /* 1408 * __phy_read_mmd - Convenience function for reading a register 1409 * from an MMD on a given PHY. 1410 */ 1411 int __phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum); 1412 1413 /* 1414 * phy_write_mmd - Convenience function for writing a register 1415 * on an MMD on a given PHY. 1416 */ 1417 int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val); 1418 1419 /* 1420 * __phy_write_mmd - Convenience function for writing a register 1421 * on an MMD on a given PHY. 1422 */ 1423 int __phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val); 1424 1425 int __phy_modify_changed(struct phy_device *phydev, u32 regnum, u16 mask, 1426 u16 set); 1427 int phy_modify_changed(struct phy_device *phydev, u32 regnum, u16 mask, 1428 u16 set); 1429 int __phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set); 1430 int phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set); 1431 1432 int __phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum, 1433 u16 mask, u16 set); 1434 int phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum, 1435 u16 mask, u16 set); 1436 int __phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum, 1437 u16 mask, u16 set); 1438 int phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum, 1439 u16 mask, u16 set); 1440 1441 /** 1442 * __phy_set_bits - Convenience function for setting bits in a PHY register 1443 * @phydev: the phy_device struct 1444 * @regnum: register number to write 1445 * @val: bits to set 1446 * 1447 * The caller must have taken the MDIO bus lock. 1448 */ 1449 static inline int __phy_set_bits(struct phy_device *phydev, u32 regnum, u16 val) 1450 { 1451 return __phy_modify(phydev, regnum, 0, val); 1452 } 1453 1454 /** 1455 * __phy_clear_bits - Convenience function for clearing bits in a PHY register 1456 * @phydev: the phy_device struct 1457 * @regnum: register number to write 1458 * @val: bits to clear 1459 * 1460 * The caller must have taken the MDIO bus lock. 1461 */ 1462 static inline int __phy_clear_bits(struct phy_device *phydev, u32 regnum, 1463 u16 val) 1464 { 1465 return __phy_modify(phydev, regnum, val, 0); 1466 } 1467 1468 /** 1469 * phy_set_bits - Convenience function for setting bits in a PHY register 1470 * @phydev: the phy_device struct 1471 * @regnum: register number to write 1472 * @val: bits to set 1473 */ 1474 static inline int phy_set_bits(struct phy_device *phydev, u32 regnum, u16 val) 1475 { 1476 return phy_modify(phydev, regnum, 0, val); 1477 } 1478 1479 /** 1480 * phy_clear_bits - Convenience function for clearing bits in a PHY register 1481 * @phydev: the phy_device struct 1482 * @regnum: register number to write 1483 * @val: bits to clear 1484 */ 1485 static inline int phy_clear_bits(struct phy_device *phydev, u32 regnum, u16 val) 1486 { 1487 return phy_modify(phydev, regnum, val, 0); 1488 } 1489 1490 /** 1491 * __phy_set_bits_mmd - Convenience function for setting bits in a register 1492 * on MMD 1493 * @phydev: the phy_device struct 1494 * @devad: the MMD containing register to modify 1495 * @regnum: register number to modify 1496 * @val: bits to set 1497 * 1498 * The caller must have taken the MDIO bus lock. 1499 */ 1500 static inline int __phy_set_bits_mmd(struct phy_device *phydev, int devad, 1501 u32 regnum, u16 val) 1502 { 1503 return __phy_modify_mmd(phydev, devad, regnum, 0, val); 1504 } 1505 1506 /** 1507 * __phy_clear_bits_mmd - Convenience function for clearing bits in a register 1508 * on MMD 1509 * @phydev: the phy_device struct 1510 * @devad: the MMD containing register to modify 1511 * @regnum: register number to modify 1512 * @val: bits to clear 1513 * 1514 * The caller must have taken the MDIO bus lock. 1515 */ 1516 static inline int __phy_clear_bits_mmd(struct phy_device *phydev, int devad, 1517 u32 regnum, u16 val) 1518 { 1519 return __phy_modify_mmd(phydev, devad, regnum, val, 0); 1520 } 1521 1522 /** 1523 * phy_set_bits_mmd - Convenience function for setting bits in a register 1524 * on MMD 1525 * @phydev: the phy_device struct 1526 * @devad: the MMD containing register to modify 1527 * @regnum: register number to modify 1528 * @val: bits to set 1529 */ 1530 static inline int phy_set_bits_mmd(struct phy_device *phydev, int devad, 1531 u32 regnum, u16 val) 1532 { 1533 return phy_modify_mmd(phydev, devad, regnum, 0, val); 1534 } 1535 1536 /** 1537 * phy_clear_bits_mmd - Convenience function for clearing bits in a register 1538 * on MMD 1539 * @phydev: the phy_device struct 1540 * @devad: the MMD containing register to modify 1541 * @regnum: register number to modify 1542 * @val: bits to clear 1543 */ 1544 static inline int phy_clear_bits_mmd(struct phy_device *phydev, int devad, 1545 u32 regnum, u16 val) 1546 { 1547 return phy_modify_mmd(phydev, devad, regnum, val, 0); 1548 } 1549 1550 /** 1551 * phy_interrupt_is_valid - Convenience function for testing a given PHY irq 1552 * @phydev: the phy_device struct 1553 * 1554 * NOTE: must be kept in sync with addition/removal of PHY_POLL and 1555 * PHY_MAC_INTERRUPT 1556 */ 1557 static inline bool phy_interrupt_is_valid(struct phy_device *phydev) 1558 { 1559 return phydev->irq != PHY_POLL && phydev->irq != PHY_MAC_INTERRUPT; 1560 } 1561 1562 /** 1563 * phy_polling_mode - Convenience function for testing whether polling is 1564 * used to detect PHY status changes 1565 * @phydev: the phy_device struct 1566 */ 1567 static inline bool phy_polling_mode(struct phy_device *phydev) 1568 { 1569 if (phydev->state == PHY_CABLETEST) 1570 if (phydev->drv->flags & PHY_POLL_CABLE_TEST) 1571 return true; 1572 1573 return phydev->irq == PHY_POLL; 1574 } 1575 1576 /** 1577 * phy_has_hwtstamp - Tests whether a PHY time stamp configuration. 1578 * @phydev: the phy_device struct 1579 */ 1580 static inline bool phy_has_hwtstamp(struct phy_device *phydev) 1581 { 1582 return phydev && phydev->mii_ts && phydev->mii_ts->hwtstamp; 1583 } 1584 1585 /** 1586 * phy_has_rxtstamp - Tests whether a PHY supports receive time stamping. 1587 * @phydev: the phy_device struct 1588 */ 1589 static inline bool phy_has_rxtstamp(struct phy_device *phydev) 1590 { 1591 return phydev && phydev->mii_ts && phydev->mii_ts->rxtstamp; 1592 } 1593 1594 /** 1595 * phy_has_tsinfo - Tests whether a PHY reports time stamping and/or 1596 * PTP hardware clock capabilities. 1597 * @phydev: the phy_device struct 1598 */ 1599 static inline bool phy_has_tsinfo(struct phy_device *phydev) 1600 { 1601 return phydev && phydev->mii_ts && phydev->mii_ts->ts_info; 1602 } 1603 1604 /** 1605 * phy_has_txtstamp - Tests whether a PHY supports transmit time stamping. 1606 * @phydev: the phy_device struct 1607 */ 1608 static inline bool phy_has_txtstamp(struct phy_device *phydev) 1609 { 1610 return phydev && phydev->mii_ts && phydev->mii_ts->txtstamp; 1611 } 1612 1613 static inline int phy_hwtstamp(struct phy_device *phydev, 1614 struct kernel_hwtstamp_config *cfg, 1615 struct netlink_ext_ack *extack) 1616 { 1617 return phydev->mii_ts->hwtstamp(phydev->mii_ts, cfg, extack); 1618 } 1619 1620 static inline bool phy_rxtstamp(struct phy_device *phydev, struct sk_buff *skb, 1621 int type) 1622 { 1623 return phydev->mii_ts->rxtstamp(phydev->mii_ts, skb, type); 1624 } 1625 1626 static inline int phy_ts_info(struct phy_device *phydev, 1627 struct kernel_ethtool_ts_info *tsinfo) 1628 { 1629 return phydev->mii_ts->ts_info(phydev->mii_ts, tsinfo); 1630 } 1631 1632 static inline void phy_txtstamp(struct phy_device *phydev, struct sk_buff *skb, 1633 int type) 1634 { 1635 phydev->mii_ts->txtstamp(phydev->mii_ts, skb, type); 1636 } 1637 1638 /** 1639 * phy_is_default_hwtstamp - Is the PHY hwtstamp the default timestamp 1640 * @phydev: Pointer to phy_device 1641 * 1642 * This is used to get default timestamping device taking into account 1643 * the new API choice, which is selecting the timestamping from MAC by 1644 * default if the phydev does not have default_timestamp flag enabled. 1645 * 1646 * Return: True if phy is the default hw timestamp, false otherwise. 1647 */ 1648 static inline bool phy_is_default_hwtstamp(struct phy_device *phydev) 1649 { 1650 return phy_has_hwtstamp(phydev) && phydev->default_timestamp; 1651 } 1652 1653 /** 1654 * phy_is_internal - Convenience function for testing if a PHY is internal 1655 * @phydev: the phy_device struct 1656 */ 1657 static inline bool phy_is_internal(struct phy_device *phydev) 1658 { 1659 return phydev->is_internal; 1660 } 1661 1662 /** 1663 * phy_on_sfp - Convenience function for testing if a PHY is on an SFP module 1664 * @phydev: the phy_device struct 1665 */ 1666 static inline bool phy_on_sfp(struct phy_device *phydev) 1667 { 1668 return phydev->is_on_sfp_module; 1669 } 1670 1671 /** 1672 * phy_interface_mode_is_rgmii - Convenience function for testing if a 1673 * PHY interface mode is RGMII (all variants) 1674 * @mode: the &phy_interface_t enum 1675 */ 1676 static inline bool phy_interface_mode_is_rgmii(phy_interface_t mode) 1677 { 1678 return mode >= PHY_INTERFACE_MODE_RGMII && 1679 mode <= PHY_INTERFACE_MODE_RGMII_TXID; 1680 }; 1681 1682 /** 1683 * phy_interface_mode_is_8023z() - does the PHY interface mode use 802.3z 1684 * negotiation 1685 * @mode: one of &enum phy_interface_t 1686 * 1687 * Returns true if the PHY interface mode uses the 16-bit negotiation 1688 * word as defined in 802.3z. (See 802.3-2015 37.2.1 Config_Reg encoding) 1689 */ 1690 static inline bool phy_interface_mode_is_8023z(phy_interface_t mode) 1691 { 1692 return mode == PHY_INTERFACE_MODE_1000BASEX || 1693 mode == PHY_INTERFACE_MODE_2500BASEX; 1694 } 1695 1696 /** 1697 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface 1698 * is RGMII (all variants) 1699 * @phydev: the phy_device struct 1700 */ 1701 static inline bool phy_interface_is_rgmii(struct phy_device *phydev) 1702 { 1703 return phy_interface_mode_is_rgmii(phydev->interface); 1704 }; 1705 1706 /** 1707 * phy_is_pseudo_fixed_link - Convenience function for testing if this 1708 * PHY is the CPU port facing side of an Ethernet switch, or similar. 1709 * @phydev: the phy_device struct 1710 */ 1711 static inline bool phy_is_pseudo_fixed_link(struct phy_device *phydev) 1712 { 1713 return phydev->is_pseudo_fixed_link; 1714 } 1715 1716 int phy_save_page(struct phy_device *phydev); 1717 int phy_select_page(struct phy_device *phydev, int page); 1718 int phy_restore_page(struct phy_device *phydev, int oldpage, int ret); 1719 int phy_read_paged(struct phy_device *phydev, int page, u32 regnum); 1720 int phy_write_paged(struct phy_device *phydev, int page, u32 regnum, u16 val); 1721 int phy_modify_paged_changed(struct phy_device *phydev, int page, u32 regnum, 1722 u16 mask, u16 set); 1723 int phy_modify_paged(struct phy_device *phydev, int page, u32 regnum, 1724 u16 mask, u16 set); 1725 1726 struct phy_device *phy_device_create(struct mii_bus *bus, int addr, u32 phy_id, 1727 bool is_c45, 1728 struct phy_c45_device_ids *c45_ids); 1729 #if IS_ENABLED(CONFIG_PHYLIB) 1730 int fwnode_get_phy_id(struct fwnode_handle *fwnode, u32 *phy_id); 1731 struct mdio_device *fwnode_mdio_find_device(struct fwnode_handle *fwnode); 1732 struct phy_device *fwnode_phy_find_device(struct fwnode_handle *phy_fwnode); 1733 struct phy_device *device_phy_find_device(struct device *dev); 1734 struct fwnode_handle *fwnode_get_phy_node(const struct fwnode_handle *fwnode); 1735 struct phy_device *get_phy_device(struct mii_bus *bus, int addr, bool is_c45); 1736 int phy_device_register(struct phy_device *phy); 1737 void phy_device_free(struct phy_device *phydev); 1738 #else 1739 static inline int fwnode_get_phy_id(struct fwnode_handle *fwnode, u32 *phy_id) 1740 { 1741 return 0; 1742 } 1743 static inline 1744 struct mdio_device *fwnode_mdio_find_device(struct fwnode_handle *fwnode) 1745 { 1746 return 0; 1747 } 1748 1749 static inline 1750 struct phy_device *fwnode_phy_find_device(struct fwnode_handle *phy_fwnode) 1751 { 1752 return NULL; 1753 } 1754 1755 static inline struct phy_device *device_phy_find_device(struct device *dev) 1756 { 1757 return NULL; 1758 } 1759 1760 static inline 1761 struct fwnode_handle *fwnode_get_phy_node(struct fwnode_handle *fwnode) 1762 { 1763 return NULL; 1764 } 1765 1766 static inline 1767 struct phy_device *get_phy_device(struct mii_bus *bus, int addr, bool is_c45) 1768 { 1769 return NULL; 1770 } 1771 1772 static inline int phy_device_register(struct phy_device *phy) 1773 { 1774 return 0; 1775 } 1776 1777 static inline void phy_device_free(struct phy_device *phydev) { } 1778 #endif /* CONFIG_PHYLIB */ 1779 void phy_device_remove(struct phy_device *phydev); 1780 int phy_get_c45_ids(struct phy_device *phydev); 1781 int phy_init_hw(struct phy_device *phydev); 1782 int phy_suspend(struct phy_device *phydev); 1783 int phy_resume(struct phy_device *phydev); 1784 int __phy_resume(struct phy_device *phydev); 1785 int phy_loopback(struct phy_device *phydev, bool enable); 1786 int phy_sfp_connect_phy(void *upstream, struct phy_device *phy); 1787 void phy_sfp_disconnect_phy(void *upstream, struct phy_device *phy); 1788 void phy_sfp_attach(void *upstream, struct sfp_bus *bus); 1789 void phy_sfp_detach(void *upstream, struct sfp_bus *bus); 1790 int phy_sfp_probe(struct phy_device *phydev, 1791 const struct sfp_upstream_ops *ops); 1792 struct phy_device *phy_attach(struct net_device *dev, const char *bus_id, 1793 phy_interface_t interface); 1794 struct phy_device *phy_find_first(struct mii_bus *bus); 1795 int phy_attach_direct(struct net_device *dev, struct phy_device *phydev, 1796 u32 flags, phy_interface_t interface); 1797 int phy_connect_direct(struct net_device *dev, struct phy_device *phydev, 1798 void (*handler)(struct net_device *), 1799 phy_interface_t interface); 1800 struct phy_device *phy_connect(struct net_device *dev, const char *bus_id, 1801 void (*handler)(struct net_device *), 1802 phy_interface_t interface); 1803 void phy_disconnect(struct phy_device *phydev); 1804 void phy_detach(struct phy_device *phydev); 1805 void phy_start(struct phy_device *phydev); 1806 void phy_stop(struct phy_device *phydev); 1807 int phy_config_aneg(struct phy_device *phydev); 1808 int _phy_start_aneg(struct phy_device *phydev); 1809 int phy_start_aneg(struct phy_device *phydev); 1810 int phy_aneg_done(struct phy_device *phydev); 1811 int phy_speed_down(struct phy_device *phydev, bool sync); 1812 int phy_speed_up(struct phy_device *phydev); 1813 bool phy_check_valid(int speed, int duplex, unsigned long *features); 1814 1815 int phy_restart_aneg(struct phy_device *phydev); 1816 int phy_reset_after_clk_enable(struct phy_device *phydev); 1817 1818 #if IS_ENABLED(CONFIG_PHYLIB) 1819 int phy_start_cable_test(struct phy_device *phydev, 1820 struct netlink_ext_ack *extack); 1821 int phy_start_cable_test_tdr(struct phy_device *phydev, 1822 struct netlink_ext_ack *extack, 1823 const struct phy_tdr_config *config); 1824 #else 1825 static inline 1826 int phy_start_cable_test(struct phy_device *phydev, 1827 struct netlink_ext_ack *extack) 1828 { 1829 NL_SET_ERR_MSG(extack, "Kernel not compiled with PHYLIB support"); 1830 return -EOPNOTSUPP; 1831 } 1832 static inline 1833 int phy_start_cable_test_tdr(struct phy_device *phydev, 1834 struct netlink_ext_ack *extack, 1835 const struct phy_tdr_config *config) 1836 { 1837 NL_SET_ERR_MSG(extack, "Kernel not compiled with PHYLIB support"); 1838 return -EOPNOTSUPP; 1839 } 1840 #endif 1841 1842 static inline void phy_device_reset(struct phy_device *phydev, int value) 1843 { 1844 mdio_device_reset(&phydev->mdio, value); 1845 } 1846 1847 #define phydev_err(_phydev, format, args...) \ 1848 dev_err(&_phydev->mdio.dev, format, ##args) 1849 1850 #define phydev_err_probe(_phydev, err, format, args...) \ 1851 dev_err_probe(&_phydev->mdio.dev, err, format, ##args) 1852 1853 #define phydev_info(_phydev, format, args...) \ 1854 dev_info(&_phydev->mdio.dev, format, ##args) 1855 1856 #define phydev_warn(_phydev, format, args...) \ 1857 dev_warn(&_phydev->mdio.dev, format, ##args) 1858 1859 #define phydev_dbg(_phydev, format, args...) \ 1860 dev_dbg(&_phydev->mdio.dev, format, ##args) 1861 1862 static inline const char *phydev_name(const struct phy_device *phydev) 1863 { 1864 return dev_name(&phydev->mdio.dev); 1865 } 1866 1867 static inline void phy_lock_mdio_bus(struct phy_device *phydev) 1868 { 1869 mutex_lock(&phydev->mdio.bus->mdio_lock); 1870 } 1871 1872 static inline void phy_unlock_mdio_bus(struct phy_device *phydev) 1873 { 1874 mutex_unlock(&phydev->mdio.bus->mdio_lock); 1875 } 1876 1877 void phy_attached_print(struct phy_device *phydev, const char *fmt, ...) 1878 __printf(2, 3); 1879 char *phy_attached_info_irq(struct phy_device *phydev) 1880 __malloc; 1881 void phy_attached_info(struct phy_device *phydev); 1882 1883 /* Clause 22 PHY */ 1884 int genphy_read_abilities(struct phy_device *phydev); 1885 int genphy_setup_forced(struct phy_device *phydev); 1886 int genphy_restart_aneg(struct phy_device *phydev); 1887 int genphy_check_and_restart_aneg(struct phy_device *phydev, bool restart); 1888 int genphy_config_eee_advert(struct phy_device *phydev); 1889 int __genphy_config_aneg(struct phy_device *phydev, bool changed); 1890 int genphy_aneg_done(struct phy_device *phydev); 1891 int genphy_update_link(struct phy_device *phydev); 1892 int genphy_read_lpa(struct phy_device *phydev); 1893 int genphy_read_status_fixed(struct phy_device *phydev); 1894 int genphy_read_status(struct phy_device *phydev); 1895 int genphy_read_master_slave(struct phy_device *phydev); 1896 int genphy_suspend(struct phy_device *phydev); 1897 int genphy_resume(struct phy_device *phydev); 1898 int genphy_loopback(struct phy_device *phydev, bool enable); 1899 int genphy_soft_reset(struct phy_device *phydev); 1900 irqreturn_t genphy_handle_interrupt_no_ack(struct phy_device *phydev); 1901 1902 static inline int genphy_config_aneg(struct phy_device *phydev) 1903 { 1904 return __genphy_config_aneg(phydev, false); 1905 } 1906 1907 static inline int genphy_no_config_intr(struct phy_device *phydev) 1908 { 1909 return 0; 1910 } 1911 int genphy_read_mmd_unsupported(struct phy_device *phdev, int devad, 1912 u16 regnum); 1913 int genphy_write_mmd_unsupported(struct phy_device *phdev, int devnum, 1914 u16 regnum, u16 val); 1915 1916 /* Clause 37 */ 1917 int genphy_c37_config_aneg(struct phy_device *phydev); 1918 int genphy_c37_read_status(struct phy_device *phydev, bool *changed); 1919 1920 /* Clause 45 PHY */ 1921 int genphy_c45_restart_aneg(struct phy_device *phydev); 1922 int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart); 1923 int genphy_c45_aneg_done(struct phy_device *phydev); 1924 int genphy_c45_read_link(struct phy_device *phydev); 1925 int genphy_c45_read_lpa(struct phy_device *phydev); 1926 int genphy_c45_read_pma(struct phy_device *phydev); 1927 int genphy_c45_pma_setup_forced(struct phy_device *phydev); 1928 int genphy_c45_pma_baset1_setup_master_slave(struct phy_device *phydev); 1929 int genphy_c45_an_config_aneg(struct phy_device *phydev); 1930 int genphy_c45_an_disable_aneg(struct phy_device *phydev); 1931 int genphy_c45_read_mdix(struct phy_device *phydev); 1932 int genphy_c45_pma_read_abilities(struct phy_device *phydev); 1933 int genphy_c45_pma_read_ext_abilities(struct phy_device *phydev); 1934 int genphy_c45_pma_baset1_read_abilities(struct phy_device *phydev); 1935 int genphy_c45_read_eee_abilities(struct phy_device *phydev); 1936 int genphy_c45_pma_baset1_read_master_slave(struct phy_device *phydev); 1937 int genphy_c45_read_status(struct phy_device *phydev); 1938 int genphy_c45_baset1_read_status(struct phy_device *phydev); 1939 int genphy_c45_config_aneg(struct phy_device *phydev); 1940 int genphy_c45_loopback(struct phy_device *phydev, bool enable); 1941 int genphy_c45_pma_resume(struct phy_device *phydev); 1942 int genphy_c45_pma_suspend(struct phy_device *phydev); 1943 int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable); 1944 int genphy_c45_plca_get_cfg(struct phy_device *phydev, 1945 struct phy_plca_cfg *plca_cfg); 1946 int genphy_c45_plca_set_cfg(struct phy_device *phydev, 1947 const struct phy_plca_cfg *plca_cfg); 1948 int genphy_c45_plca_get_status(struct phy_device *phydev, 1949 struct phy_plca_status *plca_st); 1950 int genphy_c45_eee_is_active(struct phy_device *phydev, unsigned long *adv, 1951 unsigned long *lp, bool *is_enabled); 1952 int genphy_c45_ethtool_get_eee(struct phy_device *phydev, 1953 struct ethtool_keee *data); 1954 int genphy_c45_ethtool_set_eee(struct phy_device *phydev, 1955 struct ethtool_keee *data); 1956 int genphy_c45_write_eee_adv(struct phy_device *phydev, unsigned long *adv); 1957 int genphy_c45_an_config_eee_aneg(struct phy_device *phydev); 1958 int genphy_c45_read_eee_adv(struct phy_device *phydev, unsigned long *adv); 1959 1960 /* Generic C45 PHY driver */ 1961 extern struct phy_driver genphy_c45_driver; 1962 1963 /* The gen10g_* functions are the old Clause 45 stub */ 1964 int gen10g_config_aneg(struct phy_device *phydev); 1965 1966 static inline int phy_read_status(struct phy_device *phydev) 1967 { 1968 if (!phydev->drv) 1969 return -EIO; 1970 1971 if (phydev->drv->read_status) 1972 return phydev->drv->read_status(phydev); 1973 else 1974 return genphy_read_status(phydev); 1975 } 1976 1977 void phy_driver_unregister(struct phy_driver *drv); 1978 void phy_drivers_unregister(struct phy_driver *drv, int n); 1979 int phy_driver_register(struct phy_driver *new_driver, struct module *owner); 1980 int phy_drivers_register(struct phy_driver *new_driver, int n, 1981 struct module *owner); 1982 void phy_error(struct phy_device *phydev); 1983 void phy_state_machine(struct work_struct *work); 1984 void phy_queue_state_machine(struct phy_device *phydev, unsigned long jiffies); 1985 void phy_trigger_machine(struct phy_device *phydev); 1986 void phy_mac_interrupt(struct phy_device *phydev); 1987 void phy_start_machine(struct phy_device *phydev); 1988 void phy_stop_machine(struct phy_device *phydev); 1989 void phy_ethtool_ksettings_get(struct phy_device *phydev, 1990 struct ethtool_link_ksettings *cmd); 1991 int phy_ethtool_ksettings_set(struct phy_device *phydev, 1992 const struct ethtool_link_ksettings *cmd); 1993 int phy_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd); 1994 int phy_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); 1995 int phy_do_ioctl_running(struct net_device *dev, struct ifreq *ifr, int cmd); 1996 int phy_disable_interrupts(struct phy_device *phydev); 1997 void phy_request_interrupt(struct phy_device *phydev); 1998 void phy_free_interrupt(struct phy_device *phydev); 1999 void phy_print_status(struct phy_device *phydev); 2000 int phy_get_rate_matching(struct phy_device *phydev, 2001 phy_interface_t iface); 2002 void phy_set_max_speed(struct phy_device *phydev, u32 max_speed); 2003 void phy_remove_link_mode(struct phy_device *phydev, u32 link_mode); 2004 void phy_advertise_supported(struct phy_device *phydev); 2005 void phy_advertise_eee_all(struct phy_device *phydev); 2006 void phy_support_sym_pause(struct phy_device *phydev); 2007 void phy_support_asym_pause(struct phy_device *phydev); 2008 void phy_support_eee(struct phy_device *phydev); 2009 void phy_set_sym_pause(struct phy_device *phydev, bool rx, bool tx, 2010 bool autoneg); 2011 void phy_set_asym_pause(struct phy_device *phydev, bool rx, bool tx); 2012 bool phy_validate_pause(struct phy_device *phydev, 2013 struct ethtool_pauseparam *pp); 2014 void phy_get_pause(struct phy_device *phydev, bool *tx_pause, bool *rx_pause); 2015 2016 s32 phy_get_internal_delay(struct phy_device *phydev, struct device *dev, 2017 const int *delay_values, int size, bool is_rx); 2018 2019 void phy_resolve_pause(unsigned long *local_adv, unsigned long *partner_adv, 2020 bool *tx_pause, bool *rx_pause); 2021 2022 int phy_register_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask, 2023 int (*run)(struct phy_device *)); 2024 int phy_register_fixup_for_id(const char *bus_id, 2025 int (*run)(struct phy_device *)); 2026 int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask, 2027 int (*run)(struct phy_device *)); 2028 2029 int phy_unregister_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask); 2030 int phy_unregister_fixup_for_id(const char *bus_id); 2031 int phy_unregister_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask); 2032 2033 int phy_init_eee(struct phy_device *phydev, bool clk_stop_enable); 2034 int phy_get_eee_err(struct phy_device *phydev); 2035 int phy_ethtool_set_eee(struct phy_device *phydev, struct ethtool_keee *data); 2036 int phy_ethtool_get_eee(struct phy_device *phydev, struct ethtool_keee *data); 2037 int phy_ethtool_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol); 2038 void phy_ethtool_get_wol(struct phy_device *phydev, 2039 struct ethtool_wolinfo *wol); 2040 int phy_ethtool_get_link_ksettings(struct net_device *ndev, 2041 struct ethtool_link_ksettings *cmd); 2042 int phy_ethtool_set_link_ksettings(struct net_device *ndev, 2043 const struct ethtool_link_ksettings *cmd); 2044 int phy_ethtool_nway_reset(struct net_device *ndev); 2045 int phy_package_join(struct phy_device *phydev, int base_addr, size_t priv_size); 2046 int of_phy_package_join(struct phy_device *phydev, size_t priv_size); 2047 void phy_package_leave(struct phy_device *phydev); 2048 int devm_phy_package_join(struct device *dev, struct phy_device *phydev, 2049 int base_addr, size_t priv_size); 2050 int devm_of_phy_package_join(struct device *dev, struct phy_device *phydev, 2051 size_t priv_size); 2052 2053 int __init mdio_bus_init(void); 2054 void mdio_bus_exit(void); 2055 2056 int phy_ethtool_get_strings(struct phy_device *phydev, u8 *data); 2057 int phy_ethtool_get_sset_count(struct phy_device *phydev); 2058 int phy_ethtool_get_stats(struct phy_device *phydev, 2059 struct ethtool_stats *stats, u64 *data); 2060 int phy_ethtool_get_plca_cfg(struct phy_device *phydev, 2061 struct phy_plca_cfg *plca_cfg); 2062 int phy_ethtool_set_plca_cfg(struct phy_device *phydev, 2063 const struct phy_plca_cfg *plca_cfg, 2064 struct netlink_ext_ack *extack); 2065 int phy_ethtool_get_plca_status(struct phy_device *phydev, 2066 struct phy_plca_status *plca_st); 2067 2068 int __phy_hwtstamp_get(struct phy_device *phydev, 2069 struct kernel_hwtstamp_config *config); 2070 int __phy_hwtstamp_set(struct phy_device *phydev, 2071 struct kernel_hwtstamp_config *config, 2072 struct netlink_ext_ack *extack); 2073 2074 static inline int phy_package_address(struct phy_device *phydev, 2075 unsigned int addr_offset) 2076 { 2077 struct phy_package_shared *shared = phydev->shared; 2078 u8 base_addr = shared->base_addr; 2079 2080 if (addr_offset >= PHY_MAX_ADDR - base_addr) 2081 return -EIO; 2082 2083 /* we know that addr will be in the range 0..31 and thus the 2084 * implicit cast to a signed int is not a problem. 2085 */ 2086 return base_addr + addr_offset; 2087 } 2088 2089 static inline int phy_package_read(struct phy_device *phydev, 2090 unsigned int addr_offset, u32 regnum) 2091 { 2092 int addr = phy_package_address(phydev, addr_offset); 2093 2094 if (addr < 0) 2095 return addr; 2096 2097 return mdiobus_read(phydev->mdio.bus, addr, regnum); 2098 } 2099 2100 static inline int __phy_package_read(struct phy_device *phydev, 2101 unsigned int addr_offset, u32 regnum) 2102 { 2103 int addr = phy_package_address(phydev, addr_offset); 2104 2105 if (addr < 0) 2106 return addr; 2107 2108 return __mdiobus_read(phydev->mdio.bus, addr, regnum); 2109 } 2110 2111 static inline int phy_package_write(struct phy_device *phydev, 2112 unsigned int addr_offset, u32 regnum, 2113 u16 val) 2114 { 2115 int addr = phy_package_address(phydev, addr_offset); 2116 2117 if (addr < 0) 2118 return addr; 2119 2120 return mdiobus_write(phydev->mdio.bus, addr, regnum, val); 2121 } 2122 2123 static inline int __phy_package_write(struct phy_device *phydev, 2124 unsigned int addr_offset, u32 regnum, 2125 u16 val) 2126 { 2127 int addr = phy_package_address(phydev, addr_offset); 2128 2129 if (addr < 0) 2130 return addr; 2131 2132 return __mdiobus_write(phydev->mdio.bus, addr, regnum, val); 2133 } 2134 2135 int __phy_package_read_mmd(struct phy_device *phydev, 2136 unsigned int addr_offset, int devad, 2137 u32 regnum); 2138 2139 int phy_package_read_mmd(struct phy_device *phydev, 2140 unsigned int addr_offset, int devad, 2141 u32 regnum); 2142 2143 int __phy_package_write_mmd(struct phy_device *phydev, 2144 unsigned int addr_offset, int devad, 2145 u32 regnum, u16 val); 2146 2147 int phy_package_write_mmd(struct phy_device *phydev, 2148 unsigned int addr_offset, int devad, 2149 u32 regnum, u16 val); 2150 2151 static inline bool __phy_package_set_once(struct phy_device *phydev, 2152 unsigned int b) 2153 { 2154 struct phy_package_shared *shared = phydev->shared; 2155 2156 if (!shared) 2157 return false; 2158 2159 return !test_and_set_bit(b, &shared->flags); 2160 } 2161 2162 static inline bool phy_package_init_once(struct phy_device *phydev) 2163 { 2164 return __phy_package_set_once(phydev, PHY_SHARED_F_INIT_DONE); 2165 } 2166 2167 static inline bool phy_package_probe_once(struct phy_device *phydev) 2168 { 2169 return __phy_package_set_once(phydev, PHY_SHARED_F_PROBE_DONE); 2170 } 2171 2172 extern const struct bus_type mdio_bus_type; 2173 2174 struct mdio_board_info { 2175 const char *bus_id; 2176 char modalias[MDIO_NAME_SIZE]; 2177 int mdio_addr; 2178 const void *platform_data; 2179 }; 2180 2181 #if IS_ENABLED(CONFIG_MDIO_DEVICE) 2182 int mdiobus_register_board_info(const struct mdio_board_info *info, 2183 unsigned int n); 2184 #else 2185 static inline int mdiobus_register_board_info(const struct mdio_board_info *i, 2186 unsigned int n) 2187 { 2188 return 0; 2189 } 2190 #endif 2191 2192 2193 /** 2194 * phy_module_driver() - Helper macro for registering PHY drivers 2195 * @__phy_drivers: array of PHY drivers to register 2196 * @__count: Numbers of members in array 2197 * 2198 * Helper macro for PHY drivers which do not do anything special in module 2199 * init/exit. Each module may only use this macro once, and calling it 2200 * replaces module_init() and module_exit(). 2201 */ 2202 #define phy_module_driver(__phy_drivers, __count) \ 2203 static int __init phy_module_init(void) \ 2204 { \ 2205 return phy_drivers_register(__phy_drivers, __count, THIS_MODULE); \ 2206 } \ 2207 module_init(phy_module_init); \ 2208 static void __exit phy_module_exit(void) \ 2209 { \ 2210 phy_drivers_unregister(__phy_drivers, __count); \ 2211 } \ 2212 module_exit(phy_module_exit) 2213 2214 #define module_phy_driver(__phy_drivers) \ 2215 phy_module_driver(__phy_drivers, ARRAY_SIZE(__phy_drivers)) 2216 2217 bool phy_driver_is_genphy(struct phy_device *phydev); 2218 bool phy_driver_is_genphy_10g(struct phy_device *phydev); 2219 2220 #endif /* __PHY_H */ 2221