1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _LINUX_PGTABLE_H 3 #define _LINUX_PGTABLE_H 4 5 #include <linux/pfn.h> 6 #include <asm/pgtable.h> 7 8 #define PMD_ORDER (PMD_SHIFT - PAGE_SHIFT) 9 #define PUD_ORDER (PUD_SHIFT - PAGE_SHIFT) 10 11 #ifndef __ASSEMBLY__ 12 #ifdef CONFIG_MMU 13 14 #include <linux/mm_types.h> 15 #include <linux/bug.h> 16 #include <linux/errno.h> 17 #include <asm-generic/pgtable_uffd.h> 18 #include <linux/page_table_check.h> 19 20 #if 5 - defined(__PAGETABLE_P4D_FOLDED) - defined(__PAGETABLE_PUD_FOLDED) - \ 21 defined(__PAGETABLE_PMD_FOLDED) != CONFIG_PGTABLE_LEVELS 22 #error CONFIG_PGTABLE_LEVELS is not consistent with __PAGETABLE_{P4D,PUD,PMD}_FOLDED 23 #endif 24 25 /* 26 * On almost all architectures and configurations, 0 can be used as the 27 * upper ceiling to free_pgtables(): on many architectures it has the same 28 * effect as using TASK_SIZE. However, there is one configuration which 29 * must impose a more careful limit, to avoid freeing kernel pgtables. 30 */ 31 #ifndef USER_PGTABLES_CEILING 32 #define USER_PGTABLES_CEILING 0UL 33 #endif 34 35 /* 36 * This defines the first usable user address. Platforms 37 * can override its value with custom FIRST_USER_ADDRESS 38 * defined in their respective <asm/pgtable.h>. 39 */ 40 #ifndef FIRST_USER_ADDRESS 41 #define FIRST_USER_ADDRESS 0UL 42 #endif 43 44 /* 45 * This defines the generic helper for accessing PMD page 46 * table page. Although platforms can still override this 47 * via their respective <asm/pgtable.h>. 48 */ 49 #ifndef pmd_pgtable 50 #define pmd_pgtable(pmd) pmd_page(pmd) 51 #endif 52 53 /* 54 * A page table page can be thought of an array like this: pXd_t[PTRS_PER_PxD] 55 * 56 * The pXx_index() functions return the index of the entry in the page 57 * table page which would control the given virtual address 58 * 59 * As these functions may be used by the same code for different levels of 60 * the page table folding, they are always available, regardless of 61 * CONFIG_PGTABLE_LEVELS value. For the folded levels they simply return 0 62 * because in such cases PTRS_PER_PxD equals 1. 63 */ 64 65 static inline unsigned long pte_index(unsigned long address) 66 { 67 return (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1); 68 } 69 70 #ifndef pmd_index 71 static inline unsigned long pmd_index(unsigned long address) 72 { 73 return (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1); 74 } 75 #define pmd_index pmd_index 76 #endif 77 78 #ifndef pud_index 79 static inline unsigned long pud_index(unsigned long address) 80 { 81 return (address >> PUD_SHIFT) & (PTRS_PER_PUD - 1); 82 } 83 #define pud_index pud_index 84 #endif 85 86 #ifndef pgd_index 87 /* Must be a compile-time constant, so implement it as a macro */ 88 #define pgd_index(a) (((a) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 89 #endif 90 91 #ifndef pte_offset_kernel 92 static inline pte_t *pte_offset_kernel(pmd_t *pmd, unsigned long address) 93 { 94 return (pte_t *)pmd_page_vaddr(*pmd) + pte_index(address); 95 } 96 #define pte_offset_kernel pte_offset_kernel 97 #endif 98 99 #ifdef CONFIG_HIGHPTE 100 #define __pte_map(pmd, address) \ 101 ((pte_t *)kmap_local_page(pmd_page(*(pmd))) + pte_index((address))) 102 #define pte_unmap(pte) do { \ 103 kunmap_local((pte)); \ 104 rcu_read_unlock(); \ 105 } while (0) 106 #else 107 static inline pte_t *__pte_map(pmd_t *pmd, unsigned long address) 108 { 109 return pte_offset_kernel(pmd, address); 110 } 111 static inline void pte_unmap(pte_t *pte) 112 { 113 rcu_read_unlock(); 114 } 115 #endif 116 117 void pte_free_defer(struct mm_struct *mm, pgtable_t pgtable); 118 119 /* Find an entry in the second-level page table.. */ 120 #ifndef pmd_offset 121 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) 122 { 123 return pud_pgtable(*pud) + pmd_index(address); 124 } 125 #define pmd_offset pmd_offset 126 #endif 127 128 #ifndef pud_offset 129 static inline pud_t *pud_offset(p4d_t *p4d, unsigned long address) 130 { 131 return p4d_pgtable(*p4d) + pud_index(address); 132 } 133 #define pud_offset pud_offset 134 #endif 135 136 static inline pgd_t *pgd_offset_pgd(pgd_t *pgd, unsigned long address) 137 { 138 return (pgd + pgd_index(address)); 139 }; 140 141 /* 142 * a shortcut to get a pgd_t in a given mm 143 */ 144 #ifndef pgd_offset 145 #define pgd_offset(mm, address) pgd_offset_pgd((mm)->pgd, (address)) 146 #endif 147 148 /* 149 * a shortcut which implies the use of the kernel's pgd, instead 150 * of a process's 151 */ 152 #ifndef pgd_offset_k 153 #define pgd_offset_k(address) pgd_offset(&init_mm, (address)) 154 #endif 155 156 /* 157 * In many cases it is known that a virtual address is mapped at PMD or PTE 158 * level, so instead of traversing all the page table levels, we can get a 159 * pointer to the PMD entry in user or kernel page table or translate a virtual 160 * address to the pointer in the PTE in the kernel page tables with simple 161 * helpers. 162 */ 163 static inline pmd_t *pmd_off(struct mm_struct *mm, unsigned long va) 164 { 165 return pmd_offset(pud_offset(p4d_offset(pgd_offset(mm, va), va), va), va); 166 } 167 168 static inline pmd_t *pmd_off_k(unsigned long va) 169 { 170 return pmd_offset(pud_offset(p4d_offset(pgd_offset_k(va), va), va), va); 171 } 172 173 static inline pte_t *virt_to_kpte(unsigned long vaddr) 174 { 175 pmd_t *pmd = pmd_off_k(vaddr); 176 177 return pmd_none(*pmd) ? NULL : pte_offset_kernel(pmd, vaddr); 178 } 179 180 #ifndef pmd_young 181 static inline int pmd_young(pmd_t pmd) 182 { 183 return 0; 184 } 185 #endif 186 187 #ifndef pmd_dirty 188 static inline int pmd_dirty(pmd_t pmd) 189 { 190 return 0; 191 } 192 #endif 193 194 /* 195 * A facility to provide lazy MMU batching. This allows PTE updates and 196 * page invalidations to be delayed until a call to leave lazy MMU mode 197 * is issued. Some architectures may benefit from doing this, and it is 198 * beneficial for both shadow and direct mode hypervisors, which may batch 199 * the PTE updates which happen during this window. Note that using this 200 * interface requires that read hazards be removed from the code. A read 201 * hazard could result in the direct mode hypervisor case, since the actual 202 * write to the page tables may not yet have taken place, so reads though 203 * a raw PTE pointer after it has been modified are not guaranteed to be 204 * up to date. This mode can only be entered and left under the protection of 205 * the page table locks for all page tables which may be modified. In the UP 206 * case, this is required so that preemption is disabled, and in the SMP case, 207 * it must synchronize the delayed page table writes properly on other CPUs. 208 */ 209 #ifndef __HAVE_ARCH_ENTER_LAZY_MMU_MODE 210 #define arch_enter_lazy_mmu_mode() do {} while (0) 211 #define arch_leave_lazy_mmu_mode() do {} while (0) 212 #define arch_flush_lazy_mmu_mode() do {} while (0) 213 #endif 214 215 #ifndef pte_advance_pfn 216 static inline pte_t pte_advance_pfn(pte_t pte, unsigned long nr) 217 { 218 return __pte(pte_val(pte) + (nr << PFN_PTE_SHIFT)); 219 } 220 #endif 221 222 #define pte_next_pfn(pte) pte_advance_pfn(pte, 1) 223 224 #ifndef set_ptes 225 /** 226 * set_ptes - Map consecutive pages to a contiguous range of addresses. 227 * @mm: Address space to map the pages into. 228 * @addr: Address to map the first page at. 229 * @ptep: Page table pointer for the first entry. 230 * @pte: Page table entry for the first page. 231 * @nr: Number of pages to map. 232 * 233 * When nr==1, initial state of pte may be present or not present, and new state 234 * may be present or not present. When nr>1, initial state of all ptes must be 235 * not present, and new state must be present. 236 * 237 * May be overridden by the architecture, or the architecture can define 238 * set_pte() and PFN_PTE_SHIFT. 239 * 240 * Context: The caller holds the page table lock. The pages all belong 241 * to the same folio. The PTEs are all in the same PMD. 242 */ 243 static inline void set_ptes(struct mm_struct *mm, unsigned long addr, 244 pte_t *ptep, pte_t pte, unsigned int nr) 245 { 246 page_table_check_ptes_set(mm, ptep, pte, nr); 247 248 arch_enter_lazy_mmu_mode(); 249 for (;;) { 250 set_pte(ptep, pte); 251 if (--nr == 0) 252 break; 253 ptep++; 254 pte = pte_next_pfn(pte); 255 } 256 arch_leave_lazy_mmu_mode(); 257 } 258 #endif 259 #define set_pte_at(mm, addr, ptep, pte) set_ptes(mm, addr, ptep, pte, 1) 260 261 #ifndef __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 262 extern int ptep_set_access_flags(struct vm_area_struct *vma, 263 unsigned long address, pte_t *ptep, 264 pte_t entry, int dirty); 265 #endif 266 267 #ifndef __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 268 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 269 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 270 unsigned long address, pmd_t *pmdp, 271 pmd_t entry, int dirty); 272 extern int pudp_set_access_flags(struct vm_area_struct *vma, 273 unsigned long address, pud_t *pudp, 274 pud_t entry, int dirty); 275 #else 276 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 277 unsigned long address, pmd_t *pmdp, 278 pmd_t entry, int dirty) 279 { 280 BUILD_BUG(); 281 return 0; 282 } 283 static inline int pudp_set_access_flags(struct vm_area_struct *vma, 284 unsigned long address, pud_t *pudp, 285 pud_t entry, int dirty) 286 { 287 BUILD_BUG(); 288 return 0; 289 } 290 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 291 #endif 292 293 #ifndef ptep_get 294 static inline pte_t ptep_get(pte_t *ptep) 295 { 296 return READ_ONCE(*ptep); 297 } 298 #endif 299 300 #ifndef pmdp_get 301 static inline pmd_t pmdp_get(pmd_t *pmdp) 302 { 303 return READ_ONCE(*pmdp); 304 } 305 #endif 306 307 #ifndef pudp_get 308 static inline pud_t pudp_get(pud_t *pudp) 309 { 310 return READ_ONCE(*pudp); 311 } 312 #endif 313 314 #ifndef p4dp_get 315 static inline p4d_t p4dp_get(p4d_t *p4dp) 316 { 317 return READ_ONCE(*p4dp); 318 } 319 #endif 320 321 #ifndef pgdp_get 322 static inline pgd_t pgdp_get(pgd_t *pgdp) 323 { 324 return READ_ONCE(*pgdp); 325 } 326 #endif 327 328 #ifndef __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 329 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 330 unsigned long address, 331 pte_t *ptep) 332 { 333 pte_t pte = ptep_get(ptep); 334 int r = 1; 335 if (!pte_young(pte)) 336 r = 0; 337 else 338 set_pte_at(vma->vm_mm, address, ptep, pte_mkold(pte)); 339 return r; 340 } 341 #endif 342 343 #ifndef __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 344 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG) 345 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 346 unsigned long address, 347 pmd_t *pmdp) 348 { 349 pmd_t pmd = *pmdp; 350 int r = 1; 351 if (!pmd_young(pmd)) 352 r = 0; 353 else 354 set_pmd_at(vma->vm_mm, address, pmdp, pmd_mkold(pmd)); 355 return r; 356 } 357 #else 358 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 359 unsigned long address, 360 pmd_t *pmdp) 361 { 362 BUILD_BUG(); 363 return 0; 364 } 365 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG */ 366 #endif 367 368 #ifndef __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 369 int ptep_clear_flush_young(struct vm_area_struct *vma, 370 unsigned long address, pte_t *ptep); 371 #endif 372 373 #ifndef __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 374 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 375 extern int pmdp_clear_flush_young(struct vm_area_struct *vma, 376 unsigned long address, pmd_t *pmdp); 377 #else 378 /* 379 * Despite relevant to THP only, this API is called from generic rmap code 380 * under PageTransHuge(), hence needs a dummy implementation for !THP 381 */ 382 static inline int pmdp_clear_flush_young(struct vm_area_struct *vma, 383 unsigned long address, pmd_t *pmdp) 384 { 385 BUILD_BUG(); 386 return 0; 387 } 388 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 389 #endif 390 391 #ifndef arch_has_hw_nonleaf_pmd_young 392 /* 393 * Return whether the accessed bit in non-leaf PMD entries is supported on the 394 * local CPU. 395 */ 396 static inline bool arch_has_hw_nonleaf_pmd_young(void) 397 { 398 return IS_ENABLED(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG); 399 } 400 #endif 401 402 #ifndef arch_has_hw_pte_young 403 /* 404 * Return whether the accessed bit is supported on the local CPU. 405 * 406 * This stub assumes accessing through an old PTE triggers a page fault. 407 * Architectures that automatically set the access bit should overwrite it. 408 */ 409 static inline bool arch_has_hw_pte_young(void) 410 { 411 return IS_ENABLED(CONFIG_ARCH_HAS_HW_PTE_YOUNG); 412 } 413 #endif 414 415 #ifndef arch_check_zapped_pte 416 static inline void arch_check_zapped_pte(struct vm_area_struct *vma, 417 pte_t pte) 418 { 419 } 420 #endif 421 422 #ifndef arch_check_zapped_pmd 423 static inline void arch_check_zapped_pmd(struct vm_area_struct *vma, 424 pmd_t pmd) 425 { 426 } 427 #endif 428 429 #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR 430 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 431 unsigned long address, 432 pte_t *ptep) 433 { 434 pte_t pte = ptep_get(ptep); 435 pte_clear(mm, address, ptep); 436 page_table_check_pte_clear(mm, pte); 437 return pte; 438 } 439 #endif 440 441 static inline void ptep_clear(struct mm_struct *mm, unsigned long addr, 442 pte_t *ptep) 443 { 444 ptep_get_and_clear(mm, addr, ptep); 445 } 446 447 #ifdef CONFIG_GUP_GET_PXX_LOW_HIGH 448 /* 449 * For walking the pagetables without holding any locks. Some architectures 450 * (eg x86-32 PAE) cannot load the entries atomically without using expensive 451 * instructions. We are guaranteed that a PTE will only either go from not 452 * present to present, or present to not present -- it will not switch to a 453 * completely different present page without a TLB flush inbetween; which we 454 * are blocking by holding interrupts off. 455 * 456 * Setting ptes from not present to present goes: 457 * 458 * ptep->pte_high = h; 459 * smp_wmb(); 460 * ptep->pte_low = l; 461 * 462 * And present to not present goes: 463 * 464 * ptep->pte_low = 0; 465 * smp_wmb(); 466 * ptep->pte_high = 0; 467 * 468 * We must ensure here that the load of pte_low sees 'l' IFF pte_high sees 'h'. 469 * We load pte_high *after* loading pte_low, which ensures we don't see an older 470 * value of pte_high. *Then* we recheck pte_low, which ensures that we haven't 471 * picked up a changed pte high. We might have gotten rubbish values from 472 * pte_low and pte_high, but we are guaranteed that pte_low will not have the 473 * present bit set *unless* it is 'l'. Because get_user_pages_fast() only 474 * operates on present ptes we're safe. 475 */ 476 static inline pte_t ptep_get_lockless(pte_t *ptep) 477 { 478 pte_t pte; 479 480 do { 481 pte.pte_low = ptep->pte_low; 482 smp_rmb(); 483 pte.pte_high = ptep->pte_high; 484 smp_rmb(); 485 } while (unlikely(pte.pte_low != ptep->pte_low)); 486 487 return pte; 488 } 489 #define ptep_get_lockless ptep_get_lockless 490 491 #if CONFIG_PGTABLE_LEVELS > 2 492 static inline pmd_t pmdp_get_lockless(pmd_t *pmdp) 493 { 494 pmd_t pmd; 495 496 do { 497 pmd.pmd_low = pmdp->pmd_low; 498 smp_rmb(); 499 pmd.pmd_high = pmdp->pmd_high; 500 smp_rmb(); 501 } while (unlikely(pmd.pmd_low != pmdp->pmd_low)); 502 503 return pmd; 504 } 505 #define pmdp_get_lockless pmdp_get_lockless 506 #define pmdp_get_lockless_sync() tlb_remove_table_sync_one() 507 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 508 #endif /* CONFIG_GUP_GET_PXX_LOW_HIGH */ 509 510 /* 511 * We require that the PTE can be read atomically. 512 */ 513 #ifndef ptep_get_lockless 514 static inline pte_t ptep_get_lockless(pte_t *ptep) 515 { 516 return ptep_get(ptep); 517 } 518 #endif 519 520 #ifndef pmdp_get_lockless 521 static inline pmd_t pmdp_get_lockless(pmd_t *pmdp) 522 { 523 return pmdp_get(pmdp); 524 } 525 static inline void pmdp_get_lockless_sync(void) 526 { 527 } 528 #endif 529 530 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 531 #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 532 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 533 unsigned long address, 534 pmd_t *pmdp) 535 { 536 pmd_t pmd = *pmdp; 537 538 pmd_clear(pmdp); 539 page_table_check_pmd_clear(mm, pmd); 540 541 return pmd; 542 } 543 #endif /* __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR */ 544 #ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR 545 static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm, 546 unsigned long address, 547 pud_t *pudp) 548 { 549 pud_t pud = *pudp; 550 551 pud_clear(pudp); 552 page_table_check_pud_clear(mm, pud); 553 554 return pud; 555 } 556 #endif /* __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR */ 557 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 558 559 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 560 #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 561 static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 562 unsigned long address, pmd_t *pmdp, 563 int full) 564 { 565 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); 566 } 567 #endif 568 569 #ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR_FULL 570 static inline pud_t pudp_huge_get_and_clear_full(struct vm_area_struct *vma, 571 unsigned long address, pud_t *pudp, 572 int full) 573 { 574 return pudp_huge_get_and_clear(vma->vm_mm, address, pudp); 575 } 576 #endif 577 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 578 579 #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 580 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 581 unsigned long address, pte_t *ptep, 582 int full) 583 { 584 return ptep_get_and_clear(mm, address, ptep); 585 } 586 #endif 587 588 #ifndef get_and_clear_full_ptes 589 /** 590 * get_and_clear_full_ptes - Clear present PTEs that map consecutive pages of 591 * the same folio, collecting dirty/accessed bits. 592 * @mm: Address space the pages are mapped into. 593 * @addr: Address the first page is mapped at. 594 * @ptep: Page table pointer for the first entry. 595 * @nr: Number of entries to clear. 596 * @full: Whether we are clearing a full mm. 597 * 598 * May be overridden by the architecture; otherwise, implemented as a simple 599 * loop over ptep_get_and_clear_full(), merging dirty/accessed bits into the 600 * returned PTE. 601 * 602 * Note that PTE bits in the PTE range besides the PFN can differ. For example, 603 * some PTEs might be write-protected. 604 * 605 * Context: The caller holds the page table lock. The PTEs map consecutive 606 * pages that belong to the same folio. The PTEs are all in the same PMD. 607 */ 608 static inline pte_t get_and_clear_full_ptes(struct mm_struct *mm, 609 unsigned long addr, pte_t *ptep, unsigned int nr, int full) 610 { 611 pte_t pte, tmp_pte; 612 613 pte = ptep_get_and_clear_full(mm, addr, ptep, full); 614 while (--nr) { 615 ptep++; 616 addr += PAGE_SIZE; 617 tmp_pte = ptep_get_and_clear_full(mm, addr, ptep, full); 618 if (pte_dirty(tmp_pte)) 619 pte = pte_mkdirty(pte); 620 if (pte_young(tmp_pte)) 621 pte = pte_mkyoung(pte); 622 } 623 return pte; 624 } 625 #endif 626 627 #ifndef clear_full_ptes 628 /** 629 * clear_full_ptes - Clear present PTEs that map consecutive pages of the same 630 * folio. 631 * @mm: Address space the pages are mapped into. 632 * @addr: Address the first page is mapped at. 633 * @ptep: Page table pointer for the first entry. 634 * @nr: Number of entries to clear. 635 * @full: Whether we are clearing a full mm. 636 * 637 * May be overridden by the architecture; otherwise, implemented as a simple 638 * loop over ptep_get_and_clear_full(). 639 * 640 * Note that PTE bits in the PTE range besides the PFN can differ. For example, 641 * some PTEs might be write-protected. 642 * 643 * Context: The caller holds the page table lock. The PTEs map consecutive 644 * pages that belong to the same folio. The PTEs are all in the same PMD. 645 */ 646 static inline void clear_full_ptes(struct mm_struct *mm, unsigned long addr, 647 pte_t *ptep, unsigned int nr, int full) 648 { 649 for (;;) { 650 ptep_get_and_clear_full(mm, addr, ptep, full); 651 if (--nr == 0) 652 break; 653 ptep++; 654 addr += PAGE_SIZE; 655 } 656 } 657 #endif 658 659 /* 660 * If two threads concurrently fault at the same page, the thread that 661 * won the race updates the PTE and its local TLB/Cache. The other thread 662 * gives up, simply does nothing, and continues; on architectures where 663 * software can update TLB, local TLB can be updated here to avoid next page 664 * fault. This function updates TLB only, do nothing with cache or others. 665 * It is the difference with function update_mmu_cache. 666 */ 667 #ifndef __HAVE_ARCH_UPDATE_MMU_TLB 668 static inline void update_mmu_tlb(struct vm_area_struct *vma, 669 unsigned long address, pte_t *ptep) 670 { 671 } 672 #define __HAVE_ARCH_UPDATE_MMU_TLB 673 #endif 674 675 /* 676 * Some architectures may be able to avoid expensive synchronization 677 * primitives when modifications are made to PTE's which are already 678 * not present, or in the process of an address space destruction. 679 */ 680 #ifndef __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL 681 static inline void pte_clear_not_present_full(struct mm_struct *mm, 682 unsigned long address, 683 pte_t *ptep, 684 int full) 685 { 686 pte_clear(mm, address, ptep); 687 } 688 #endif 689 690 #ifndef __HAVE_ARCH_PTEP_CLEAR_FLUSH 691 extern pte_t ptep_clear_flush(struct vm_area_struct *vma, 692 unsigned long address, 693 pte_t *ptep); 694 #endif 695 696 #ifndef __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH 697 extern pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, 698 unsigned long address, 699 pmd_t *pmdp); 700 extern pud_t pudp_huge_clear_flush(struct vm_area_struct *vma, 701 unsigned long address, 702 pud_t *pudp); 703 #endif 704 705 #ifndef pte_mkwrite 706 static inline pte_t pte_mkwrite(pte_t pte, struct vm_area_struct *vma) 707 { 708 return pte_mkwrite_novma(pte); 709 } 710 #endif 711 712 #if defined(CONFIG_ARCH_WANT_PMD_MKWRITE) && !defined(pmd_mkwrite) 713 static inline pmd_t pmd_mkwrite(pmd_t pmd, struct vm_area_struct *vma) 714 { 715 return pmd_mkwrite_novma(pmd); 716 } 717 #endif 718 719 #ifndef __HAVE_ARCH_PTEP_SET_WRPROTECT 720 struct mm_struct; 721 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 722 { 723 pte_t old_pte = ptep_get(ptep); 724 set_pte_at(mm, address, ptep, pte_wrprotect(old_pte)); 725 } 726 #endif 727 728 #ifndef wrprotect_ptes 729 /** 730 * wrprotect_ptes - Write-protect PTEs that map consecutive pages of the same 731 * folio. 732 * @mm: Address space the pages are mapped into. 733 * @addr: Address the first page is mapped at. 734 * @ptep: Page table pointer for the first entry. 735 * @nr: Number of entries to write-protect. 736 * 737 * May be overridden by the architecture; otherwise, implemented as a simple 738 * loop over ptep_set_wrprotect(). 739 * 740 * Note that PTE bits in the PTE range besides the PFN can differ. For example, 741 * some PTEs might be write-protected. 742 * 743 * Context: The caller holds the page table lock. The PTEs map consecutive 744 * pages that belong to the same folio. The PTEs are all in the same PMD. 745 */ 746 static inline void wrprotect_ptes(struct mm_struct *mm, unsigned long addr, 747 pte_t *ptep, unsigned int nr) 748 { 749 for (;;) { 750 ptep_set_wrprotect(mm, addr, ptep); 751 if (--nr == 0) 752 break; 753 ptep++; 754 addr += PAGE_SIZE; 755 } 756 } 757 #endif 758 759 /* 760 * On some architectures hardware does not set page access bit when accessing 761 * memory page, it is responsibility of software setting this bit. It brings 762 * out extra page fault penalty to track page access bit. For optimization page 763 * access bit can be set during all page fault flow on these arches. 764 * To be differentiate with macro pte_mkyoung, this macro is used on platforms 765 * where software maintains page access bit. 766 */ 767 #ifndef pte_sw_mkyoung 768 static inline pte_t pte_sw_mkyoung(pte_t pte) 769 { 770 return pte; 771 } 772 #define pte_sw_mkyoung pte_sw_mkyoung 773 #endif 774 775 #ifndef __HAVE_ARCH_PMDP_SET_WRPROTECT 776 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 777 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 778 unsigned long address, pmd_t *pmdp) 779 { 780 pmd_t old_pmd = *pmdp; 781 set_pmd_at(mm, address, pmdp, pmd_wrprotect(old_pmd)); 782 } 783 #else 784 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 785 unsigned long address, pmd_t *pmdp) 786 { 787 BUILD_BUG(); 788 } 789 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 790 #endif 791 #ifndef __HAVE_ARCH_PUDP_SET_WRPROTECT 792 #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD 793 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 794 static inline void pudp_set_wrprotect(struct mm_struct *mm, 795 unsigned long address, pud_t *pudp) 796 { 797 pud_t old_pud = *pudp; 798 799 set_pud_at(mm, address, pudp, pud_wrprotect(old_pud)); 800 } 801 #else 802 static inline void pudp_set_wrprotect(struct mm_struct *mm, 803 unsigned long address, pud_t *pudp) 804 { 805 BUILD_BUG(); 806 } 807 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 808 #endif /* CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD */ 809 #endif 810 811 #ifndef pmdp_collapse_flush 812 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 813 extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 814 unsigned long address, pmd_t *pmdp); 815 #else 816 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 817 unsigned long address, 818 pmd_t *pmdp) 819 { 820 BUILD_BUG(); 821 return *pmdp; 822 } 823 #define pmdp_collapse_flush pmdp_collapse_flush 824 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 825 #endif 826 827 #ifndef __HAVE_ARCH_PGTABLE_DEPOSIT 828 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 829 pgtable_t pgtable); 830 #endif 831 832 #ifndef __HAVE_ARCH_PGTABLE_WITHDRAW 833 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 834 #endif 835 836 #ifndef arch_needs_pgtable_deposit 837 #define arch_needs_pgtable_deposit() (false) 838 #endif 839 840 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 841 /* 842 * This is an implementation of pmdp_establish() that is only suitable for an 843 * architecture that doesn't have hardware dirty/accessed bits. In this case we 844 * can't race with CPU which sets these bits and non-atomic approach is fine. 845 */ 846 static inline pmd_t generic_pmdp_establish(struct vm_area_struct *vma, 847 unsigned long address, pmd_t *pmdp, pmd_t pmd) 848 { 849 pmd_t old_pmd = *pmdp; 850 set_pmd_at(vma->vm_mm, address, pmdp, pmd); 851 return old_pmd; 852 } 853 #endif 854 855 #ifndef __HAVE_ARCH_PMDP_INVALIDATE 856 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 857 pmd_t *pmdp); 858 #endif 859 860 #ifndef __HAVE_ARCH_PMDP_INVALIDATE_AD 861 862 /* 863 * pmdp_invalidate_ad() invalidates the PMD while changing a transparent 864 * hugepage mapping in the page tables. This function is similar to 865 * pmdp_invalidate(), but should only be used if the access and dirty bits would 866 * not be cleared by the software in the new PMD value. The function ensures 867 * that hardware changes of the access and dirty bits updates would not be lost. 868 * 869 * Doing so can allow in certain architectures to avoid a TLB flush in most 870 * cases. Yet, another TLB flush might be necessary later if the PMD update 871 * itself requires such flush (e.g., if protection was set to be stricter). Yet, 872 * even when a TLB flush is needed because of the update, the caller may be able 873 * to batch these TLB flushing operations, so fewer TLB flush operations are 874 * needed. 875 */ 876 extern pmd_t pmdp_invalidate_ad(struct vm_area_struct *vma, 877 unsigned long address, pmd_t *pmdp); 878 #endif 879 880 #ifndef __HAVE_ARCH_PTE_SAME 881 static inline int pte_same(pte_t pte_a, pte_t pte_b) 882 { 883 return pte_val(pte_a) == pte_val(pte_b); 884 } 885 #endif 886 887 #ifndef __HAVE_ARCH_PTE_UNUSED 888 /* 889 * Some architectures provide facilities to virtualization guests 890 * so that they can flag allocated pages as unused. This allows the 891 * host to transparently reclaim unused pages. This function returns 892 * whether the pte's page is unused. 893 */ 894 static inline int pte_unused(pte_t pte) 895 { 896 return 0; 897 } 898 #endif 899 900 #ifndef pte_access_permitted 901 #define pte_access_permitted(pte, write) \ 902 (pte_present(pte) && (!(write) || pte_write(pte))) 903 #endif 904 905 #ifndef pmd_access_permitted 906 #define pmd_access_permitted(pmd, write) \ 907 (pmd_present(pmd) && (!(write) || pmd_write(pmd))) 908 #endif 909 910 #ifndef pud_access_permitted 911 #define pud_access_permitted(pud, write) \ 912 (pud_present(pud) && (!(write) || pud_write(pud))) 913 #endif 914 915 #ifndef p4d_access_permitted 916 #define p4d_access_permitted(p4d, write) \ 917 (p4d_present(p4d) && (!(write) || p4d_write(p4d))) 918 #endif 919 920 #ifndef pgd_access_permitted 921 #define pgd_access_permitted(pgd, write) \ 922 (pgd_present(pgd) && (!(write) || pgd_write(pgd))) 923 #endif 924 925 #ifndef __HAVE_ARCH_PMD_SAME 926 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 927 { 928 return pmd_val(pmd_a) == pmd_val(pmd_b); 929 } 930 #endif 931 932 #ifndef pud_same 933 static inline int pud_same(pud_t pud_a, pud_t pud_b) 934 { 935 return pud_val(pud_a) == pud_val(pud_b); 936 } 937 #define pud_same pud_same 938 #endif 939 940 #ifndef __HAVE_ARCH_P4D_SAME 941 static inline int p4d_same(p4d_t p4d_a, p4d_t p4d_b) 942 { 943 return p4d_val(p4d_a) == p4d_val(p4d_b); 944 } 945 #endif 946 947 #ifndef __HAVE_ARCH_PGD_SAME 948 static inline int pgd_same(pgd_t pgd_a, pgd_t pgd_b) 949 { 950 return pgd_val(pgd_a) == pgd_val(pgd_b); 951 } 952 #endif 953 954 /* 955 * Use set_p*_safe(), and elide TLB flushing, when confident that *no* 956 * TLB flush will be required as a result of the "set". For example, use 957 * in scenarios where it is known ahead of time that the routine is 958 * setting non-present entries, or re-setting an existing entry to the 959 * same value. Otherwise, use the typical "set" helpers and flush the 960 * TLB. 961 */ 962 #define set_pte_safe(ptep, pte) \ 963 ({ \ 964 WARN_ON_ONCE(pte_present(*ptep) && !pte_same(*ptep, pte)); \ 965 set_pte(ptep, pte); \ 966 }) 967 968 #define set_pmd_safe(pmdp, pmd) \ 969 ({ \ 970 WARN_ON_ONCE(pmd_present(*pmdp) && !pmd_same(*pmdp, pmd)); \ 971 set_pmd(pmdp, pmd); \ 972 }) 973 974 #define set_pud_safe(pudp, pud) \ 975 ({ \ 976 WARN_ON_ONCE(pud_present(*pudp) && !pud_same(*pudp, pud)); \ 977 set_pud(pudp, pud); \ 978 }) 979 980 #define set_p4d_safe(p4dp, p4d) \ 981 ({ \ 982 WARN_ON_ONCE(p4d_present(*p4dp) && !p4d_same(*p4dp, p4d)); \ 983 set_p4d(p4dp, p4d); \ 984 }) 985 986 #define set_pgd_safe(pgdp, pgd) \ 987 ({ \ 988 WARN_ON_ONCE(pgd_present(*pgdp) && !pgd_same(*pgdp, pgd)); \ 989 set_pgd(pgdp, pgd); \ 990 }) 991 992 #ifndef __HAVE_ARCH_DO_SWAP_PAGE 993 /* 994 * Some architectures support metadata associated with a page. When a 995 * page is being swapped out, this metadata must be saved so it can be 996 * restored when the page is swapped back in. SPARC M7 and newer 997 * processors support an ADI (Application Data Integrity) tag for the 998 * page as metadata for the page. arch_do_swap_page() can restore this 999 * metadata when a page is swapped back in. 1000 */ 1001 static inline void arch_do_swap_page(struct mm_struct *mm, 1002 struct vm_area_struct *vma, 1003 unsigned long addr, 1004 pte_t pte, pte_t oldpte) 1005 { 1006 1007 } 1008 #endif 1009 1010 #ifndef __HAVE_ARCH_UNMAP_ONE 1011 /* 1012 * Some architectures support metadata associated with a page. When a 1013 * page is being swapped out, this metadata must be saved so it can be 1014 * restored when the page is swapped back in. SPARC M7 and newer 1015 * processors support an ADI (Application Data Integrity) tag for the 1016 * page as metadata for the page. arch_unmap_one() can save this 1017 * metadata on a swap-out of a page. 1018 */ 1019 static inline int arch_unmap_one(struct mm_struct *mm, 1020 struct vm_area_struct *vma, 1021 unsigned long addr, 1022 pte_t orig_pte) 1023 { 1024 return 0; 1025 } 1026 #endif 1027 1028 /* 1029 * Allow architectures to preserve additional metadata associated with 1030 * swapped-out pages. The corresponding __HAVE_ARCH_SWAP_* macros and function 1031 * prototypes must be defined in the arch-specific asm/pgtable.h file. 1032 */ 1033 #ifndef __HAVE_ARCH_PREPARE_TO_SWAP 1034 static inline int arch_prepare_to_swap(struct page *page) 1035 { 1036 return 0; 1037 } 1038 #endif 1039 1040 #ifndef __HAVE_ARCH_SWAP_INVALIDATE 1041 static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 1042 { 1043 } 1044 1045 static inline void arch_swap_invalidate_area(int type) 1046 { 1047 } 1048 #endif 1049 1050 #ifndef __HAVE_ARCH_SWAP_RESTORE 1051 static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio) 1052 { 1053 } 1054 #endif 1055 1056 #ifndef __HAVE_ARCH_PGD_OFFSET_GATE 1057 #define pgd_offset_gate(mm, addr) pgd_offset(mm, addr) 1058 #endif 1059 1060 #ifndef __HAVE_ARCH_MOVE_PTE 1061 #define move_pte(pte, prot, old_addr, new_addr) (pte) 1062 #endif 1063 1064 #ifndef pte_accessible 1065 # define pte_accessible(mm, pte) ((void)(pte), 1) 1066 #endif 1067 1068 #ifndef flush_tlb_fix_spurious_fault 1069 #define flush_tlb_fix_spurious_fault(vma, address, ptep) flush_tlb_page(vma, address) 1070 #endif 1071 1072 /* 1073 * When walking page tables, get the address of the next boundary, 1074 * or the end address of the range if that comes earlier. Although no 1075 * vma end wraps to 0, rounded up __boundary may wrap to 0 throughout. 1076 */ 1077 1078 #define pgd_addr_end(addr, end) \ 1079 ({ unsigned long __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK; \ 1080 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 1081 }) 1082 1083 #ifndef p4d_addr_end 1084 #define p4d_addr_end(addr, end) \ 1085 ({ unsigned long __boundary = ((addr) + P4D_SIZE) & P4D_MASK; \ 1086 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 1087 }) 1088 #endif 1089 1090 #ifndef pud_addr_end 1091 #define pud_addr_end(addr, end) \ 1092 ({ unsigned long __boundary = ((addr) + PUD_SIZE) & PUD_MASK; \ 1093 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 1094 }) 1095 #endif 1096 1097 #ifndef pmd_addr_end 1098 #define pmd_addr_end(addr, end) \ 1099 ({ unsigned long __boundary = ((addr) + PMD_SIZE) & PMD_MASK; \ 1100 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 1101 }) 1102 #endif 1103 1104 /* 1105 * When walking page tables, we usually want to skip any p?d_none entries; 1106 * and any p?d_bad entries - reporting the error before resetting to none. 1107 * Do the tests inline, but report and clear the bad entry in mm/memory.c. 1108 */ 1109 void pgd_clear_bad(pgd_t *); 1110 1111 #ifndef __PAGETABLE_P4D_FOLDED 1112 void p4d_clear_bad(p4d_t *); 1113 #else 1114 #define p4d_clear_bad(p4d) do { } while (0) 1115 #endif 1116 1117 #ifndef __PAGETABLE_PUD_FOLDED 1118 void pud_clear_bad(pud_t *); 1119 #else 1120 #define pud_clear_bad(p4d) do { } while (0) 1121 #endif 1122 1123 void pmd_clear_bad(pmd_t *); 1124 1125 static inline int pgd_none_or_clear_bad(pgd_t *pgd) 1126 { 1127 if (pgd_none(*pgd)) 1128 return 1; 1129 if (unlikely(pgd_bad(*pgd))) { 1130 pgd_clear_bad(pgd); 1131 return 1; 1132 } 1133 return 0; 1134 } 1135 1136 static inline int p4d_none_or_clear_bad(p4d_t *p4d) 1137 { 1138 if (p4d_none(*p4d)) 1139 return 1; 1140 if (unlikely(p4d_bad(*p4d))) { 1141 p4d_clear_bad(p4d); 1142 return 1; 1143 } 1144 return 0; 1145 } 1146 1147 static inline int pud_none_or_clear_bad(pud_t *pud) 1148 { 1149 if (pud_none(*pud)) 1150 return 1; 1151 if (unlikely(pud_bad(*pud))) { 1152 pud_clear_bad(pud); 1153 return 1; 1154 } 1155 return 0; 1156 } 1157 1158 static inline int pmd_none_or_clear_bad(pmd_t *pmd) 1159 { 1160 if (pmd_none(*pmd)) 1161 return 1; 1162 if (unlikely(pmd_bad(*pmd))) { 1163 pmd_clear_bad(pmd); 1164 return 1; 1165 } 1166 return 0; 1167 } 1168 1169 static inline pte_t __ptep_modify_prot_start(struct vm_area_struct *vma, 1170 unsigned long addr, 1171 pte_t *ptep) 1172 { 1173 /* 1174 * Get the current pte state, but zero it out to make it 1175 * non-present, preventing the hardware from asynchronously 1176 * updating it. 1177 */ 1178 return ptep_get_and_clear(vma->vm_mm, addr, ptep); 1179 } 1180 1181 static inline void __ptep_modify_prot_commit(struct vm_area_struct *vma, 1182 unsigned long addr, 1183 pte_t *ptep, pte_t pte) 1184 { 1185 /* 1186 * The pte is non-present, so there's no hardware state to 1187 * preserve. 1188 */ 1189 set_pte_at(vma->vm_mm, addr, ptep, pte); 1190 } 1191 1192 #ifndef __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1193 /* 1194 * Start a pte protection read-modify-write transaction, which 1195 * protects against asynchronous hardware modifications to the pte. 1196 * The intention is not to prevent the hardware from making pte 1197 * updates, but to prevent any updates it may make from being lost. 1198 * 1199 * This does not protect against other software modifications of the 1200 * pte; the appropriate pte lock must be held over the transaction. 1201 * 1202 * Note that this interface is intended to be batchable, meaning that 1203 * ptep_modify_prot_commit may not actually update the pte, but merely 1204 * queue the update to be done at some later time. The update must be 1205 * actually committed before the pte lock is released, however. 1206 */ 1207 static inline pte_t ptep_modify_prot_start(struct vm_area_struct *vma, 1208 unsigned long addr, 1209 pte_t *ptep) 1210 { 1211 return __ptep_modify_prot_start(vma, addr, ptep); 1212 } 1213 1214 /* 1215 * Commit an update to a pte, leaving any hardware-controlled bits in 1216 * the PTE unmodified. 1217 */ 1218 static inline void ptep_modify_prot_commit(struct vm_area_struct *vma, 1219 unsigned long addr, 1220 pte_t *ptep, pte_t old_pte, pte_t pte) 1221 { 1222 __ptep_modify_prot_commit(vma, addr, ptep, pte); 1223 } 1224 #endif /* __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION */ 1225 #endif /* CONFIG_MMU */ 1226 1227 /* 1228 * No-op macros that just return the current protection value. Defined here 1229 * because these macros can be used even if CONFIG_MMU is not defined. 1230 */ 1231 1232 #ifndef pgprot_nx 1233 #define pgprot_nx(prot) (prot) 1234 #endif 1235 1236 #ifndef pgprot_noncached 1237 #define pgprot_noncached(prot) (prot) 1238 #endif 1239 1240 #ifndef pgprot_writecombine 1241 #define pgprot_writecombine pgprot_noncached 1242 #endif 1243 1244 #ifndef pgprot_writethrough 1245 #define pgprot_writethrough pgprot_noncached 1246 #endif 1247 1248 #ifndef pgprot_device 1249 #define pgprot_device pgprot_noncached 1250 #endif 1251 1252 #ifndef pgprot_mhp 1253 #define pgprot_mhp(prot) (prot) 1254 #endif 1255 1256 #ifdef CONFIG_MMU 1257 #ifndef pgprot_modify 1258 #define pgprot_modify pgprot_modify 1259 static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot) 1260 { 1261 if (pgprot_val(oldprot) == pgprot_val(pgprot_noncached(oldprot))) 1262 newprot = pgprot_noncached(newprot); 1263 if (pgprot_val(oldprot) == pgprot_val(pgprot_writecombine(oldprot))) 1264 newprot = pgprot_writecombine(newprot); 1265 if (pgprot_val(oldprot) == pgprot_val(pgprot_device(oldprot))) 1266 newprot = pgprot_device(newprot); 1267 return newprot; 1268 } 1269 #endif 1270 #endif /* CONFIG_MMU */ 1271 1272 #ifndef pgprot_encrypted 1273 #define pgprot_encrypted(prot) (prot) 1274 #endif 1275 1276 #ifndef pgprot_decrypted 1277 #define pgprot_decrypted(prot) (prot) 1278 #endif 1279 1280 /* 1281 * A facility to provide batching of the reload of page tables and 1282 * other process state with the actual context switch code for 1283 * paravirtualized guests. By convention, only one of the batched 1284 * update (lazy) modes (CPU, MMU) should be active at any given time, 1285 * entry should never be nested, and entry and exits should always be 1286 * paired. This is for sanity of maintaining and reasoning about the 1287 * kernel code. In this case, the exit (end of the context switch) is 1288 * in architecture-specific code, and so doesn't need a generic 1289 * definition. 1290 */ 1291 #ifndef __HAVE_ARCH_START_CONTEXT_SWITCH 1292 #define arch_start_context_switch(prev) do {} while (0) 1293 #endif 1294 1295 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1296 #ifndef CONFIG_ARCH_ENABLE_THP_MIGRATION 1297 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) 1298 { 1299 return pmd; 1300 } 1301 1302 static inline int pmd_swp_soft_dirty(pmd_t pmd) 1303 { 1304 return 0; 1305 } 1306 1307 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) 1308 { 1309 return pmd; 1310 } 1311 #endif 1312 #else /* !CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1313 static inline int pte_soft_dirty(pte_t pte) 1314 { 1315 return 0; 1316 } 1317 1318 static inline int pmd_soft_dirty(pmd_t pmd) 1319 { 1320 return 0; 1321 } 1322 1323 static inline pte_t pte_mksoft_dirty(pte_t pte) 1324 { 1325 return pte; 1326 } 1327 1328 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 1329 { 1330 return pmd; 1331 } 1332 1333 static inline pte_t pte_clear_soft_dirty(pte_t pte) 1334 { 1335 return pte; 1336 } 1337 1338 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 1339 { 1340 return pmd; 1341 } 1342 1343 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 1344 { 1345 return pte; 1346 } 1347 1348 static inline int pte_swp_soft_dirty(pte_t pte) 1349 { 1350 return 0; 1351 } 1352 1353 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 1354 { 1355 return pte; 1356 } 1357 1358 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) 1359 { 1360 return pmd; 1361 } 1362 1363 static inline int pmd_swp_soft_dirty(pmd_t pmd) 1364 { 1365 return 0; 1366 } 1367 1368 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) 1369 { 1370 return pmd; 1371 } 1372 #endif 1373 1374 #ifndef __HAVE_PFNMAP_TRACKING 1375 /* 1376 * Interfaces that can be used by architecture code to keep track of 1377 * memory type of pfn mappings specified by the remap_pfn_range, 1378 * vmf_insert_pfn. 1379 */ 1380 1381 /* 1382 * track_pfn_remap is called when a _new_ pfn mapping is being established 1383 * by remap_pfn_range() for physical range indicated by pfn and size. 1384 */ 1385 static inline int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot, 1386 unsigned long pfn, unsigned long addr, 1387 unsigned long size) 1388 { 1389 return 0; 1390 } 1391 1392 /* 1393 * track_pfn_insert is called when a _new_ single pfn is established 1394 * by vmf_insert_pfn(). 1395 */ 1396 static inline void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot, 1397 pfn_t pfn) 1398 { 1399 } 1400 1401 /* 1402 * track_pfn_copy is called when vma that is covering the pfnmap gets 1403 * copied through copy_page_range(). 1404 */ 1405 static inline int track_pfn_copy(struct vm_area_struct *vma) 1406 { 1407 return 0; 1408 } 1409 1410 /* 1411 * untrack_pfn is called while unmapping a pfnmap for a region. 1412 * untrack can be called for a specific region indicated by pfn and size or 1413 * can be for the entire vma (in which case pfn, size are zero). 1414 */ 1415 static inline void untrack_pfn(struct vm_area_struct *vma, 1416 unsigned long pfn, unsigned long size, 1417 bool mm_wr_locked) 1418 { 1419 } 1420 1421 /* 1422 * untrack_pfn_clear is called while mremapping a pfnmap for a new region 1423 * or fails to copy pgtable during duplicate vm area. 1424 */ 1425 static inline void untrack_pfn_clear(struct vm_area_struct *vma) 1426 { 1427 } 1428 #else 1429 extern int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot, 1430 unsigned long pfn, unsigned long addr, 1431 unsigned long size); 1432 extern void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot, 1433 pfn_t pfn); 1434 extern int track_pfn_copy(struct vm_area_struct *vma); 1435 extern void untrack_pfn(struct vm_area_struct *vma, unsigned long pfn, 1436 unsigned long size, bool mm_wr_locked); 1437 extern void untrack_pfn_clear(struct vm_area_struct *vma); 1438 #endif 1439 1440 #ifdef CONFIG_MMU 1441 #ifdef __HAVE_COLOR_ZERO_PAGE 1442 static inline int is_zero_pfn(unsigned long pfn) 1443 { 1444 extern unsigned long zero_pfn; 1445 unsigned long offset_from_zero_pfn = pfn - zero_pfn; 1446 return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT); 1447 } 1448 1449 #define my_zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr)) 1450 1451 #else 1452 static inline int is_zero_pfn(unsigned long pfn) 1453 { 1454 extern unsigned long zero_pfn; 1455 return pfn == zero_pfn; 1456 } 1457 1458 static inline unsigned long my_zero_pfn(unsigned long addr) 1459 { 1460 extern unsigned long zero_pfn; 1461 return zero_pfn; 1462 } 1463 #endif 1464 #else 1465 static inline int is_zero_pfn(unsigned long pfn) 1466 { 1467 return 0; 1468 } 1469 1470 static inline unsigned long my_zero_pfn(unsigned long addr) 1471 { 1472 return 0; 1473 } 1474 #endif /* CONFIG_MMU */ 1475 1476 #ifdef CONFIG_MMU 1477 1478 #ifndef CONFIG_TRANSPARENT_HUGEPAGE 1479 static inline int pmd_trans_huge(pmd_t pmd) 1480 { 1481 return 0; 1482 } 1483 #ifndef pmd_write 1484 static inline int pmd_write(pmd_t pmd) 1485 { 1486 BUG(); 1487 return 0; 1488 } 1489 #endif /* pmd_write */ 1490 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1491 1492 #ifndef pud_write 1493 static inline int pud_write(pud_t pud) 1494 { 1495 BUG(); 1496 return 0; 1497 } 1498 #endif /* pud_write */ 1499 1500 #if !defined(CONFIG_ARCH_HAS_PTE_DEVMAP) || !defined(CONFIG_TRANSPARENT_HUGEPAGE) 1501 static inline int pmd_devmap(pmd_t pmd) 1502 { 1503 return 0; 1504 } 1505 static inline int pud_devmap(pud_t pud) 1506 { 1507 return 0; 1508 } 1509 static inline int pgd_devmap(pgd_t pgd) 1510 { 1511 return 0; 1512 } 1513 #endif 1514 1515 #if !defined(CONFIG_TRANSPARENT_HUGEPAGE) || \ 1516 !defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) 1517 static inline int pud_trans_huge(pud_t pud) 1518 { 1519 return 0; 1520 } 1521 #endif 1522 1523 static inline int pud_trans_unstable(pud_t *pud) 1524 { 1525 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) && \ 1526 defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) 1527 pud_t pudval = READ_ONCE(*pud); 1528 1529 if (pud_none(pudval) || pud_trans_huge(pudval) || pud_devmap(pudval)) 1530 return 1; 1531 if (unlikely(pud_bad(pudval))) { 1532 pud_clear_bad(pud); 1533 return 1; 1534 } 1535 #endif 1536 return 0; 1537 } 1538 1539 #ifndef CONFIG_NUMA_BALANCING 1540 /* 1541 * In an inaccessible (PROT_NONE) VMA, pte_protnone() may indicate "yes". It is 1542 * perfectly valid to indicate "no" in that case, which is why our default 1543 * implementation defaults to "always no". 1544 * 1545 * In an accessible VMA, however, pte_protnone() reliably indicates PROT_NONE 1546 * page protection due to NUMA hinting. NUMA hinting faults only apply in 1547 * accessible VMAs. 1548 * 1549 * So, to reliably identify PROT_NONE PTEs that require a NUMA hinting fault, 1550 * looking at the VMA accessibility is sufficient. 1551 */ 1552 static inline int pte_protnone(pte_t pte) 1553 { 1554 return 0; 1555 } 1556 1557 static inline int pmd_protnone(pmd_t pmd) 1558 { 1559 return 0; 1560 } 1561 #endif /* CONFIG_NUMA_BALANCING */ 1562 1563 #endif /* CONFIG_MMU */ 1564 1565 #ifdef CONFIG_HAVE_ARCH_HUGE_VMAP 1566 1567 #ifndef __PAGETABLE_P4D_FOLDED 1568 int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot); 1569 void p4d_clear_huge(p4d_t *p4d); 1570 #else 1571 static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot) 1572 { 1573 return 0; 1574 } 1575 static inline void p4d_clear_huge(p4d_t *p4d) { } 1576 #endif /* !__PAGETABLE_P4D_FOLDED */ 1577 1578 int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot); 1579 int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot); 1580 int pud_clear_huge(pud_t *pud); 1581 int pmd_clear_huge(pmd_t *pmd); 1582 int p4d_free_pud_page(p4d_t *p4d, unsigned long addr); 1583 int pud_free_pmd_page(pud_t *pud, unsigned long addr); 1584 int pmd_free_pte_page(pmd_t *pmd, unsigned long addr); 1585 #else /* !CONFIG_HAVE_ARCH_HUGE_VMAP */ 1586 static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot) 1587 { 1588 return 0; 1589 } 1590 static inline int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot) 1591 { 1592 return 0; 1593 } 1594 static inline int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot) 1595 { 1596 return 0; 1597 } 1598 static inline void p4d_clear_huge(p4d_t *p4d) { } 1599 static inline int pud_clear_huge(pud_t *pud) 1600 { 1601 return 0; 1602 } 1603 static inline int pmd_clear_huge(pmd_t *pmd) 1604 { 1605 return 0; 1606 } 1607 static inline int p4d_free_pud_page(p4d_t *p4d, unsigned long addr) 1608 { 1609 return 0; 1610 } 1611 static inline int pud_free_pmd_page(pud_t *pud, unsigned long addr) 1612 { 1613 return 0; 1614 } 1615 static inline int pmd_free_pte_page(pmd_t *pmd, unsigned long addr) 1616 { 1617 return 0; 1618 } 1619 #endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */ 1620 1621 #ifndef __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 1622 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1623 /* 1624 * ARCHes with special requirements for evicting THP backing TLB entries can 1625 * implement this. Otherwise also, it can help optimize normal TLB flush in 1626 * THP regime. Stock flush_tlb_range() typically has optimization to nuke the 1627 * entire TLB if flush span is greater than a threshold, which will 1628 * likely be true for a single huge page. Thus a single THP flush will 1629 * invalidate the entire TLB which is not desirable. 1630 * e.g. see arch/arc: flush_pmd_tlb_range 1631 */ 1632 #define flush_pmd_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end) 1633 #define flush_pud_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end) 1634 #else 1635 #define flush_pmd_tlb_range(vma, addr, end) BUILD_BUG() 1636 #define flush_pud_tlb_range(vma, addr, end) BUILD_BUG() 1637 #endif 1638 #endif 1639 1640 struct file; 1641 int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn, 1642 unsigned long size, pgprot_t *vma_prot); 1643 1644 #ifndef CONFIG_X86_ESPFIX64 1645 static inline void init_espfix_bsp(void) { } 1646 #endif 1647 1648 extern void __init pgtable_cache_init(void); 1649 1650 #ifndef __HAVE_ARCH_PFN_MODIFY_ALLOWED 1651 static inline bool pfn_modify_allowed(unsigned long pfn, pgprot_t prot) 1652 { 1653 return true; 1654 } 1655 1656 static inline bool arch_has_pfn_modify_check(void) 1657 { 1658 return false; 1659 } 1660 #endif /* !_HAVE_ARCH_PFN_MODIFY_ALLOWED */ 1661 1662 /* 1663 * Architecture PAGE_KERNEL_* fallbacks 1664 * 1665 * Some architectures don't define certain PAGE_KERNEL_* flags. This is either 1666 * because they really don't support them, or the port needs to be updated to 1667 * reflect the required functionality. Below are a set of relatively safe 1668 * fallbacks, as best effort, which we can count on in lieu of the architectures 1669 * not defining them on their own yet. 1670 */ 1671 1672 #ifndef PAGE_KERNEL_RO 1673 # define PAGE_KERNEL_RO PAGE_KERNEL 1674 #endif 1675 1676 #ifndef PAGE_KERNEL_EXEC 1677 # define PAGE_KERNEL_EXEC PAGE_KERNEL 1678 #endif 1679 1680 /* 1681 * Page Table Modification bits for pgtbl_mod_mask. 1682 * 1683 * These are used by the p?d_alloc_track*() set of functions an in the generic 1684 * vmalloc/ioremap code to track at which page-table levels entries have been 1685 * modified. Based on that the code can better decide when vmalloc and ioremap 1686 * mapping changes need to be synchronized to other page-tables in the system. 1687 */ 1688 #define __PGTBL_PGD_MODIFIED 0 1689 #define __PGTBL_P4D_MODIFIED 1 1690 #define __PGTBL_PUD_MODIFIED 2 1691 #define __PGTBL_PMD_MODIFIED 3 1692 #define __PGTBL_PTE_MODIFIED 4 1693 1694 #define PGTBL_PGD_MODIFIED BIT(__PGTBL_PGD_MODIFIED) 1695 #define PGTBL_P4D_MODIFIED BIT(__PGTBL_P4D_MODIFIED) 1696 #define PGTBL_PUD_MODIFIED BIT(__PGTBL_PUD_MODIFIED) 1697 #define PGTBL_PMD_MODIFIED BIT(__PGTBL_PMD_MODIFIED) 1698 #define PGTBL_PTE_MODIFIED BIT(__PGTBL_PTE_MODIFIED) 1699 1700 /* Page-Table Modification Mask */ 1701 typedef unsigned int pgtbl_mod_mask; 1702 1703 #endif /* !__ASSEMBLY__ */ 1704 1705 #if !defined(MAX_POSSIBLE_PHYSMEM_BITS) && !defined(CONFIG_64BIT) 1706 #ifdef CONFIG_PHYS_ADDR_T_64BIT 1707 /* 1708 * ZSMALLOC needs to know the highest PFN on 32-bit architectures 1709 * with physical address space extension, but falls back to 1710 * BITS_PER_LONG otherwise. 1711 */ 1712 #error Missing MAX_POSSIBLE_PHYSMEM_BITS definition 1713 #else 1714 #define MAX_POSSIBLE_PHYSMEM_BITS 32 1715 #endif 1716 #endif 1717 1718 #ifndef has_transparent_hugepage 1719 #define has_transparent_hugepage() IS_BUILTIN(CONFIG_TRANSPARENT_HUGEPAGE) 1720 #endif 1721 1722 #ifndef has_transparent_pud_hugepage 1723 #define has_transparent_pud_hugepage() IS_BUILTIN(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) 1724 #endif 1725 /* 1726 * On some architectures it depends on the mm if the p4d/pud or pmd 1727 * layer of the page table hierarchy is folded or not. 1728 */ 1729 #ifndef mm_p4d_folded 1730 #define mm_p4d_folded(mm) __is_defined(__PAGETABLE_P4D_FOLDED) 1731 #endif 1732 1733 #ifndef mm_pud_folded 1734 #define mm_pud_folded(mm) __is_defined(__PAGETABLE_PUD_FOLDED) 1735 #endif 1736 1737 #ifndef mm_pmd_folded 1738 #define mm_pmd_folded(mm) __is_defined(__PAGETABLE_PMD_FOLDED) 1739 #endif 1740 1741 #ifndef p4d_offset_lockless 1742 #define p4d_offset_lockless(pgdp, pgd, address) p4d_offset(&(pgd), address) 1743 #endif 1744 #ifndef pud_offset_lockless 1745 #define pud_offset_lockless(p4dp, p4d, address) pud_offset(&(p4d), address) 1746 #endif 1747 #ifndef pmd_offset_lockless 1748 #define pmd_offset_lockless(pudp, pud, address) pmd_offset(&(pud), address) 1749 #endif 1750 1751 /* 1752 * p?d_leaf() - true if this entry is a final mapping to a physical address. 1753 * This differs from p?d_huge() by the fact that they are always available (if 1754 * the architecture supports large pages at the appropriate level) even 1755 * if CONFIG_HUGETLB_PAGE is not defined. 1756 * Only meaningful when called on a valid entry. 1757 */ 1758 #ifndef pgd_leaf 1759 #define pgd_leaf(x) 0 1760 #endif 1761 #ifndef p4d_leaf 1762 #define p4d_leaf(x) 0 1763 #endif 1764 #ifndef pud_leaf 1765 #define pud_leaf(x) 0 1766 #endif 1767 #ifndef pmd_leaf 1768 #define pmd_leaf(x) 0 1769 #endif 1770 1771 #ifndef pgd_leaf_size 1772 #define pgd_leaf_size(x) (1ULL << PGDIR_SHIFT) 1773 #endif 1774 #ifndef p4d_leaf_size 1775 #define p4d_leaf_size(x) P4D_SIZE 1776 #endif 1777 #ifndef pud_leaf_size 1778 #define pud_leaf_size(x) PUD_SIZE 1779 #endif 1780 #ifndef pmd_leaf_size 1781 #define pmd_leaf_size(x) PMD_SIZE 1782 #endif 1783 #ifndef pte_leaf_size 1784 #define pte_leaf_size(x) PAGE_SIZE 1785 #endif 1786 1787 /* 1788 * Some architectures have MMUs that are configurable or selectable at boot 1789 * time. These lead to variable PTRS_PER_x. For statically allocated arrays it 1790 * helps to have a static maximum value. 1791 */ 1792 1793 #ifndef MAX_PTRS_PER_PTE 1794 #define MAX_PTRS_PER_PTE PTRS_PER_PTE 1795 #endif 1796 1797 #ifndef MAX_PTRS_PER_PMD 1798 #define MAX_PTRS_PER_PMD PTRS_PER_PMD 1799 #endif 1800 1801 #ifndef MAX_PTRS_PER_PUD 1802 #define MAX_PTRS_PER_PUD PTRS_PER_PUD 1803 #endif 1804 1805 #ifndef MAX_PTRS_PER_P4D 1806 #define MAX_PTRS_PER_P4D PTRS_PER_P4D 1807 #endif 1808 1809 /* description of effects of mapping type and prot in current implementation. 1810 * this is due to the limited x86 page protection hardware. The expected 1811 * behavior is in parens: 1812 * 1813 * map_type prot 1814 * PROT_NONE PROT_READ PROT_WRITE PROT_EXEC 1815 * MAP_SHARED r: (no) no r: (yes) yes r: (no) yes r: (no) yes 1816 * w: (no) no w: (no) no w: (yes) yes w: (no) no 1817 * x: (no) no x: (no) yes x: (no) yes x: (yes) yes 1818 * 1819 * MAP_PRIVATE r: (no) no r: (yes) yes r: (no) yes r: (no) yes 1820 * w: (no) no w: (no) no w: (copy) copy w: (no) no 1821 * x: (no) no x: (no) yes x: (no) yes x: (yes) yes 1822 * 1823 * On arm64, PROT_EXEC has the following behaviour for both MAP_SHARED and 1824 * MAP_PRIVATE (with Enhanced PAN supported): 1825 * r: (no) no 1826 * w: (no) no 1827 * x: (yes) yes 1828 */ 1829 #define DECLARE_VM_GET_PAGE_PROT \ 1830 pgprot_t vm_get_page_prot(unsigned long vm_flags) \ 1831 { \ 1832 return protection_map[vm_flags & \ 1833 (VM_READ | VM_WRITE | VM_EXEC | VM_SHARED)]; \ 1834 } \ 1835 EXPORT_SYMBOL(vm_get_page_prot); 1836 1837 #endif /* _LINUX_PGTABLE_H */ 1838