1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _LINUX_PGTABLE_H 3 #define _LINUX_PGTABLE_H 4 5 #include <linux/pfn.h> 6 #include <asm/pgtable.h> 7 8 #define PMD_ORDER (PMD_SHIFT - PAGE_SHIFT) 9 #define PUD_ORDER (PUD_SHIFT - PAGE_SHIFT) 10 11 #ifndef __ASSEMBLY__ 12 #ifdef CONFIG_MMU 13 14 #include <linux/mm_types.h> 15 #include <linux/bug.h> 16 #include <linux/errno.h> 17 #include <asm-generic/pgtable_uffd.h> 18 #include <linux/page_table_check.h> 19 20 #if 5 - defined(__PAGETABLE_P4D_FOLDED) - defined(__PAGETABLE_PUD_FOLDED) - \ 21 defined(__PAGETABLE_PMD_FOLDED) != CONFIG_PGTABLE_LEVELS 22 #error CONFIG_PGTABLE_LEVELS is not consistent with __PAGETABLE_{P4D,PUD,PMD}_FOLDED 23 #endif 24 25 /* 26 * On almost all architectures and configurations, 0 can be used as the 27 * upper ceiling to free_pgtables(): on many architectures it has the same 28 * effect as using TASK_SIZE. However, there is one configuration which 29 * must impose a more careful limit, to avoid freeing kernel pgtables. 30 */ 31 #ifndef USER_PGTABLES_CEILING 32 #define USER_PGTABLES_CEILING 0UL 33 #endif 34 35 /* 36 * This defines the first usable user address. Platforms 37 * can override its value with custom FIRST_USER_ADDRESS 38 * defined in their respective <asm/pgtable.h>. 39 */ 40 #ifndef FIRST_USER_ADDRESS 41 #define FIRST_USER_ADDRESS 0UL 42 #endif 43 44 /* 45 * This defines the generic helper for accessing PMD page 46 * table page. Although platforms can still override this 47 * via their respective <asm/pgtable.h>. 48 */ 49 #ifndef pmd_pgtable 50 #define pmd_pgtable(pmd) pmd_page(pmd) 51 #endif 52 53 #define pmd_folio(pmd) page_folio(pmd_page(pmd)) 54 55 /* 56 * A page table page can be thought of an array like this: pXd_t[PTRS_PER_PxD] 57 * 58 * The pXx_index() functions return the index of the entry in the page 59 * table page which would control the given virtual address 60 * 61 * As these functions may be used by the same code for different levels of 62 * the page table folding, they are always available, regardless of 63 * CONFIG_PGTABLE_LEVELS value. For the folded levels they simply return 0 64 * because in such cases PTRS_PER_PxD equals 1. 65 */ 66 67 static inline unsigned long pte_index(unsigned long address) 68 { 69 return (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1); 70 } 71 72 #ifndef pmd_index 73 static inline unsigned long pmd_index(unsigned long address) 74 { 75 return (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1); 76 } 77 #define pmd_index pmd_index 78 #endif 79 80 #ifndef pud_index 81 static inline unsigned long pud_index(unsigned long address) 82 { 83 return (address >> PUD_SHIFT) & (PTRS_PER_PUD - 1); 84 } 85 #define pud_index pud_index 86 #endif 87 88 #ifndef pgd_index 89 /* Must be a compile-time constant, so implement it as a macro */ 90 #define pgd_index(a) (((a) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 91 #endif 92 93 #ifndef pte_offset_kernel 94 static inline pte_t *pte_offset_kernel(pmd_t *pmd, unsigned long address) 95 { 96 return (pte_t *)pmd_page_vaddr(*pmd) + pte_index(address); 97 } 98 #define pte_offset_kernel pte_offset_kernel 99 #endif 100 101 #ifdef CONFIG_HIGHPTE 102 #define __pte_map(pmd, address) \ 103 ((pte_t *)kmap_local_page(pmd_page(*(pmd))) + pte_index((address))) 104 #define pte_unmap(pte) do { \ 105 kunmap_local((pte)); \ 106 rcu_read_unlock(); \ 107 } while (0) 108 #else 109 static inline pte_t *__pte_map(pmd_t *pmd, unsigned long address) 110 { 111 return pte_offset_kernel(pmd, address); 112 } 113 static inline void pte_unmap(pte_t *pte) 114 { 115 rcu_read_unlock(); 116 } 117 #endif 118 119 void pte_free_defer(struct mm_struct *mm, pgtable_t pgtable); 120 121 /* Find an entry in the second-level page table.. */ 122 #ifndef pmd_offset 123 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) 124 { 125 return pud_pgtable(*pud) + pmd_index(address); 126 } 127 #define pmd_offset pmd_offset 128 #endif 129 130 #ifndef pud_offset 131 static inline pud_t *pud_offset(p4d_t *p4d, unsigned long address) 132 { 133 return p4d_pgtable(*p4d) + pud_index(address); 134 } 135 #define pud_offset pud_offset 136 #endif 137 138 static inline pgd_t *pgd_offset_pgd(pgd_t *pgd, unsigned long address) 139 { 140 return (pgd + pgd_index(address)); 141 }; 142 143 /* 144 * a shortcut to get a pgd_t in a given mm 145 */ 146 #ifndef pgd_offset 147 #define pgd_offset(mm, address) pgd_offset_pgd((mm)->pgd, (address)) 148 #endif 149 150 /* 151 * a shortcut which implies the use of the kernel's pgd, instead 152 * of a process's 153 */ 154 #define pgd_offset_k(address) pgd_offset(&init_mm, (address)) 155 156 /* 157 * In many cases it is known that a virtual address is mapped at PMD or PTE 158 * level, so instead of traversing all the page table levels, we can get a 159 * pointer to the PMD entry in user or kernel page table or translate a virtual 160 * address to the pointer in the PTE in the kernel page tables with simple 161 * helpers. 162 */ 163 static inline pmd_t *pmd_off(struct mm_struct *mm, unsigned long va) 164 { 165 return pmd_offset(pud_offset(p4d_offset(pgd_offset(mm, va), va), va), va); 166 } 167 168 static inline pmd_t *pmd_off_k(unsigned long va) 169 { 170 return pmd_offset(pud_offset(p4d_offset(pgd_offset_k(va), va), va), va); 171 } 172 173 static inline pte_t *virt_to_kpte(unsigned long vaddr) 174 { 175 pmd_t *pmd = pmd_off_k(vaddr); 176 177 return pmd_none(*pmd) ? NULL : pte_offset_kernel(pmd, vaddr); 178 } 179 180 #ifndef pmd_young 181 static inline int pmd_young(pmd_t pmd) 182 { 183 return 0; 184 } 185 #endif 186 187 #ifndef pmd_dirty 188 static inline int pmd_dirty(pmd_t pmd) 189 { 190 return 0; 191 } 192 #endif 193 194 /* 195 * A facility to provide lazy MMU batching. This allows PTE updates and 196 * page invalidations to be delayed until a call to leave lazy MMU mode 197 * is issued. Some architectures may benefit from doing this, and it is 198 * beneficial for both shadow and direct mode hypervisors, which may batch 199 * the PTE updates which happen during this window. Note that using this 200 * interface requires that read hazards be removed from the code. A read 201 * hazard could result in the direct mode hypervisor case, since the actual 202 * write to the page tables may not yet have taken place, so reads though 203 * a raw PTE pointer after it has been modified are not guaranteed to be 204 * up to date. This mode can only be entered and left under the protection of 205 * the page table locks for all page tables which may be modified. In the UP 206 * case, this is required so that preemption is disabled, and in the SMP case, 207 * it must synchronize the delayed page table writes properly on other CPUs. 208 */ 209 #ifndef __HAVE_ARCH_ENTER_LAZY_MMU_MODE 210 #define arch_enter_lazy_mmu_mode() do {} while (0) 211 #define arch_leave_lazy_mmu_mode() do {} while (0) 212 #define arch_flush_lazy_mmu_mode() do {} while (0) 213 #endif 214 215 #ifndef pte_batch_hint 216 /** 217 * pte_batch_hint - Number of pages that can be added to batch without scanning. 218 * @ptep: Page table pointer for the entry. 219 * @pte: Page table entry. 220 * 221 * Some architectures know that a set of contiguous ptes all map the same 222 * contiguous memory with the same permissions. In this case, it can provide a 223 * hint to aid pte batching without the core code needing to scan every pte. 224 * 225 * An architecture implementation may ignore the PTE accessed state. Further, 226 * the dirty state must apply atomically to all the PTEs described by the hint. 227 * 228 * May be overridden by the architecture, else pte_batch_hint is always 1. 229 */ 230 static inline unsigned int pte_batch_hint(pte_t *ptep, pte_t pte) 231 { 232 return 1; 233 } 234 #endif 235 236 #ifndef pte_advance_pfn 237 static inline pte_t pte_advance_pfn(pte_t pte, unsigned long nr) 238 { 239 return __pte(pte_val(pte) + (nr << PFN_PTE_SHIFT)); 240 } 241 #endif 242 243 #define pte_next_pfn(pte) pte_advance_pfn(pte, 1) 244 245 #ifndef set_ptes 246 /** 247 * set_ptes - Map consecutive pages to a contiguous range of addresses. 248 * @mm: Address space to map the pages into. 249 * @addr: Address to map the first page at. 250 * @ptep: Page table pointer for the first entry. 251 * @pte: Page table entry for the first page. 252 * @nr: Number of pages to map. 253 * 254 * When nr==1, initial state of pte may be present or not present, and new state 255 * may be present or not present. When nr>1, initial state of all ptes must be 256 * not present, and new state must be present. 257 * 258 * May be overridden by the architecture, or the architecture can define 259 * set_pte() and PFN_PTE_SHIFT. 260 * 261 * Context: The caller holds the page table lock. The pages all belong 262 * to the same folio. The PTEs are all in the same PMD. 263 */ 264 static inline void set_ptes(struct mm_struct *mm, unsigned long addr, 265 pte_t *ptep, pte_t pte, unsigned int nr) 266 { 267 page_table_check_ptes_set(mm, ptep, pte, nr); 268 269 arch_enter_lazy_mmu_mode(); 270 for (;;) { 271 set_pte(ptep, pte); 272 if (--nr == 0) 273 break; 274 ptep++; 275 pte = pte_next_pfn(pte); 276 } 277 arch_leave_lazy_mmu_mode(); 278 } 279 #endif 280 #define set_pte_at(mm, addr, ptep, pte) set_ptes(mm, addr, ptep, pte, 1) 281 282 #ifndef __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 283 extern int ptep_set_access_flags(struct vm_area_struct *vma, 284 unsigned long address, pte_t *ptep, 285 pte_t entry, int dirty); 286 #endif 287 288 #ifndef __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 289 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 290 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 291 unsigned long address, pmd_t *pmdp, 292 pmd_t entry, int dirty); 293 extern int pudp_set_access_flags(struct vm_area_struct *vma, 294 unsigned long address, pud_t *pudp, 295 pud_t entry, int dirty); 296 #else 297 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 298 unsigned long address, pmd_t *pmdp, 299 pmd_t entry, int dirty) 300 { 301 BUILD_BUG(); 302 return 0; 303 } 304 static inline int pudp_set_access_flags(struct vm_area_struct *vma, 305 unsigned long address, pud_t *pudp, 306 pud_t entry, int dirty) 307 { 308 BUILD_BUG(); 309 return 0; 310 } 311 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 312 #endif 313 314 #ifndef ptep_get 315 static inline pte_t ptep_get(pte_t *ptep) 316 { 317 return READ_ONCE(*ptep); 318 } 319 #endif 320 321 #ifndef pmdp_get 322 static inline pmd_t pmdp_get(pmd_t *pmdp) 323 { 324 return READ_ONCE(*pmdp); 325 } 326 #endif 327 328 #ifndef pudp_get 329 static inline pud_t pudp_get(pud_t *pudp) 330 { 331 return READ_ONCE(*pudp); 332 } 333 #endif 334 335 #ifndef p4dp_get 336 static inline p4d_t p4dp_get(p4d_t *p4dp) 337 { 338 return READ_ONCE(*p4dp); 339 } 340 #endif 341 342 #ifndef pgdp_get 343 static inline pgd_t pgdp_get(pgd_t *pgdp) 344 { 345 return READ_ONCE(*pgdp); 346 } 347 #endif 348 349 #ifndef __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 350 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 351 unsigned long address, 352 pte_t *ptep) 353 { 354 pte_t pte = ptep_get(ptep); 355 int r = 1; 356 if (!pte_young(pte)) 357 r = 0; 358 else 359 set_pte_at(vma->vm_mm, address, ptep, pte_mkold(pte)); 360 return r; 361 } 362 #endif 363 364 #ifndef mkold_ptes 365 /** 366 * mkold_ptes - Mark PTEs that map consecutive pages of the same folio as old. 367 * @vma: VMA the pages are mapped into. 368 * @addr: Address the first page is mapped at. 369 * @ptep: Page table pointer for the first entry. 370 * @nr: Number of entries to mark old. 371 * 372 * May be overridden by the architecture; otherwise, implemented as a simple 373 * loop over ptep_test_and_clear_young(). 374 * 375 * Note that PTE bits in the PTE range besides the PFN can differ. For example, 376 * some PTEs might be write-protected. 377 * 378 * Context: The caller holds the page table lock. The PTEs map consecutive 379 * pages that belong to the same folio. The PTEs are all in the same PMD. 380 */ 381 static inline void mkold_ptes(struct vm_area_struct *vma, unsigned long addr, 382 pte_t *ptep, unsigned int nr) 383 { 384 for (;;) { 385 ptep_test_and_clear_young(vma, addr, ptep); 386 if (--nr == 0) 387 break; 388 ptep++; 389 addr += PAGE_SIZE; 390 } 391 } 392 #endif 393 394 #ifndef __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 395 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG) 396 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 397 unsigned long address, 398 pmd_t *pmdp) 399 { 400 pmd_t pmd = *pmdp; 401 int r = 1; 402 if (!pmd_young(pmd)) 403 r = 0; 404 else 405 set_pmd_at(vma->vm_mm, address, pmdp, pmd_mkold(pmd)); 406 return r; 407 } 408 #else 409 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 410 unsigned long address, 411 pmd_t *pmdp) 412 { 413 BUILD_BUG(); 414 return 0; 415 } 416 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG */ 417 #endif 418 419 #ifndef __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 420 int ptep_clear_flush_young(struct vm_area_struct *vma, 421 unsigned long address, pte_t *ptep); 422 #endif 423 424 #ifndef __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 425 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 426 extern int pmdp_clear_flush_young(struct vm_area_struct *vma, 427 unsigned long address, pmd_t *pmdp); 428 #else 429 /* 430 * Despite relevant to THP only, this API is called from generic rmap code 431 * under PageTransHuge(), hence needs a dummy implementation for !THP 432 */ 433 static inline int pmdp_clear_flush_young(struct vm_area_struct *vma, 434 unsigned long address, pmd_t *pmdp) 435 { 436 BUILD_BUG(); 437 return 0; 438 } 439 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 440 #endif 441 442 #ifndef arch_has_hw_nonleaf_pmd_young 443 /* 444 * Return whether the accessed bit in non-leaf PMD entries is supported on the 445 * local CPU. 446 */ 447 static inline bool arch_has_hw_nonleaf_pmd_young(void) 448 { 449 return IS_ENABLED(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG); 450 } 451 #endif 452 453 #ifndef arch_has_hw_pte_young 454 /* 455 * Return whether the accessed bit is supported on the local CPU. 456 * 457 * This stub assumes accessing through an old PTE triggers a page fault. 458 * Architectures that automatically set the access bit should overwrite it. 459 */ 460 static inline bool arch_has_hw_pte_young(void) 461 { 462 return IS_ENABLED(CONFIG_ARCH_HAS_HW_PTE_YOUNG); 463 } 464 #endif 465 466 #ifndef arch_check_zapped_pte 467 static inline void arch_check_zapped_pte(struct vm_area_struct *vma, 468 pte_t pte) 469 { 470 } 471 #endif 472 473 #ifndef arch_check_zapped_pmd 474 static inline void arch_check_zapped_pmd(struct vm_area_struct *vma, 475 pmd_t pmd) 476 { 477 } 478 #endif 479 480 #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR 481 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 482 unsigned long address, 483 pte_t *ptep) 484 { 485 pte_t pte = ptep_get(ptep); 486 pte_clear(mm, address, ptep); 487 page_table_check_pte_clear(mm, pte); 488 return pte; 489 } 490 #endif 491 492 static inline void ptep_clear(struct mm_struct *mm, unsigned long addr, 493 pte_t *ptep) 494 { 495 ptep_get_and_clear(mm, addr, ptep); 496 } 497 498 #ifdef CONFIG_GUP_GET_PXX_LOW_HIGH 499 /* 500 * For walking the pagetables without holding any locks. Some architectures 501 * (eg x86-32 PAE) cannot load the entries atomically without using expensive 502 * instructions. We are guaranteed that a PTE will only either go from not 503 * present to present, or present to not present -- it will not switch to a 504 * completely different present page without a TLB flush inbetween; which we 505 * are blocking by holding interrupts off. 506 * 507 * Setting ptes from not present to present goes: 508 * 509 * ptep->pte_high = h; 510 * smp_wmb(); 511 * ptep->pte_low = l; 512 * 513 * And present to not present goes: 514 * 515 * ptep->pte_low = 0; 516 * smp_wmb(); 517 * ptep->pte_high = 0; 518 * 519 * We must ensure here that the load of pte_low sees 'l' IFF pte_high sees 'h'. 520 * We load pte_high *after* loading pte_low, which ensures we don't see an older 521 * value of pte_high. *Then* we recheck pte_low, which ensures that we haven't 522 * picked up a changed pte high. We might have gotten rubbish values from 523 * pte_low and pte_high, but we are guaranteed that pte_low will not have the 524 * present bit set *unless* it is 'l'. Because get_user_pages_fast() only 525 * operates on present ptes we're safe. 526 */ 527 static inline pte_t ptep_get_lockless(pte_t *ptep) 528 { 529 pte_t pte; 530 531 do { 532 pte.pte_low = ptep->pte_low; 533 smp_rmb(); 534 pte.pte_high = ptep->pte_high; 535 smp_rmb(); 536 } while (unlikely(pte.pte_low != ptep->pte_low)); 537 538 return pte; 539 } 540 #define ptep_get_lockless ptep_get_lockless 541 542 #if CONFIG_PGTABLE_LEVELS > 2 543 static inline pmd_t pmdp_get_lockless(pmd_t *pmdp) 544 { 545 pmd_t pmd; 546 547 do { 548 pmd.pmd_low = pmdp->pmd_low; 549 smp_rmb(); 550 pmd.pmd_high = pmdp->pmd_high; 551 smp_rmb(); 552 } while (unlikely(pmd.pmd_low != pmdp->pmd_low)); 553 554 return pmd; 555 } 556 #define pmdp_get_lockless pmdp_get_lockless 557 #define pmdp_get_lockless_sync() tlb_remove_table_sync_one() 558 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 559 #endif /* CONFIG_GUP_GET_PXX_LOW_HIGH */ 560 561 /* 562 * We require that the PTE can be read atomically. 563 */ 564 #ifndef ptep_get_lockless 565 static inline pte_t ptep_get_lockless(pte_t *ptep) 566 { 567 return ptep_get(ptep); 568 } 569 #endif 570 571 #ifndef pmdp_get_lockless 572 static inline pmd_t pmdp_get_lockless(pmd_t *pmdp) 573 { 574 return pmdp_get(pmdp); 575 } 576 static inline void pmdp_get_lockless_sync(void) 577 { 578 } 579 #endif 580 581 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 582 #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 583 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 584 unsigned long address, 585 pmd_t *pmdp) 586 { 587 pmd_t pmd = *pmdp; 588 589 pmd_clear(pmdp); 590 page_table_check_pmd_clear(mm, pmd); 591 592 return pmd; 593 } 594 #endif /* __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR */ 595 #ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR 596 static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm, 597 unsigned long address, 598 pud_t *pudp) 599 { 600 pud_t pud = *pudp; 601 602 pud_clear(pudp); 603 page_table_check_pud_clear(mm, pud); 604 605 return pud; 606 } 607 #endif /* __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR */ 608 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 609 610 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 611 #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 612 static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 613 unsigned long address, pmd_t *pmdp, 614 int full) 615 { 616 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); 617 } 618 #endif 619 620 #ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR_FULL 621 static inline pud_t pudp_huge_get_and_clear_full(struct vm_area_struct *vma, 622 unsigned long address, pud_t *pudp, 623 int full) 624 { 625 return pudp_huge_get_and_clear(vma->vm_mm, address, pudp); 626 } 627 #endif 628 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 629 630 #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 631 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 632 unsigned long address, pte_t *ptep, 633 int full) 634 { 635 return ptep_get_and_clear(mm, address, ptep); 636 } 637 #endif 638 639 #ifndef get_and_clear_full_ptes 640 /** 641 * get_and_clear_full_ptes - Clear present PTEs that map consecutive pages of 642 * the same folio, collecting dirty/accessed bits. 643 * @mm: Address space the pages are mapped into. 644 * @addr: Address the first page is mapped at. 645 * @ptep: Page table pointer for the first entry. 646 * @nr: Number of entries to clear. 647 * @full: Whether we are clearing a full mm. 648 * 649 * May be overridden by the architecture; otherwise, implemented as a simple 650 * loop over ptep_get_and_clear_full(), merging dirty/accessed bits into the 651 * returned PTE. 652 * 653 * Note that PTE bits in the PTE range besides the PFN can differ. For example, 654 * some PTEs might be write-protected. 655 * 656 * Context: The caller holds the page table lock. The PTEs map consecutive 657 * pages that belong to the same folio. The PTEs are all in the same PMD. 658 */ 659 static inline pte_t get_and_clear_full_ptes(struct mm_struct *mm, 660 unsigned long addr, pte_t *ptep, unsigned int nr, int full) 661 { 662 pte_t pte, tmp_pte; 663 664 pte = ptep_get_and_clear_full(mm, addr, ptep, full); 665 while (--nr) { 666 ptep++; 667 addr += PAGE_SIZE; 668 tmp_pte = ptep_get_and_clear_full(mm, addr, ptep, full); 669 if (pte_dirty(tmp_pte)) 670 pte = pte_mkdirty(pte); 671 if (pte_young(tmp_pte)) 672 pte = pte_mkyoung(pte); 673 } 674 return pte; 675 } 676 #endif 677 678 #ifndef clear_full_ptes 679 /** 680 * clear_full_ptes - Clear present PTEs that map consecutive pages of the same 681 * folio. 682 * @mm: Address space the pages are mapped into. 683 * @addr: Address the first page is mapped at. 684 * @ptep: Page table pointer for the first entry. 685 * @nr: Number of entries to clear. 686 * @full: Whether we are clearing a full mm. 687 * 688 * May be overridden by the architecture; otherwise, implemented as a simple 689 * loop over ptep_get_and_clear_full(). 690 * 691 * Note that PTE bits in the PTE range besides the PFN can differ. For example, 692 * some PTEs might be write-protected. 693 * 694 * Context: The caller holds the page table lock. The PTEs map consecutive 695 * pages that belong to the same folio. The PTEs are all in the same PMD. 696 */ 697 static inline void clear_full_ptes(struct mm_struct *mm, unsigned long addr, 698 pte_t *ptep, unsigned int nr, int full) 699 { 700 for (;;) { 701 ptep_get_and_clear_full(mm, addr, ptep, full); 702 if (--nr == 0) 703 break; 704 ptep++; 705 addr += PAGE_SIZE; 706 } 707 } 708 #endif 709 710 /* 711 * If two threads concurrently fault at the same page, the thread that 712 * won the race updates the PTE and its local TLB/Cache. The other thread 713 * gives up, simply does nothing, and continues; on architectures where 714 * software can update TLB, local TLB can be updated here to avoid next page 715 * fault. This function updates TLB only, do nothing with cache or others. 716 * It is the difference with function update_mmu_cache. 717 */ 718 #ifndef __HAVE_ARCH_UPDATE_MMU_TLB 719 static inline void update_mmu_tlb(struct vm_area_struct *vma, 720 unsigned long address, pte_t *ptep) 721 { 722 } 723 #define __HAVE_ARCH_UPDATE_MMU_TLB 724 #endif 725 726 /* 727 * Some architectures may be able to avoid expensive synchronization 728 * primitives when modifications are made to PTE's which are already 729 * not present, or in the process of an address space destruction. 730 */ 731 #ifndef __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL 732 static inline void pte_clear_not_present_full(struct mm_struct *mm, 733 unsigned long address, 734 pte_t *ptep, 735 int full) 736 { 737 pte_clear(mm, address, ptep); 738 } 739 #endif 740 741 #ifndef clear_not_present_full_ptes 742 /** 743 * clear_not_present_full_ptes - Clear multiple not present PTEs which are 744 * consecutive in the pgtable. 745 * @mm: Address space the ptes represent. 746 * @addr: Address of the first pte. 747 * @ptep: Page table pointer for the first entry. 748 * @nr: Number of entries to clear. 749 * @full: Whether we are clearing a full mm. 750 * 751 * May be overridden by the architecture; otherwise, implemented as a simple 752 * loop over pte_clear_not_present_full(). 753 * 754 * Context: The caller holds the page table lock. The PTEs are all not present. 755 * The PTEs are all in the same PMD. 756 */ 757 static inline void clear_not_present_full_ptes(struct mm_struct *mm, 758 unsigned long addr, pte_t *ptep, unsigned int nr, int full) 759 { 760 for (;;) { 761 pte_clear_not_present_full(mm, addr, ptep, full); 762 if (--nr == 0) 763 break; 764 ptep++; 765 addr += PAGE_SIZE; 766 } 767 } 768 #endif 769 770 #ifndef __HAVE_ARCH_PTEP_CLEAR_FLUSH 771 extern pte_t ptep_clear_flush(struct vm_area_struct *vma, 772 unsigned long address, 773 pte_t *ptep); 774 #endif 775 776 #ifndef __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH 777 extern pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, 778 unsigned long address, 779 pmd_t *pmdp); 780 extern pud_t pudp_huge_clear_flush(struct vm_area_struct *vma, 781 unsigned long address, 782 pud_t *pudp); 783 #endif 784 785 #ifndef pte_mkwrite 786 static inline pte_t pte_mkwrite(pte_t pte, struct vm_area_struct *vma) 787 { 788 return pte_mkwrite_novma(pte); 789 } 790 #endif 791 792 #if defined(CONFIG_ARCH_WANT_PMD_MKWRITE) && !defined(pmd_mkwrite) 793 static inline pmd_t pmd_mkwrite(pmd_t pmd, struct vm_area_struct *vma) 794 { 795 return pmd_mkwrite_novma(pmd); 796 } 797 #endif 798 799 #ifndef __HAVE_ARCH_PTEP_SET_WRPROTECT 800 struct mm_struct; 801 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 802 { 803 pte_t old_pte = ptep_get(ptep); 804 set_pte_at(mm, address, ptep, pte_wrprotect(old_pte)); 805 } 806 #endif 807 808 #ifndef wrprotect_ptes 809 /** 810 * wrprotect_ptes - Write-protect PTEs that map consecutive pages of the same 811 * folio. 812 * @mm: Address space the pages are mapped into. 813 * @addr: Address the first page is mapped at. 814 * @ptep: Page table pointer for the first entry. 815 * @nr: Number of entries to write-protect. 816 * 817 * May be overridden by the architecture; otherwise, implemented as a simple 818 * loop over ptep_set_wrprotect(). 819 * 820 * Note that PTE bits in the PTE range besides the PFN can differ. For example, 821 * some PTEs might be write-protected. 822 * 823 * Context: The caller holds the page table lock. The PTEs map consecutive 824 * pages that belong to the same folio. The PTEs are all in the same PMD. 825 */ 826 static inline void wrprotect_ptes(struct mm_struct *mm, unsigned long addr, 827 pte_t *ptep, unsigned int nr) 828 { 829 for (;;) { 830 ptep_set_wrprotect(mm, addr, ptep); 831 if (--nr == 0) 832 break; 833 ptep++; 834 addr += PAGE_SIZE; 835 } 836 } 837 #endif 838 839 /* 840 * On some architectures hardware does not set page access bit when accessing 841 * memory page, it is responsibility of software setting this bit. It brings 842 * out extra page fault penalty to track page access bit. For optimization page 843 * access bit can be set during all page fault flow on these arches. 844 * To be differentiate with macro pte_mkyoung, this macro is used on platforms 845 * where software maintains page access bit. 846 */ 847 #ifndef pte_sw_mkyoung 848 static inline pte_t pte_sw_mkyoung(pte_t pte) 849 { 850 return pte; 851 } 852 #define pte_sw_mkyoung pte_sw_mkyoung 853 #endif 854 855 #ifndef __HAVE_ARCH_PMDP_SET_WRPROTECT 856 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 857 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 858 unsigned long address, pmd_t *pmdp) 859 { 860 pmd_t old_pmd = *pmdp; 861 set_pmd_at(mm, address, pmdp, pmd_wrprotect(old_pmd)); 862 } 863 #else 864 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 865 unsigned long address, pmd_t *pmdp) 866 { 867 BUILD_BUG(); 868 } 869 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 870 #endif 871 #ifndef __HAVE_ARCH_PUDP_SET_WRPROTECT 872 #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD 873 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 874 static inline void pudp_set_wrprotect(struct mm_struct *mm, 875 unsigned long address, pud_t *pudp) 876 { 877 pud_t old_pud = *pudp; 878 879 set_pud_at(mm, address, pudp, pud_wrprotect(old_pud)); 880 } 881 #else 882 static inline void pudp_set_wrprotect(struct mm_struct *mm, 883 unsigned long address, pud_t *pudp) 884 { 885 BUILD_BUG(); 886 } 887 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 888 #endif /* CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD */ 889 #endif 890 891 #ifndef pmdp_collapse_flush 892 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 893 extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 894 unsigned long address, pmd_t *pmdp); 895 #else 896 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 897 unsigned long address, 898 pmd_t *pmdp) 899 { 900 BUILD_BUG(); 901 return *pmdp; 902 } 903 #define pmdp_collapse_flush pmdp_collapse_flush 904 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 905 #endif 906 907 #ifndef __HAVE_ARCH_PGTABLE_DEPOSIT 908 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 909 pgtable_t pgtable); 910 #endif 911 912 #ifndef __HAVE_ARCH_PGTABLE_WITHDRAW 913 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 914 #endif 915 916 #ifndef arch_needs_pgtable_deposit 917 #define arch_needs_pgtable_deposit() (false) 918 #endif 919 920 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 921 /* 922 * This is an implementation of pmdp_establish() that is only suitable for an 923 * architecture that doesn't have hardware dirty/accessed bits. In this case we 924 * can't race with CPU which sets these bits and non-atomic approach is fine. 925 */ 926 static inline pmd_t generic_pmdp_establish(struct vm_area_struct *vma, 927 unsigned long address, pmd_t *pmdp, pmd_t pmd) 928 { 929 pmd_t old_pmd = *pmdp; 930 set_pmd_at(vma->vm_mm, address, pmdp, pmd); 931 return old_pmd; 932 } 933 #endif 934 935 #ifndef __HAVE_ARCH_PMDP_INVALIDATE 936 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 937 pmd_t *pmdp); 938 #endif 939 940 #ifndef __HAVE_ARCH_PMDP_INVALIDATE_AD 941 942 /* 943 * pmdp_invalidate_ad() invalidates the PMD while changing a transparent 944 * hugepage mapping in the page tables. This function is similar to 945 * pmdp_invalidate(), but should only be used if the access and dirty bits would 946 * not be cleared by the software in the new PMD value. The function ensures 947 * that hardware changes of the access and dirty bits updates would not be lost. 948 * 949 * Doing so can allow in certain architectures to avoid a TLB flush in most 950 * cases. Yet, another TLB flush might be necessary later if the PMD update 951 * itself requires such flush (e.g., if protection was set to be stricter). Yet, 952 * even when a TLB flush is needed because of the update, the caller may be able 953 * to batch these TLB flushing operations, so fewer TLB flush operations are 954 * needed. 955 */ 956 extern pmd_t pmdp_invalidate_ad(struct vm_area_struct *vma, 957 unsigned long address, pmd_t *pmdp); 958 #endif 959 960 #ifndef __HAVE_ARCH_PTE_SAME 961 static inline int pte_same(pte_t pte_a, pte_t pte_b) 962 { 963 return pte_val(pte_a) == pte_val(pte_b); 964 } 965 #endif 966 967 #ifndef __HAVE_ARCH_PTE_UNUSED 968 /* 969 * Some architectures provide facilities to virtualization guests 970 * so that they can flag allocated pages as unused. This allows the 971 * host to transparently reclaim unused pages. This function returns 972 * whether the pte's page is unused. 973 */ 974 static inline int pte_unused(pte_t pte) 975 { 976 return 0; 977 } 978 #endif 979 980 #ifndef pte_access_permitted 981 #define pte_access_permitted(pte, write) \ 982 (pte_present(pte) && (!(write) || pte_write(pte))) 983 #endif 984 985 #ifndef pmd_access_permitted 986 #define pmd_access_permitted(pmd, write) \ 987 (pmd_present(pmd) && (!(write) || pmd_write(pmd))) 988 #endif 989 990 #ifndef pud_access_permitted 991 #define pud_access_permitted(pud, write) \ 992 (pud_present(pud) && (!(write) || pud_write(pud))) 993 #endif 994 995 #ifndef p4d_access_permitted 996 #define p4d_access_permitted(p4d, write) \ 997 (p4d_present(p4d) && (!(write) || p4d_write(p4d))) 998 #endif 999 1000 #ifndef pgd_access_permitted 1001 #define pgd_access_permitted(pgd, write) \ 1002 (pgd_present(pgd) && (!(write) || pgd_write(pgd))) 1003 #endif 1004 1005 #ifndef __HAVE_ARCH_PMD_SAME 1006 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 1007 { 1008 return pmd_val(pmd_a) == pmd_val(pmd_b); 1009 } 1010 #endif 1011 1012 #ifndef pud_same 1013 static inline int pud_same(pud_t pud_a, pud_t pud_b) 1014 { 1015 return pud_val(pud_a) == pud_val(pud_b); 1016 } 1017 #define pud_same pud_same 1018 #endif 1019 1020 #ifndef __HAVE_ARCH_P4D_SAME 1021 static inline int p4d_same(p4d_t p4d_a, p4d_t p4d_b) 1022 { 1023 return p4d_val(p4d_a) == p4d_val(p4d_b); 1024 } 1025 #endif 1026 1027 #ifndef __HAVE_ARCH_PGD_SAME 1028 static inline int pgd_same(pgd_t pgd_a, pgd_t pgd_b) 1029 { 1030 return pgd_val(pgd_a) == pgd_val(pgd_b); 1031 } 1032 #endif 1033 1034 /* 1035 * Use set_p*_safe(), and elide TLB flushing, when confident that *no* 1036 * TLB flush will be required as a result of the "set". For example, use 1037 * in scenarios where it is known ahead of time that the routine is 1038 * setting non-present entries, or re-setting an existing entry to the 1039 * same value. Otherwise, use the typical "set" helpers and flush the 1040 * TLB. 1041 */ 1042 #define set_pte_safe(ptep, pte) \ 1043 ({ \ 1044 WARN_ON_ONCE(pte_present(*ptep) && !pte_same(*ptep, pte)); \ 1045 set_pte(ptep, pte); \ 1046 }) 1047 1048 #define set_pmd_safe(pmdp, pmd) \ 1049 ({ \ 1050 WARN_ON_ONCE(pmd_present(*pmdp) && !pmd_same(*pmdp, pmd)); \ 1051 set_pmd(pmdp, pmd); \ 1052 }) 1053 1054 #define set_pud_safe(pudp, pud) \ 1055 ({ \ 1056 WARN_ON_ONCE(pud_present(*pudp) && !pud_same(*pudp, pud)); \ 1057 set_pud(pudp, pud); \ 1058 }) 1059 1060 #define set_p4d_safe(p4dp, p4d) \ 1061 ({ \ 1062 WARN_ON_ONCE(p4d_present(*p4dp) && !p4d_same(*p4dp, p4d)); \ 1063 set_p4d(p4dp, p4d); \ 1064 }) 1065 1066 #define set_pgd_safe(pgdp, pgd) \ 1067 ({ \ 1068 WARN_ON_ONCE(pgd_present(*pgdp) && !pgd_same(*pgdp, pgd)); \ 1069 set_pgd(pgdp, pgd); \ 1070 }) 1071 1072 #ifndef __HAVE_ARCH_DO_SWAP_PAGE 1073 /* 1074 * Some architectures support metadata associated with a page. When a 1075 * page is being swapped out, this metadata must be saved so it can be 1076 * restored when the page is swapped back in. SPARC M7 and newer 1077 * processors support an ADI (Application Data Integrity) tag for the 1078 * page as metadata for the page. arch_do_swap_page() can restore this 1079 * metadata when a page is swapped back in. 1080 */ 1081 static inline void arch_do_swap_page(struct mm_struct *mm, 1082 struct vm_area_struct *vma, 1083 unsigned long addr, 1084 pte_t pte, pte_t oldpte) 1085 { 1086 1087 } 1088 #endif 1089 1090 #ifndef __HAVE_ARCH_UNMAP_ONE 1091 /* 1092 * Some architectures support metadata associated with a page. When a 1093 * page is being swapped out, this metadata must be saved so it can be 1094 * restored when the page is swapped back in. SPARC M7 and newer 1095 * processors support an ADI (Application Data Integrity) tag for the 1096 * page as metadata for the page. arch_unmap_one() can save this 1097 * metadata on a swap-out of a page. 1098 */ 1099 static inline int arch_unmap_one(struct mm_struct *mm, 1100 struct vm_area_struct *vma, 1101 unsigned long addr, 1102 pte_t orig_pte) 1103 { 1104 return 0; 1105 } 1106 #endif 1107 1108 /* 1109 * Allow architectures to preserve additional metadata associated with 1110 * swapped-out pages. The corresponding __HAVE_ARCH_SWAP_* macros and function 1111 * prototypes must be defined in the arch-specific asm/pgtable.h file. 1112 */ 1113 #ifndef __HAVE_ARCH_PREPARE_TO_SWAP 1114 static inline int arch_prepare_to_swap(struct folio *folio) 1115 { 1116 return 0; 1117 } 1118 #endif 1119 1120 #ifndef __HAVE_ARCH_SWAP_INVALIDATE 1121 static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 1122 { 1123 } 1124 1125 static inline void arch_swap_invalidate_area(int type) 1126 { 1127 } 1128 #endif 1129 1130 #ifndef __HAVE_ARCH_SWAP_RESTORE 1131 static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio) 1132 { 1133 } 1134 #endif 1135 1136 #ifndef __HAVE_ARCH_PGD_OFFSET_GATE 1137 #define pgd_offset_gate(mm, addr) pgd_offset(mm, addr) 1138 #endif 1139 1140 #ifndef __HAVE_ARCH_MOVE_PTE 1141 #define move_pte(pte, old_addr, new_addr) (pte) 1142 #endif 1143 1144 #ifndef pte_accessible 1145 # define pte_accessible(mm, pte) ((void)(pte), 1) 1146 #endif 1147 1148 #ifndef flush_tlb_fix_spurious_fault 1149 #define flush_tlb_fix_spurious_fault(vma, address, ptep) flush_tlb_page(vma, address) 1150 #endif 1151 1152 /* 1153 * When walking page tables, get the address of the next boundary, 1154 * or the end address of the range if that comes earlier. Although no 1155 * vma end wraps to 0, rounded up __boundary may wrap to 0 throughout. 1156 */ 1157 1158 #define pgd_addr_end(addr, end) \ 1159 ({ unsigned long __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK; \ 1160 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 1161 }) 1162 1163 #ifndef p4d_addr_end 1164 #define p4d_addr_end(addr, end) \ 1165 ({ unsigned long __boundary = ((addr) + P4D_SIZE) & P4D_MASK; \ 1166 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 1167 }) 1168 #endif 1169 1170 #ifndef pud_addr_end 1171 #define pud_addr_end(addr, end) \ 1172 ({ unsigned long __boundary = ((addr) + PUD_SIZE) & PUD_MASK; \ 1173 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 1174 }) 1175 #endif 1176 1177 #ifndef pmd_addr_end 1178 #define pmd_addr_end(addr, end) \ 1179 ({ unsigned long __boundary = ((addr) + PMD_SIZE) & PMD_MASK; \ 1180 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 1181 }) 1182 #endif 1183 1184 /* 1185 * When walking page tables, we usually want to skip any p?d_none entries; 1186 * and any p?d_bad entries - reporting the error before resetting to none. 1187 * Do the tests inline, but report and clear the bad entry in mm/memory.c. 1188 */ 1189 void pgd_clear_bad(pgd_t *); 1190 1191 #ifndef __PAGETABLE_P4D_FOLDED 1192 void p4d_clear_bad(p4d_t *); 1193 #else 1194 #define p4d_clear_bad(p4d) do { } while (0) 1195 #endif 1196 1197 #ifndef __PAGETABLE_PUD_FOLDED 1198 void pud_clear_bad(pud_t *); 1199 #else 1200 #define pud_clear_bad(p4d) do { } while (0) 1201 #endif 1202 1203 void pmd_clear_bad(pmd_t *); 1204 1205 static inline int pgd_none_or_clear_bad(pgd_t *pgd) 1206 { 1207 if (pgd_none(*pgd)) 1208 return 1; 1209 if (unlikely(pgd_bad(*pgd))) { 1210 pgd_clear_bad(pgd); 1211 return 1; 1212 } 1213 return 0; 1214 } 1215 1216 static inline int p4d_none_or_clear_bad(p4d_t *p4d) 1217 { 1218 if (p4d_none(*p4d)) 1219 return 1; 1220 if (unlikely(p4d_bad(*p4d))) { 1221 p4d_clear_bad(p4d); 1222 return 1; 1223 } 1224 return 0; 1225 } 1226 1227 static inline int pud_none_or_clear_bad(pud_t *pud) 1228 { 1229 if (pud_none(*pud)) 1230 return 1; 1231 if (unlikely(pud_bad(*pud))) { 1232 pud_clear_bad(pud); 1233 return 1; 1234 } 1235 return 0; 1236 } 1237 1238 static inline int pmd_none_or_clear_bad(pmd_t *pmd) 1239 { 1240 if (pmd_none(*pmd)) 1241 return 1; 1242 if (unlikely(pmd_bad(*pmd))) { 1243 pmd_clear_bad(pmd); 1244 return 1; 1245 } 1246 return 0; 1247 } 1248 1249 static inline pte_t __ptep_modify_prot_start(struct vm_area_struct *vma, 1250 unsigned long addr, 1251 pte_t *ptep) 1252 { 1253 /* 1254 * Get the current pte state, but zero it out to make it 1255 * non-present, preventing the hardware from asynchronously 1256 * updating it. 1257 */ 1258 return ptep_get_and_clear(vma->vm_mm, addr, ptep); 1259 } 1260 1261 static inline void __ptep_modify_prot_commit(struct vm_area_struct *vma, 1262 unsigned long addr, 1263 pte_t *ptep, pte_t pte) 1264 { 1265 /* 1266 * The pte is non-present, so there's no hardware state to 1267 * preserve. 1268 */ 1269 set_pte_at(vma->vm_mm, addr, ptep, pte); 1270 } 1271 1272 #ifndef __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1273 /* 1274 * Start a pte protection read-modify-write transaction, which 1275 * protects against asynchronous hardware modifications to the pte. 1276 * The intention is not to prevent the hardware from making pte 1277 * updates, but to prevent any updates it may make from being lost. 1278 * 1279 * This does not protect against other software modifications of the 1280 * pte; the appropriate pte lock must be held over the transaction. 1281 * 1282 * Note that this interface is intended to be batchable, meaning that 1283 * ptep_modify_prot_commit may not actually update the pte, but merely 1284 * queue the update to be done at some later time. The update must be 1285 * actually committed before the pte lock is released, however. 1286 */ 1287 static inline pte_t ptep_modify_prot_start(struct vm_area_struct *vma, 1288 unsigned long addr, 1289 pte_t *ptep) 1290 { 1291 return __ptep_modify_prot_start(vma, addr, ptep); 1292 } 1293 1294 /* 1295 * Commit an update to a pte, leaving any hardware-controlled bits in 1296 * the PTE unmodified. 1297 */ 1298 static inline void ptep_modify_prot_commit(struct vm_area_struct *vma, 1299 unsigned long addr, 1300 pte_t *ptep, pte_t old_pte, pte_t pte) 1301 { 1302 __ptep_modify_prot_commit(vma, addr, ptep, pte); 1303 } 1304 #endif /* __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION */ 1305 #endif /* CONFIG_MMU */ 1306 1307 /* 1308 * No-op macros that just return the current protection value. Defined here 1309 * because these macros can be used even if CONFIG_MMU is not defined. 1310 */ 1311 1312 #ifndef pgprot_nx 1313 #define pgprot_nx(prot) (prot) 1314 #endif 1315 1316 #ifndef pgprot_noncached 1317 #define pgprot_noncached(prot) (prot) 1318 #endif 1319 1320 #ifndef pgprot_writecombine 1321 #define pgprot_writecombine pgprot_noncached 1322 #endif 1323 1324 #ifndef pgprot_writethrough 1325 #define pgprot_writethrough pgprot_noncached 1326 #endif 1327 1328 #ifndef pgprot_device 1329 #define pgprot_device pgprot_noncached 1330 #endif 1331 1332 #ifndef pgprot_mhp 1333 #define pgprot_mhp(prot) (prot) 1334 #endif 1335 1336 #ifdef CONFIG_MMU 1337 #ifndef pgprot_modify 1338 #define pgprot_modify pgprot_modify 1339 static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot) 1340 { 1341 if (pgprot_val(oldprot) == pgprot_val(pgprot_noncached(oldprot))) 1342 newprot = pgprot_noncached(newprot); 1343 if (pgprot_val(oldprot) == pgprot_val(pgprot_writecombine(oldprot))) 1344 newprot = pgprot_writecombine(newprot); 1345 if (pgprot_val(oldprot) == pgprot_val(pgprot_device(oldprot))) 1346 newprot = pgprot_device(newprot); 1347 return newprot; 1348 } 1349 #endif 1350 #endif /* CONFIG_MMU */ 1351 1352 #ifndef pgprot_encrypted 1353 #define pgprot_encrypted(prot) (prot) 1354 #endif 1355 1356 #ifndef pgprot_decrypted 1357 #define pgprot_decrypted(prot) (prot) 1358 #endif 1359 1360 /* 1361 * A facility to provide batching of the reload of page tables and 1362 * other process state with the actual context switch code for 1363 * paravirtualized guests. By convention, only one of the batched 1364 * update (lazy) modes (CPU, MMU) should be active at any given time, 1365 * entry should never be nested, and entry and exits should always be 1366 * paired. This is for sanity of maintaining and reasoning about the 1367 * kernel code. In this case, the exit (end of the context switch) is 1368 * in architecture-specific code, and so doesn't need a generic 1369 * definition. 1370 */ 1371 #ifndef __HAVE_ARCH_START_CONTEXT_SWITCH 1372 #define arch_start_context_switch(prev) do {} while (0) 1373 #endif 1374 1375 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1376 #ifndef CONFIG_ARCH_ENABLE_THP_MIGRATION 1377 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) 1378 { 1379 return pmd; 1380 } 1381 1382 static inline int pmd_swp_soft_dirty(pmd_t pmd) 1383 { 1384 return 0; 1385 } 1386 1387 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) 1388 { 1389 return pmd; 1390 } 1391 #endif 1392 #else /* !CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1393 static inline int pte_soft_dirty(pte_t pte) 1394 { 1395 return 0; 1396 } 1397 1398 static inline int pmd_soft_dirty(pmd_t pmd) 1399 { 1400 return 0; 1401 } 1402 1403 static inline pte_t pte_mksoft_dirty(pte_t pte) 1404 { 1405 return pte; 1406 } 1407 1408 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 1409 { 1410 return pmd; 1411 } 1412 1413 static inline pte_t pte_clear_soft_dirty(pte_t pte) 1414 { 1415 return pte; 1416 } 1417 1418 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 1419 { 1420 return pmd; 1421 } 1422 1423 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 1424 { 1425 return pte; 1426 } 1427 1428 static inline int pte_swp_soft_dirty(pte_t pte) 1429 { 1430 return 0; 1431 } 1432 1433 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 1434 { 1435 return pte; 1436 } 1437 1438 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) 1439 { 1440 return pmd; 1441 } 1442 1443 static inline int pmd_swp_soft_dirty(pmd_t pmd) 1444 { 1445 return 0; 1446 } 1447 1448 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) 1449 { 1450 return pmd; 1451 } 1452 #endif 1453 1454 #ifndef __HAVE_PFNMAP_TRACKING 1455 /* 1456 * Interfaces that can be used by architecture code to keep track of 1457 * memory type of pfn mappings specified by the remap_pfn_range, 1458 * vmf_insert_pfn. 1459 */ 1460 1461 /* 1462 * track_pfn_remap is called when a _new_ pfn mapping is being established 1463 * by remap_pfn_range() for physical range indicated by pfn and size. 1464 */ 1465 static inline int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot, 1466 unsigned long pfn, unsigned long addr, 1467 unsigned long size) 1468 { 1469 return 0; 1470 } 1471 1472 /* 1473 * track_pfn_insert is called when a _new_ single pfn is established 1474 * by vmf_insert_pfn(). 1475 */ 1476 static inline void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot, 1477 pfn_t pfn) 1478 { 1479 } 1480 1481 /* 1482 * track_pfn_copy is called when vma that is covering the pfnmap gets 1483 * copied through copy_page_range(). 1484 */ 1485 static inline int track_pfn_copy(struct vm_area_struct *vma) 1486 { 1487 return 0; 1488 } 1489 1490 /* 1491 * untrack_pfn is called while unmapping a pfnmap for a region. 1492 * untrack can be called for a specific region indicated by pfn and size or 1493 * can be for the entire vma (in which case pfn, size are zero). 1494 */ 1495 static inline void untrack_pfn(struct vm_area_struct *vma, 1496 unsigned long pfn, unsigned long size, 1497 bool mm_wr_locked) 1498 { 1499 } 1500 1501 /* 1502 * untrack_pfn_clear is called while mremapping a pfnmap for a new region 1503 * or fails to copy pgtable during duplicate vm area. 1504 */ 1505 static inline void untrack_pfn_clear(struct vm_area_struct *vma) 1506 { 1507 } 1508 #else 1509 extern int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot, 1510 unsigned long pfn, unsigned long addr, 1511 unsigned long size); 1512 extern void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot, 1513 pfn_t pfn); 1514 extern int track_pfn_copy(struct vm_area_struct *vma); 1515 extern void untrack_pfn(struct vm_area_struct *vma, unsigned long pfn, 1516 unsigned long size, bool mm_wr_locked); 1517 extern void untrack_pfn_clear(struct vm_area_struct *vma); 1518 #endif 1519 1520 #ifdef CONFIG_MMU 1521 #ifdef __HAVE_COLOR_ZERO_PAGE 1522 static inline int is_zero_pfn(unsigned long pfn) 1523 { 1524 extern unsigned long zero_pfn; 1525 unsigned long offset_from_zero_pfn = pfn - zero_pfn; 1526 return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT); 1527 } 1528 1529 #define my_zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr)) 1530 1531 #else 1532 static inline int is_zero_pfn(unsigned long pfn) 1533 { 1534 extern unsigned long zero_pfn; 1535 return pfn == zero_pfn; 1536 } 1537 1538 static inline unsigned long my_zero_pfn(unsigned long addr) 1539 { 1540 extern unsigned long zero_pfn; 1541 return zero_pfn; 1542 } 1543 #endif 1544 #else 1545 static inline int is_zero_pfn(unsigned long pfn) 1546 { 1547 return 0; 1548 } 1549 1550 static inline unsigned long my_zero_pfn(unsigned long addr) 1551 { 1552 return 0; 1553 } 1554 #endif /* CONFIG_MMU */ 1555 1556 #ifdef CONFIG_MMU 1557 1558 #ifndef CONFIG_TRANSPARENT_HUGEPAGE 1559 static inline int pmd_trans_huge(pmd_t pmd) 1560 { 1561 return 0; 1562 } 1563 #ifndef pmd_write 1564 static inline int pmd_write(pmd_t pmd) 1565 { 1566 BUG(); 1567 return 0; 1568 } 1569 #endif /* pmd_write */ 1570 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1571 1572 #ifndef pud_write 1573 static inline int pud_write(pud_t pud) 1574 { 1575 BUG(); 1576 return 0; 1577 } 1578 #endif /* pud_write */ 1579 1580 #if !defined(CONFIG_ARCH_HAS_PTE_DEVMAP) || !defined(CONFIG_TRANSPARENT_HUGEPAGE) 1581 static inline int pmd_devmap(pmd_t pmd) 1582 { 1583 return 0; 1584 } 1585 static inline int pud_devmap(pud_t pud) 1586 { 1587 return 0; 1588 } 1589 static inline int pgd_devmap(pgd_t pgd) 1590 { 1591 return 0; 1592 } 1593 #endif 1594 1595 #if !defined(CONFIG_TRANSPARENT_HUGEPAGE) || \ 1596 !defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) 1597 static inline int pud_trans_huge(pud_t pud) 1598 { 1599 return 0; 1600 } 1601 #endif 1602 1603 static inline int pud_trans_unstable(pud_t *pud) 1604 { 1605 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) && \ 1606 defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) 1607 pud_t pudval = READ_ONCE(*pud); 1608 1609 if (pud_none(pudval) || pud_trans_huge(pudval) || pud_devmap(pudval)) 1610 return 1; 1611 if (unlikely(pud_bad(pudval))) { 1612 pud_clear_bad(pud); 1613 return 1; 1614 } 1615 #endif 1616 return 0; 1617 } 1618 1619 #ifndef CONFIG_NUMA_BALANCING 1620 /* 1621 * In an inaccessible (PROT_NONE) VMA, pte_protnone() may indicate "yes". It is 1622 * perfectly valid to indicate "no" in that case, which is why our default 1623 * implementation defaults to "always no". 1624 * 1625 * In an accessible VMA, however, pte_protnone() reliably indicates PROT_NONE 1626 * page protection due to NUMA hinting. NUMA hinting faults only apply in 1627 * accessible VMAs. 1628 * 1629 * So, to reliably identify PROT_NONE PTEs that require a NUMA hinting fault, 1630 * looking at the VMA accessibility is sufficient. 1631 */ 1632 static inline int pte_protnone(pte_t pte) 1633 { 1634 return 0; 1635 } 1636 1637 static inline int pmd_protnone(pmd_t pmd) 1638 { 1639 return 0; 1640 } 1641 #endif /* CONFIG_NUMA_BALANCING */ 1642 1643 #endif /* CONFIG_MMU */ 1644 1645 #ifdef CONFIG_HAVE_ARCH_HUGE_VMAP 1646 1647 #ifndef __PAGETABLE_P4D_FOLDED 1648 int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot); 1649 void p4d_clear_huge(p4d_t *p4d); 1650 #else 1651 static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot) 1652 { 1653 return 0; 1654 } 1655 static inline void p4d_clear_huge(p4d_t *p4d) { } 1656 #endif /* !__PAGETABLE_P4D_FOLDED */ 1657 1658 int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot); 1659 int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot); 1660 int pud_clear_huge(pud_t *pud); 1661 int pmd_clear_huge(pmd_t *pmd); 1662 int p4d_free_pud_page(p4d_t *p4d, unsigned long addr); 1663 int pud_free_pmd_page(pud_t *pud, unsigned long addr); 1664 int pmd_free_pte_page(pmd_t *pmd, unsigned long addr); 1665 #else /* !CONFIG_HAVE_ARCH_HUGE_VMAP */ 1666 static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot) 1667 { 1668 return 0; 1669 } 1670 static inline int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot) 1671 { 1672 return 0; 1673 } 1674 static inline int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot) 1675 { 1676 return 0; 1677 } 1678 static inline void p4d_clear_huge(p4d_t *p4d) { } 1679 static inline int pud_clear_huge(pud_t *pud) 1680 { 1681 return 0; 1682 } 1683 static inline int pmd_clear_huge(pmd_t *pmd) 1684 { 1685 return 0; 1686 } 1687 static inline int p4d_free_pud_page(p4d_t *p4d, unsigned long addr) 1688 { 1689 return 0; 1690 } 1691 static inline int pud_free_pmd_page(pud_t *pud, unsigned long addr) 1692 { 1693 return 0; 1694 } 1695 static inline int pmd_free_pte_page(pmd_t *pmd, unsigned long addr) 1696 { 1697 return 0; 1698 } 1699 #endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */ 1700 1701 #ifndef __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 1702 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1703 /* 1704 * ARCHes with special requirements for evicting THP backing TLB entries can 1705 * implement this. Otherwise also, it can help optimize normal TLB flush in 1706 * THP regime. Stock flush_tlb_range() typically has optimization to nuke the 1707 * entire TLB if flush span is greater than a threshold, which will 1708 * likely be true for a single huge page. Thus a single THP flush will 1709 * invalidate the entire TLB which is not desirable. 1710 * e.g. see arch/arc: flush_pmd_tlb_range 1711 */ 1712 #define flush_pmd_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end) 1713 #define flush_pud_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end) 1714 #else 1715 #define flush_pmd_tlb_range(vma, addr, end) BUILD_BUG() 1716 #define flush_pud_tlb_range(vma, addr, end) BUILD_BUG() 1717 #endif 1718 #endif 1719 1720 struct file; 1721 int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn, 1722 unsigned long size, pgprot_t *vma_prot); 1723 1724 #ifndef CONFIG_X86_ESPFIX64 1725 static inline void init_espfix_bsp(void) { } 1726 #endif 1727 1728 extern void __init pgtable_cache_init(void); 1729 1730 #ifndef __HAVE_ARCH_PFN_MODIFY_ALLOWED 1731 static inline bool pfn_modify_allowed(unsigned long pfn, pgprot_t prot) 1732 { 1733 return true; 1734 } 1735 1736 static inline bool arch_has_pfn_modify_check(void) 1737 { 1738 return false; 1739 } 1740 #endif /* !_HAVE_ARCH_PFN_MODIFY_ALLOWED */ 1741 1742 /* 1743 * Architecture PAGE_KERNEL_* fallbacks 1744 * 1745 * Some architectures don't define certain PAGE_KERNEL_* flags. This is either 1746 * because they really don't support them, or the port needs to be updated to 1747 * reflect the required functionality. Below are a set of relatively safe 1748 * fallbacks, as best effort, which we can count on in lieu of the architectures 1749 * not defining them on their own yet. 1750 */ 1751 1752 #ifndef PAGE_KERNEL_RO 1753 # define PAGE_KERNEL_RO PAGE_KERNEL 1754 #endif 1755 1756 #ifndef PAGE_KERNEL_EXEC 1757 # define PAGE_KERNEL_EXEC PAGE_KERNEL 1758 #endif 1759 1760 /* 1761 * Page Table Modification bits for pgtbl_mod_mask. 1762 * 1763 * These are used by the p?d_alloc_track*() set of functions an in the generic 1764 * vmalloc/ioremap code to track at which page-table levels entries have been 1765 * modified. Based on that the code can better decide when vmalloc and ioremap 1766 * mapping changes need to be synchronized to other page-tables in the system. 1767 */ 1768 #define __PGTBL_PGD_MODIFIED 0 1769 #define __PGTBL_P4D_MODIFIED 1 1770 #define __PGTBL_PUD_MODIFIED 2 1771 #define __PGTBL_PMD_MODIFIED 3 1772 #define __PGTBL_PTE_MODIFIED 4 1773 1774 #define PGTBL_PGD_MODIFIED BIT(__PGTBL_PGD_MODIFIED) 1775 #define PGTBL_P4D_MODIFIED BIT(__PGTBL_P4D_MODIFIED) 1776 #define PGTBL_PUD_MODIFIED BIT(__PGTBL_PUD_MODIFIED) 1777 #define PGTBL_PMD_MODIFIED BIT(__PGTBL_PMD_MODIFIED) 1778 #define PGTBL_PTE_MODIFIED BIT(__PGTBL_PTE_MODIFIED) 1779 1780 /* Page-Table Modification Mask */ 1781 typedef unsigned int pgtbl_mod_mask; 1782 1783 #endif /* !__ASSEMBLY__ */ 1784 1785 #if !defined(MAX_POSSIBLE_PHYSMEM_BITS) && !defined(CONFIG_64BIT) 1786 #ifdef CONFIG_PHYS_ADDR_T_64BIT 1787 /* 1788 * ZSMALLOC needs to know the highest PFN on 32-bit architectures 1789 * with physical address space extension, but falls back to 1790 * BITS_PER_LONG otherwise. 1791 */ 1792 #error Missing MAX_POSSIBLE_PHYSMEM_BITS definition 1793 #else 1794 #define MAX_POSSIBLE_PHYSMEM_BITS 32 1795 #endif 1796 #endif 1797 1798 #ifndef has_transparent_hugepage 1799 #define has_transparent_hugepage() IS_BUILTIN(CONFIG_TRANSPARENT_HUGEPAGE) 1800 #endif 1801 1802 #ifndef has_transparent_pud_hugepage 1803 #define has_transparent_pud_hugepage() IS_BUILTIN(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) 1804 #endif 1805 /* 1806 * On some architectures it depends on the mm if the p4d/pud or pmd 1807 * layer of the page table hierarchy is folded or not. 1808 */ 1809 #ifndef mm_p4d_folded 1810 #define mm_p4d_folded(mm) __is_defined(__PAGETABLE_P4D_FOLDED) 1811 #endif 1812 1813 #ifndef mm_pud_folded 1814 #define mm_pud_folded(mm) __is_defined(__PAGETABLE_PUD_FOLDED) 1815 #endif 1816 1817 #ifndef mm_pmd_folded 1818 #define mm_pmd_folded(mm) __is_defined(__PAGETABLE_PMD_FOLDED) 1819 #endif 1820 1821 #ifndef p4d_offset_lockless 1822 #define p4d_offset_lockless(pgdp, pgd, address) p4d_offset(&(pgd), address) 1823 #endif 1824 #ifndef pud_offset_lockless 1825 #define pud_offset_lockless(p4dp, p4d, address) pud_offset(&(p4d), address) 1826 #endif 1827 #ifndef pmd_offset_lockless 1828 #define pmd_offset_lockless(pudp, pud, address) pmd_offset(&(pud), address) 1829 #endif 1830 1831 /* 1832 * pXd_leaf() is the API to check whether a pgtable entry is a huge page 1833 * mapping. It should work globally across all archs, without any 1834 * dependency on CONFIG_* options. For architectures that do not support 1835 * huge mappings on specific levels, below fallbacks will be used. 1836 * 1837 * A leaf pgtable entry should always imply the following: 1838 * 1839 * - It is a "present" entry. IOW, before using this API, please check it 1840 * with pXd_present() first. NOTE: it may not always mean the "present 1841 * bit" is set. For example, PROT_NONE entries are always "present". 1842 * 1843 * - It should _never_ be a swap entry of any type. Above "present" check 1844 * should have guarded this, but let's be crystal clear on this. 1845 * 1846 * - It should contain a huge PFN, which points to a huge page larger than 1847 * PAGE_SIZE of the platform. The PFN format isn't important here. 1848 * 1849 * - It should cover all kinds of huge mappings (e.g., pXd_trans_huge(), 1850 * pXd_devmap(), or hugetlb mappings). 1851 */ 1852 #ifndef pgd_leaf 1853 #define pgd_leaf(x) false 1854 #endif 1855 #ifndef p4d_leaf 1856 #define p4d_leaf(x) false 1857 #endif 1858 #ifndef pud_leaf 1859 #define pud_leaf(x) false 1860 #endif 1861 #ifndef pmd_leaf 1862 #define pmd_leaf(x) false 1863 #endif 1864 1865 #ifndef pgd_leaf_size 1866 #define pgd_leaf_size(x) (1ULL << PGDIR_SHIFT) 1867 #endif 1868 #ifndef p4d_leaf_size 1869 #define p4d_leaf_size(x) P4D_SIZE 1870 #endif 1871 #ifndef pud_leaf_size 1872 #define pud_leaf_size(x) PUD_SIZE 1873 #endif 1874 #ifndef pmd_leaf_size 1875 #define pmd_leaf_size(x) PMD_SIZE 1876 #endif 1877 #ifndef pte_leaf_size 1878 #define pte_leaf_size(x) PAGE_SIZE 1879 #endif 1880 1881 /* 1882 * We always define pmd_pfn for all archs as it's used in lots of generic 1883 * code. Now it happens too for pud_pfn (and can happen for larger 1884 * mappings too in the future; we're not there yet). Instead of defining 1885 * it for all archs (like pmd_pfn), provide a fallback. 1886 * 1887 * Note that returning 0 here means any arch that didn't define this can 1888 * get severely wrong when it hits a real pud leaf. It's arch's 1889 * responsibility to properly define it when a huge pud is possible. 1890 */ 1891 #ifndef pud_pfn 1892 #define pud_pfn(x) 0 1893 #endif 1894 1895 /* 1896 * Some architectures have MMUs that are configurable or selectable at boot 1897 * time. These lead to variable PTRS_PER_x. For statically allocated arrays it 1898 * helps to have a static maximum value. 1899 */ 1900 1901 #ifndef MAX_PTRS_PER_PTE 1902 #define MAX_PTRS_PER_PTE PTRS_PER_PTE 1903 #endif 1904 1905 #ifndef MAX_PTRS_PER_PMD 1906 #define MAX_PTRS_PER_PMD PTRS_PER_PMD 1907 #endif 1908 1909 #ifndef MAX_PTRS_PER_PUD 1910 #define MAX_PTRS_PER_PUD PTRS_PER_PUD 1911 #endif 1912 1913 #ifndef MAX_PTRS_PER_P4D 1914 #define MAX_PTRS_PER_P4D PTRS_PER_P4D 1915 #endif 1916 1917 /* description of effects of mapping type and prot in current implementation. 1918 * this is due to the limited x86 page protection hardware. The expected 1919 * behavior is in parens: 1920 * 1921 * map_type prot 1922 * PROT_NONE PROT_READ PROT_WRITE PROT_EXEC 1923 * MAP_SHARED r: (no) no r: (yes) yes r: (no) yes r: (no) yes 1924 * w: (no) no w: (no) no w: (yes) yes w: (no) no 1925 * x: (no) no x: (no) yes x: (no) yes x: (yes) yes 1926 * 1927 * MAP_PRIVATE r: (no) no r: (yes) yes r: (no) yes r: (no) yes 1928 * w: (no) no w: (no) no w: (copy) copy w: (no) no 1929 * x: (no) no x: (no) yes x: (no) yes x: (yes) yes 1930 * 1931 * On arm64, PROT_EXEC has the following behaviour for both MAP_SHARED and 1932 * MAP_PRIVATE (with Enhanced PAN supported): 1933 * r: (no) no 1934 * w: (no) no 1935 * x: (yes) yes 1936 */ 1937 #define DECLARE_VM_GET_PAGE_PROT \ 1938 pgprot_t vm_get_page_prot(unsigned long vm_flags) \ 1939 { \ 1940 return protection_map[vm_flags & \ 1941 (VM_READ | VM_WRITE | VM_EXEC | VM_SHARED)]; \ 1942 } \ 1943 EXPORT_SYMBOL(vm_get_page_prot); 1944 1945 #endif /* _LINUX_PGTABLE_H */ 1946